
STM32L476RG.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000188  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00006ad0  08000190  08000190  00010190  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000120  08006c60  08006c60  00016c60  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  08006d80  08006d80  00020084  2**0
                  CONTENTS
  4 .ARM          00000008  08006d80  08006d80  00016d80  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  08006d88  08006d88  00020084  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08006d88  08006d88  00016d88  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  08006d8c  08006d8c  00016d8c  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         00000084  20000000  08006d90  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00003eb4  20000084  08006e14  00020084  2**2
                  ALLOC
 10 ._user_heap_stack 00000600  20003f38  08006e14  00023f38  2**0
                  ALLOC
 11 .ARM.attributes 00000030  00000000  00000000  00020084  2**0
                  CONTENTS, READONLY
 12 .debug_info   0001fdb6  00000000  00000000  000200b4  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_abbrev 0000432c  00000000  00000000  0003fe6a  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_aranges 000019c8  00000000  00000000  00044198  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_ranges 00001800  00000000  00000000  00045b60  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_macro  0002abfa  00000000  00000000  00047360  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_line   0001eb4b  00000000  00000000  00071f5a  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_str    00104d4b  00000000  00000000  00090aa5  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .comment      00000050  00000000  00000000  001957f0  2**0
                  CONTENTS, READONLY
 20 .debug_frame  00006d98  00000000  00000000  00195840  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

08000190 <__do_global_dtors_aux>:
 8000190:	b510      	push	{r4, lr}
 8000192:	4c05      	ldr	r4, [pc, #20]	; (80001a8 <__do_global_dtors_aux+0x18>)
 8000194:	7823      	ldrb	r3, [r4, #0]
 8000196:	b933      	cbnz	r3, 80001a6 <__do_global_dtors_aux+0x16>
 8000198:	4b04      	ldr	r3, [pc, #16]	; (80001ac <__do_global_dtors_aux+0x1c>)
 800019a:	b113      	cbz	r3, 80001a2 <__do_global_dtors_aux+0x12>
 800019c:	4804      	ldr	r0, [pc, #16]	; (80001b0 <__do_global_dtors_aux+0x20>)
 800019e:	f3af 8000 	nop.w
 80001a2:	2301      	movs	r3, #1
 80001a4:	7023      	strb	r3, [r4, #0]
 80001a6:	bd10      	pop	{r4, pc}
 80001a8:	20000084 	.word	0x20000084
 80001ac:	00000000 	.word	0x00000000
 80001b0:	08006c48 	.word	0x08006c48

080001b4 <frame_dummy>:
 80001b4:	b508      	push	{r3, lr}
 80001b6:	4b03      	ldr	r3, [pc, #12]	; (80001c4 <frame_dummy+0x10>)
 80001b8:	b11b      	cbz	r3, 80001c2 <frame_dummy+0xe>
 80001ba:	4903      	ldr	r1, [pc, #12]	; (80001c8 <frame_dummy+0x14>)
 80001bc:	4803      	ldr	r0, [pc, #12]	; (80001cc <frame_dummy+0x18>)
 80001be:	f3af 8000 	nop.w
 80001c2:	bd08      	pop	{r3, pc}
 80001c4:	00000000 	.word	0x00000000
 80001c8:	20000088 	.word	0x20000088
 80001cc:	08006c48 	.word	0x08006c48

080001d0 <__aeabi_uldivmod>:
 80001d0:	b953      	cbnz	r3, 80001e8 <__aeabi_uldivmod+0x18>
 80001d2:	b94a      	cbnz	r2, 80001e8 <__aeabi_uldivmod+0x18>
 80001d4:	2900      	cmp	r1, #0
 80001d6:	bf08      	it	eq
 80001d8:	2800      	cmpeq	r0, #0
 80001da:	bf1c      	itt	ne
 80001dc:	f04f 31ff 	movne.w	r1, #4294967295
 80001e0:	f04f 30ff 	movne.w	r0, #4294967295
 80001e4:	f000 b974 	b.w	80004d0 <__aeabi_idiv0>
 80001e8:	f1ad 0c08 	sub.w	ip, sp, #8
 80001ec:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 80001f0:	f000 f806 	bl	8000200 <__udivmoddi4>
 80001f4:	f8dd e004 	ldr.w	lr, [sp, #4]
 80001f8:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 80001fc:	b004      	add	sp, #16
 80001fe:	4770      	bx	lr

08000200 <__udivmoddi4>:
 8000200:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8000204:	9d08      	ldr	r5, [sp, #32]
 8000206:	4604      	mov	r4, r0
 8000208:	468e      	mov	lr, r1
 800020a:	2b00      	cmp	r3, #0
 800020c:	d14d      	bne.n	80002aa <__udivmoddi4+0xaa>
 800020e:	428a      	cmp	r2, r1
 8000210:	4694      	mov	ip, r2
 8000212:	d969      	bls.n	80002e8 <__udivmoddi4+0xe8>
 8000214:	fab2 f282 	clz	r2, r2
 8000218:	b152      	cbz	r2, 8000230 <__udivmoddi4+0x30>
 800021a:	fa01 f302 	lsl.w	r3, r1, r2
 800021e:	f1c2 0120 	rsb	r1, r2, #32
 8000222:	fa20 f101 	lsr.w	r1, r0, r1
 8000226:	fa0c fc02 	lsl.w	ip, ip, r2
 800022a:	ea41 0e03 	orr.w	lr, r1, r3
 800022e:	4094      	lsls	r4, r2
 8000230:	ea4f 481c 	mov.w	r8, ip, lsr #16
 8000234:	0c21      	lsrs	r1, r4, #16
 8000236:	fbbe f6f8 	udiv	r6, lr, r8
 800023a:	fa1f f78c 	uxth.w	r7, ip
 800023e:	fb08 e316 	mls	r3, r8, r6, lr
 8000242:	ea41 4303 	orr.w	r3, r1, r3, lsl #16
 8000246:	fb06 f107 	mul.w	r1, r6, r7
 800024a:	4299      	cmp	r1, r3
 800024c:	d90a      	bls.n	8000264 <__udivmoddi4+0x64>
 800024e:	eb1c 0303 	adds.w	r3, ip, r3
 8000252:	f106 30ff 	add.w	r0, r6, #4294967295
 8000256:	f080 811f 	bcs.w	8000498 <__udivmoddi4+0x298>
 800025a:	4299      	cmp	r1, r3
 800025c:	f240 811c 	bls.w	8000498 <__udivmoddi4+0x298>
 8000260:	3e02      	subs	r6, #2
 8000262:	4463      	add	r3, ip
 8000264:	1a5b      	subs	r3, r3, r1
 8000266:	b2a4      	uxth	r4, r4
 8000268:	fbb3 f0f8 	udiv	r0, r3, r8
 800026c:	fb08 3310 	mls	r3, r8, r0, r3
 8000270:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
 8000274:	fb00 f707 	mul.w	r7, r0, r7
 8000278:	42a7      	cmp	r7, r4
 800027a:	d90a      	bls.n	8000292 <__udivmoddi4+0x92>
 800027c:	eb1c 0404 	adds.w	r4, ip, r4
 8000280:	f100 33ff 	add.w	r3, r0, #4294967295
 8000284:	f080 810a 	bcs.w	800049c <__udivmoddi4+0x29c>
 8000288:	42a7      	cmp	r7, r4
 800028a:	f240 8107 	bls.w	800049c <__udivmoddi4+0x29c>
 800028e:	4464      	add	r4, ip
 8000290:	3802      	subs	r0, #2
 8000292:	ea40 4006 	orr.w	r0, r0, r6, lsl #16
 8000296:	1be4      	subs	r4, r4, r7
 8000298:	2600      	movs	r6, #0
 800029a:	b11d      	cbz	r5, 80002a4 <__udivmoddi4+0xa4>
 800029c:	40d4      	lsrs	r4, r2
 800029e:	2300      	movs	r3, #0
 80002a0:	e9c5 4300 	strd	r4, r3, [r5]
 80002a4:	4631      	mov	r1, r6
 80002a6:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002aa:	428b      	cmp	r3, r1
 80002ac:	d909      	bls.n	80002c2 <__udivmoddi4+0xc2>
 80002ae:	2d00      	cmp	r5, #0
 80002b0:	f000 80ef 	beq.w	8000492 <__udivmoddi4+0x292>
 80002b4:	2600      	movs	r6, #0
 80002b6:	e9c5 0100 	strd	r0, r1, [r5]
 80002ba:	4630      	mov	r0, r6
 80002bc:	4631      	mov	r1, r6
 80002be:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002c2:	fab3 f683 	clz	r6, r3
 80002c6:	2e00      	cmp	r6, #0
 80002c8:	d14a      	bne.n	8000360 <__udivmoddi4+0x160>
 80002ca:	428b      	cmp	r3, r1
 80002cc:	d302      	bcc.n	80002d4 <__udivmoddi4+0xd4>
 80002ce:	4282      	cmp	r2, r0
 80002d0:	f200 80f9 	bhi.w	80004c6 <__udivmoddi4+0x2c6>
 80002d4:	1a84      	subs	r4, r0, r2
 80002d6:	eb61 0303 	sbc.w	r3, r1, r3
 80002da:	2001      	movs	r0, #1
 80002dc:	469e      	mov	lr, r3
 80002de:	2d00      	cmp	r5, #0
 80002e0:	d0e0      	beq.n	80002a4 <__udivmoddi4+0xa4>
 80002e2:	e9c5 4e00 	strd	r4, lr, [r5]
 80002e6:	e7dd      	b.n	80002a4 <__udivmoddi4+0xa4>
 80002e8:	b902      	cbnz	r2, 80002ec <__udivmoddi4+0xec>
 80002ea:	deff      	udf	#255	; 0xff
 80002ec:	fab2 f282 	clz	r2, r2
 80002f0:	2a00      	cmp	r2, #0
 80002f2:	f040 8092 	bne.w	800041a <__udivmoddi4+0x21a>
 80002f6:	eba1 010c 	sub.w	r1, r1, ip
 80002fa:	ea4f 471c 	mov.w	r7, ip, lsr #16
 80002fe:	fa1f fe8c 	uxth.w	lr, ip
 8000302:	2601      	movs	r6, #1
 8000304:	0c20      	lsrs	r0, r4, #16
 8000306:	fbb1 f3f7 	udiv	r3, r1, r7
 800030a:	fb07 1113 	mls	r1, r7, r3, r1
 800030e:	ea40 4101 	orr.w	r1, r0, r1, lsl #16
 8000312:	fb0e f003 	mul.w	r0, lr, r3
 8000316:	4288      	cmp	r0, r1
 8000318:	d908      	bls.n	800032c <__udivmoddi4+0x12c>
 800031a:	eb1c 0101 	adds.w	r1, ip, r1
 800031e:	f103 38ff 	add.w	r8, r3, #4294967295
 8000322:	d202      	bcs.n	800032a <__udivmoddi4+0x12a>
 8000324:	4288      	cmp	r0, r1
 8000326:	f200 80cb 	bhi.w	80004c0 <__udivmoddi4+0x2c0>
 800032a:	4643      	mov	r3, r8
 800032c:	1a09      	subs	r1, r1, r0
 800032e:	b2a4      	uxth	r4, r4
 8000330:	fbb1 f0f7 	udiv	r0, r1, r7
 8000334:	fb07 1110 	mls	r1, r7, r0, r1
 8000338:	ea44 4401 	orr.w	r4, r4, r1, lsl #16
 800033c:	fb0e fe00 	mul.w	lr, lr, r0
 8000340:	45a6      	cmp	lr, r4
 8000342:	d908      	bls.n	8000356 <__udivmoddi4+0x156>
 8000344:	eb1c 0404 	adds.w	r4, ip, r4
 8000348:	f100 31ff 	add.w	r1, r0, #4294967295
 800034c:	d202      	bcs.n	8000354 <__udivmoddi4+0x154>
 800034e:	45a6      	cmp	lr, r4
 8000350:	f200 80bb 	bhi.w	80004ca <__udivmoddi4+0x2ca>
 8000354:	4608      	mov	r0, r1
 8000356:	eba4 040e 	sub.w	r4, r4, lr
 800035a:	ea40 4003 	orr.w	r0, r0, r3, lsl #16
 800035e:	e79c      	b.n	800029a <__udivmoddi4+0x9a>
 8000360:	f1c6 0720 	rsb	r7, r6, #32
 8000364:	40b3      	lsls	r3, r6
 8000366:	fa22 fc07 	lsr.w	ip, r2, r7
 800036a:	ea4c 0c03 	orr.w	ip, ip, r3
 800036e:	fa20 f407 	lsr.w	r4, r0, r7
 8000372:	fa01 f306 	lsl.w	r3, r1, r6
 8000376:	431c      	orrs	r4, r3
 8000378:	40f9      	lsrs	r1, r7
 800037a:	ea4f 491c 	mov.w	r9, ip, lsr #16
 800037e:	fa00 f306 	lsl.w	r3, r0, r6
 8000382:	fbb1 f8f9 	udiv	r8, r1, r9
 8000386:	0c20      	lsrs	r0, r4, #16
 8000388:	fa1f fe8c 	uxth.w	lr, ip
 800038c:	fb09 1118 	mls	r1, r9, r8, r1
 8000390:	ea40 4101 	orr.w	r1, r0, r1, lsl #16
 8000394:	fb08 f00e 	mul.w	r0, r8, lr
 8000398:	4288      	cmp	r0, r1
 800039a:	fa02 f206 	lsl.w	r2, r2, r6
 800039e:	d90b      	bls.n	80003b8 <__udivmoddi4+0x1b8>
 80003a0:	eb1c 0101 	adds.w	r1, ip, r1
 80003a4:	f108 3aff 	add.w	sl, r8, #4294967295
 80003a8:	f080 8088 	bcs.w	80004bc <__udivmoddi4+0x2bc>
 80003ac:	4288      	cmp	r0, r1
 80003ae:	f240 8085 	bls.w	80004bc <__udivmoddi4+0x2bc>
 80003b2:	f1a8 0802 	sub.w	r8, r8, #2
 80003b6:	4461      	add	r1, ip
 80003b8:	1a09      	subs	r1, r1, r0
 80003ba:	b2a4      	uxth	r4, r4
 80003bc:	fbb1 f0f9 	udiv	r0, r1, r9
 80003c0:	fb09 1110 	mls	r1, r9, r0, r1
 80003c4:	ea44 4101 	orr.w	r1, r4, r1, lsl #16
 80003c8:	fb00 fe0e 	mul.w	lr, r0, lr
 80003cc:	458e      	cmp	lr, r1
 80003ce:	d908      	bls.n	80003e2 <__udivmoddi4+0x1e2>
 80003d0:	eb1c 0101 	adds.w	r1, ip, r1
 80003d4:	f100 34ff 	add.w	r4, r0, #4294967295
 80003d8:	d26c      	bcs.n	80004b4 <__udivmoddi4+0x2b4>
 80003da:	458e      	cmp	lr, r1
 80003dc:	d96a      	bls.n	80004b4 <__udivmoddi4+0x2b4>
 80003de:	3802      	subs	r0, #2
 80003e0:	4461      	add	r1, ip
 80003e2:	ea40 4008 	orr.w	r0, r0, r8, lsl #16
 80003e6:	fba0 9402 	umull	r9, r4, r0, r2
 80003ea:	eba1 010e 	sub.w	r1, r1, lr
 80003ee:	42a1      	cmp	r1, r4
 80003f0:	46c8      	mov	r8, r9
 80003f2:	46a6      	mov	lr, r4
 80003f4:	d356      	bcc.n	80004a4 <__udivmoddi4+0x2a4>
 80003f6:	d053      	beq.n	80004a0 <__udivmoddi4+0x2a0>
 80003f8:	b15d      	cbz	r5, 8000412 <__udivmoddi4+0x212>
 80003fa:	ebb3 0208 	subs.w	r2, r3, r8
 80003fe:	eb61 010e 	sbc.w	r1, r1, lr
 8000402:	fa01 f707 	lsl.w	r7, r1, r7
 8000406:	fa22 f306 	lsr.w	r3, r2, r6
 800040a:	40f1      	lsrs	r1, r6
 800040c:	431f      	orrs	r7, r3
 800040e:	e9c5 7100 	strd	r7, r1, [r5]
 8000412:	2600      	movs	r6, #0
 8000414:	4631      	mov	r1, r6
 8000416:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800041a:	f1c2 0320 	rsb	r3, r2, #32
 800041e:	40d8      	lsrs	r0, r3
 8000420:	fa0c fc02 	lsl.w	ip, ip, r2
 8000424:	fa21 f303 	lsr.w	r3, r1, r3
 8000428:	4091      	lsls	r1, r2
 800042a:	4301      	orrs	r1, r0
 800042c:	ea4f 471c 	mov.w	r7, ip, lsr #16
 8000430:	fa1f fe8c 	uxth.w	lr, ip
 8000434:	fbb3 f0f7 	udiv	r0, r3, r7
 8000438:	fb07 3610 	mls	r6, r7, r0, r3
 800043c:	0c0b      	lsrs	r3, r1, #16
 800043e:	ea43 4306 	orr.w	r3, r3, r6, lsl #16
 8000442:	fb00 f60e 	mul.w	r6, r0, lr
 8000446:	429e      	cmp	r6, r3
 8000448:	fa04 f402 	lsl.w	r4, r4, r2
 800044c:	d908      	bls.n	8000460 <__udivmoddi4+0x260>
 800044e:	eb1c 0303 	adds.w	r3, ip, r3
 8000452:	f100 38ff 	add.w	r8, r0, #4294967295
 8000456:	d22f      	bcs.n	80004b8 <__udivmoddi4+0x2b8>
 8000458:	429e      	cmp	r6, r3
 800045a:	d92d      	bls.n	80004b8 <__udivmoddi4+0x2b8>
 800045c:	3802      	subs	r0, #2
 800045e:	4463      	add	r3, ip
 8000460:	1b9b      	subs	r3, r3, r6
 8000462:	b289      	uxth	r1, r1
 8000464:	fbb3 f6f7 	udiv	r6, r3, r7
 8000468:	fb07 3316 	mls	r3, r7, r6, r3
 800046c:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
 8000470:	fb06 f30e 	mul.w	r3, r6, lr
 8000474:	428b      	cmp	r3, r1
 8000476:	d908      	bls.n	800048a <__udivmoddi4+0x28a>
 8000478:	eb1c 0101 	adds.w	r1, ip, r1
 800047c:	f106 38ff 	add.w	r8, r6, #4294967295
 8000480:	d216      	bcs.n	80004b0 <__udivmoddi4+0x2b0>
 8000482:	428b      	cmp	r3, r1
 8000484:	d914      	bls.n	80004b0 <__udivmoddi4+0x2b0>
 8000486:	3e02      	subs	r6, #2
 8000488:	4461      	add	r1, ip
 800048a:	1ac9      	subs	r1, r1, r3
 800048c:	ea46 4600 	orr.w	r6, r6, r0, lsl #16
 8000490:	e738      	b.n	8000304 <__udivmoddi4+0x104>
 8000492:	462e      	mov	r6, r5
 8000494:	4628      	mov	r0, r5
 8000496:	e705      	b.n	80002a4 <__udivmoddi4+0xa4>
 8000498:	4606      	mov	r6, r0
 800049a:	e6e3      	b.n	8000264 <__udivmoddi4+0x64>
 800049c:	4618      	mov	r0, r3
 800049e:	e6f8      	b.n	8000292 <__udivmoddi4+0x92>
 80004a0:	454b      	cmp	r3, r9
 80004a2:	d2a9      	bcs.n	80003f8 <__udivmoddi4+0x1f8>
 80004a4:	ebb9 0802 	subs.w	r8, r9, r2
 80004a8:	eb64 0e0c 	sbc.w	lr, r4, ip
 80004ac:	3801      	subs	r0, #1
 80004ae:	e7a3      	b.n	80003f8 <__udivmoddi4+0x1f8>
 80004b0:	4646      	mov	r6, r8
 80004b2:	e7ea      	b.n	800048a <__udivmoddi4+0x28a>
 80004b4:	4620      	mov	r0, r4
 80004b6:	e794      	b.n	80003e2 <__udivmoddi4+0x1e2>
 80004b8:	4640      	mov	r0, r8
 80004ba:	e7d1      	b.n	8000460 <__udivmoddi4+0x260>
 80004bc:	46d0      	mov	r8, sl
 80004be:	e77b      	b.n	80003b8 <__udivmoddi4+0x1b8>
 80004c0:	3b02      	subs	r3, #2
 80004c2:	4461      	add	r1, ip
 80004c4:	e732      	b.n	800032c <__udivmoddi4+0x12c>
 80004c6:	4630      	mov	r0, r6
 80004c8:	e709      	b.n	80002de <__udivmoddi4+0xde>
 80004ca:	4464      	add	r4, ip
 80004cc:	3802      	subs	r0, #2
 80004ce:	e742      	b.n	8000356 <__udivmoddi4+0x156>

080004d0 <__aeabi_idiv0>:
 80004d0:	4770      	bx	lr
 80004d2:	bf00      	nop

080004d4 <MX_DMA_Init>:

/**
  * Enable DMA controller clock
  */
void MX_DMA_Init(void)
{
 80004d4:	b580      	push	{r7, lr}
 80004d6:	b082      	sub	sp, #8
 80004d8:	af00      	add	r7, sp, #0

  /* DMA controller clock enable */
  __HAL_RCC_DMA1_CLK_ENABLE();
 80004da:	4b10      	ldr	r3, [pc, #64]	; (800051c <MX_DMA_Init+0x48>)
 80004dc:	6c9b      	ldr	r3, [r3, #72]	; 0x48
 80004de:	4a0f      	ldr	r2, [pc, #60]	; (800051c <MX_DMA_Init+0x48>)
 80004e0:	f043 0301 	orr.w	r3, r3, #1
 80004e4:	6493      	str	r3, [r2, #72]	; 0x48
 80004e6:	4b0d      	ldr	r3, [pc, #52]	; (800051c <MX_DMA_Init+0x48>)
 80004e8:	6c9b      	ldr	r3, [r3, #72]	; 0x48
 80004ea:	f003 0301 	and.w	r3, r3, #1
 80004ee:	607b      	str	r3, [r7, #4]
 80004f0:	687b      	ldr	r3, [r7, #4]

  /* DMA interrupt init */
  /* DMA1_Channel6_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 5, 0);
 80004f2:	2200      	movs	r2, #0
 80004f4:	2105      	movs	r1, #5
 80004f6:	2010      	movs	r0, #16
 80004f8:	f000 fcc8 	bl	8000e8c <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn);
 80004fc:	2010      	movs	r0, #16
 80004fe:	f000 fce1 	bl	8000ec4 <HAL_NVIC_EnableIRQ>
  /* DMA1_Channel7_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 5, 0);
 8000502:	2200      	movs	r2, #0
 8000504:	2105      	movs	r1, #5
 8000506:	2011      	movs	r0, #17
 8000508:	f000 fcc0 	bl	8000e8c <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
 800050c:	2011      	movs	r0, #17
 800050e:	f000 fcd9 	bl	8000ec4 <HAL_NVIC_EnableIRQ>

}
 8000512:	bf00      	nop
 8000514:	3708      	adds	r7, #8
 8000516:	46bd      	mov	sp, r7
 8000518:	bd80      	pop	{r7, pc}
 800051a:	bf00      	nop
 800051c:	40021000 	.word	0x40021000

08000520 <vApplicationIdleHook>:
void vApplicationIdleHook(void);
void vApplicationTickHook(void);

/* USER CODE BEGIN 2 */
void vApplicationIdleHook(void)
{
 8000520:	b480      	push	{r7}
 8000522:	af00      	add	r7, sp, #0
	 specified, or call vTaskDelay()). If the application makes use of the
	 vTaskDelete() API function (as this demo application does) then it is also
	 important that vApplicationIdleHook() is permitted to return to its calling
	 function, because it is the responsibility of the idle task to clean up
	 memory allocated by the kernel to any task that has since been deleted. */
}
 8000524:	bf00      	nop
 8000526:	46bd      	mov	sp, r7
 8000528:	f85d 7b04 	ldr.w	r7, [sp], #4
 800052c:	4770      	bx	lr

0800052e <vApplicationTickHook>:
/* USER CODE END 2 */

/* USER CODE BEGIN 3 */
void vApplicationTickHook(void)
{
 800052e:	b480      	push	{r7}
 8000530:	af00      	add	r7, sp, #0
	/* This function will be called by each tick interrupt if
	 configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
	 added here, but the tick hook is called from an interrupt context, so
	 code must not attempt to block, and only the interrupt safe FreeRTOS API
	 functions can be used (those that end in FromISR()). */
}
 8000532:	bf00      	nop
 8000534:	46bd      	mov	sp, r7
 8000536:	f85d 7b04 	ldr.w	r7, [sp], #4
 800053a:	4770      	bx	lr

0800053c <MX_FREERTOS_Init>:
 * @brief  FreeRTOS initialization
 * @param  None
 * @retval None
 */
void MX_FREERTOS_Init(void)
{
 800053c:	b580      	push	{r7, lr}
 800053e:	af00      	add	r7, sp, #0
	/* add queues, ... */
	/* USER CODE END RTOS_QUEUES */

	/* Create the thread(s) */
	/* creation of defaultTask */
	defaultTaskHandle = osThreadNew(StartDefaultTask, NULL,
 8000540:	4a08      	ldr	r2, [pc, #32]	; (8000564 <MX_FREERTOS_Init+0x28>)
 8000542:	2100      	movs	r1, #0
 8000544:	4808      	ldr	r0, [pc, #32]	; (8000568 <MX_FREERTOS_Init+0x2c>)
 8000546:	f003 fd03 	bl	8003f50 <osThreadNew>
 800054a:	4603      	mov	r3, r0
 800054c:	4a07      	ldr	r2, [pc, #28]	; (800056c <MX_FREERTOS_Init+0x30>)
 800054e:	6013      	str	r3, [r2, #0]
			&defaultTask_attributes);

	/* creation of Example01 */
	Example01Handle = osThreadNew(StartExample01, NULL, &Example01_attributes);
 8000550:	4a07      	ldr	r2, [pc, #28]	; (8000570 <MX_FREERTOS_Init+0x34>)
 8000552:	2100      	movs	r1, #0
 8000554:	4807      	ldr	r0, [pc, #28]	; (8000574 <MX_FREERTOS_Init+0x38>)
 8000556:	f003 fcfb 	bl	8003f50 <osThreadNew>
 800055a:	4603      	mov	r3, r0
 800055c:	4a06      	ldr	r2, [pc, #24]	; (8000578 <MX_FREERTOS_Init+0x3c>)
 800055e:	6013      	str	r3, [r2, #0]

	/* USER CODE BEGIN RTOS_EVENTS */
	/* add events, ... */
	/* USER CODE END RTOS_EVENTS */

}
 8000560:	bf00      	nop
 8000562:	bd80      	pop	{r7, pc}
 8000564:	08006c90 	.word	0x08006c90
 8000568:	0800057d 	.word	0x0800057d
 800056c:	200000a0 	.word	0x200000a0
 8000570:	08006cb4 	.word	0x08006cb4
 8000574:	0800058d 	.word	0x0800058d
 8000578:	200000a4 	.word	0x200000a4

0800057c <StartDefaultTask>:
 * @param  argument: Not used
 * @retval None
 */
/* USER CODE END Header_StartDefaultTask */
void StartDefaultTask(void *argument)
{
 800057c:	b580      	push	{r7, lr}
 800057e:	b082      	sub	sp, #8
 8000580:	af00      	add	r7, sp, #0
 8000582:	6078      	str	r0, [r7, #4]
	/* USER CODE BEGIN StartDefaultTask */
	/* Infinite loop */
	for (;;)
	{
		osDelay(1);
 8000584:	2001      	movs	r0, #1
 8000586:	f003 fd75 	bl	8004074 <osDelay>
 800058a:	e7fb      	b.n	8000584 <StartDefaultTask+0x8>

0800058c <StartExample01>:
 * @param argument: Not used
 * @retval None
 */
/* USER CODE END Header_StartExample01 */
void StartExample01(void *argument)
{
 800058c:	b580      	push	{r7, lr}
 800058e:	b082      	sub	sp, #8
 8000590:	af00      	add	r7, sp, #0
 8000592:	6078      	str	r0, [r7, #4]
	/* USER CODE BEGIN StartExample01 */
	/* Infinite loop */
	for (;;)
	{
		HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_5);
 8000594:	2120      	movs	r1, #32
 8000596:	f04f 4090 	mov.w	r0, #1207959552	; 0x48000000
 800059a:	f000 ffcb 	bl	8001534 <HAL_GPIO_TogglePin>
		osDelay(500);
 800059e:	f44f 70fa 	mov.w	r0, #500	; 0x1f4
 80005a2:	f003 fd67 	bl	8004074 <osDelay>
		HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_5);
 80005a6:	e7f5      	b.n	8000594 <StartExample01+0x8>

080005a8 <MX_GPIO_Init>:
        * Output
        * EVENT_OUT
        * EXTI
*/
void MX_GPIO_Init(void)
{
 80005a8:	b580      	push	{r7, lr}
 80005aa:	b08a      	sub	sp, #40	; 0x28
 80005ac:	af00      	add	r7, sp, #0

  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80005ae:	f107 0314 	add.w	r3, r7, #20
 80005b2:	2200      	movs	r2, #0
 80005b4:	601a      	str	r2, [r3, #0]
 80005b6:	605a      	str	r2, [r3, #4]
 80005b8:	609a      	str	r2, [r3, #8]
 80005ba:	60da      	str	r2, [r3, #12]
 80005bc:	611a      	str	r2, [r3, #16]

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 80005be:	4b2b      	ldr	r3, [pc, #172]	; (800066c <MX_GPIO_Init+0xc4>)
 80005c0:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80005c2:	4a2a      	ldr	r2, [pc, #168]	; (800066c <MX_GPIO_Init+0xc4>)
 80005c4:	f043 0304 	orr.w	r3, r3, #4
 80005c8:	64d3      	str	r3, [r2, #76]	; 0x4c
 80005ca:	4b28      	ldr	r3, [pc, #160]	; (800066c <MX_GPIO_Init+0xc4>)
 80005cc:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80005ce:	f003 0304 	and.w	r3, r3, #4
 80005d2:	613b      	str	r3, [r7, #16]
 80005d4:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOH_CLK_ENABLE();
 80005d6:	4b25      	ldr	r3, [pc, #148]	; (800066c <MX_GPIO_Init+0xc4>)
 80005d8:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80005da:	4a24      	ldr	r2, [pc, #144]	; (800066c <MX_GPIO_Init+0xc4>)
 80005dc:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 80005e0:	64d3      	str	r3, [r2, #76]	; 0x4c
 80005e2:	4b22      	ldr	r3, [pc, #136]	; (800066c <MX_GPIO_Init+0xc4>)
 80005e4:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80005e6:	f003 0380 	and.w	r3, r3, #128	; 0x80
 80005ea:	60fb      	str	r3, [r7, #12]
 80005ec:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 80005ee:	4b1f      	ldr	r3, [pc, #124]	; (800066c <MX_GPIO_Init+0xc4>)
 80005f0:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80005f2:	4a1e      	ldr	r2, [pc, #120]	; (800066c <MX_GPIO_Init+0xc4>)
 80005f4:	f043 0301 	orr.w	r3, r3, #1
 80005f8:	64d3      	str	r3, [r2, #76]	; 0x4c
 80005fa:	4b1c      	ldr	r3, [pc, #112]	; (800066c <MX_GPIO_Init+0xc4>)
 80005fc:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80005fe:	f003 0301 	and.w	r3, r3, #1
 8000602:	60bb      	str	r3, [r7, #8]
 8000604:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8000606:	4b19      	ldr	r3, [pc, #100]	; (800066c <MX_GPIO_Init+0xc4>)
 8000608:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 800060a:	4a18      	ldr	r2, [pc, #96]	; (800066c <MX_GPIO_Init+0xc4>)
 800060c:	f043 0302 	orr.w	r3, r3, #2
 8000610:	64d3      	str	r3, [r2, #76]	; 0x4c
 8000612:	4b16      	ldr	r3, [pc, #88]	; (800066c <MX_GPIO_Init+0xc4>)
 8000614:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8000616:	f003 0302 	and.w	r3, r3, #2
 800061a:	607b      	str	r3, [r7, #4]
 800061c:	687b      	ldr	r3, [r7, #4]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
 800061e:	2200      	movs	r2, #0
 8000620:	2120      	movs	r1, #32
 8000622:	f04f 4090 	mov.w	r0, #1207959552	; 0x48000000
 8000626:	f000 ff6d 	bl	8001504 <HAL_GPIO_WritePin>

  /*Configure GPIO pin : PtPin */
  GPIO_InitStruct.Pin = B1_Pin;
 800062a:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 800062e:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
 8000630:	f44f 1304 	mov.w	r3, #2162688	; 0x210000
 8000634:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000636:	2300      	movs	r3, #0
 8000638:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
 800063a:	f107 0314 	add.w	r3, r7, #20
 800063e:	4619      	mov	r1, r3
 8000640:	480b      	ldr	r0, [pc, #44]	; (8000670 <MX_GPIO_Init+0xc8>)
 8000642:	f000 fdb5 	bl	80011b0 <HAL_GPIO_Init>

  /*Configure GPIO pin : PtPin */
  GPIO_InitStruct.Pin = LD2_Pin;
 8000646:	2320      	movs	r3, #32
 8000648:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 800064a:	2301      	movs	r3, #1
 800064c:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 800064e:	2300      	movs	r3, #0
 8000650:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000652:	2300      	movs	r3, #0
 8000654:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
 8000656:	f107 0314 	add.w	r3, r7, #20
 800065a:	4619      	mov	r1, r3
 800065c:	f04f 4090 	mov.w	r0, #1207959552	; 0x48000000
 8000660:	f000 fda6 	bl	80011b0 <HAL_GPIO_Init>

}
 8000664:	bf00      	nop
 8000666:	3728      	adds	r7, #40	; 0x28
 8000668:	46bd      	mov	sp, r7
 800066a:	bd80      	pop	{r7, pc}
 800066c:	40021000 	.word	0x40021000
 8000670:	48000800 	.word	0x48000800

08000674 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8000674:	b580      	push	{r7, lr}
 8000676:	af00      	add	r7, sp, #0
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8000678:	f000 fb10 	bl	8000c9c <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 800067c:	f000 f812 	bl	80006a4 <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 8000680:	f7ff ff92 	bl	80005a8 <MX_GPIO_Init>
  MX_USART2_UART_Init();
 8000684:	f000 f9f6 	bl	8000a74 <MX_USART2_UART_Init>
  MX_DMA_Init();
 8000688:	f7ff ff24 	bl	80004d4 <MX_DMA_Init>
  MX_RTC_Init();
 800068c:	f000 f8d4 	bl	8000838 <MX_RTC_Init>
  MX_RNG_Init();
 8000690:	f000 f888 	bl	80007a4 <MX_RNG_Init>
  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */

  /* Init scheduler */
  osKernelInitialize();  /* Call init function for freertos objects (in freertos.c) */
 8000694:	f003 fc10 	bl	8003eb8 <osKernelInitialize>
  MX_FREERTOS_Init();
 8000698:	f7ff ff50 	bl	800053c <MX_FREERTOS_Init>

  /* Start scheduler */
  osKernelStart();
 800069c:	f003 fc32 	bl	8003f04 <osKernelStart>

  /* We should never get here as control is now taken by the scheduler */
  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
 80006a0:	e7fe      	b.n	80006a0 <main+0x2c>
	...

080006a4 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 80006a4:	b580      	push	{r7, lr}
 80006a6:	b096      	sub	sp, #88	; 0x58
 80006a8:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 80006aa:	f107 0314 	add.w	r3, r7, #20
 80006ae:	2244      	movs	r2, #68	; 0x44
 80006b0:	2100      	movs	r1, #0
 80006b2:	4618      	mov	r0, r3
 80006b4:	f006 f9fe 	bl	8006ab4 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 80006b8:	463b      	mov	r3, r7
 80006ba:	2200      	movs	r2, #0
 80006bc:	601a      	str	r2, [r3, #0]
 80006be:	605a      	str	r2, [r3, #4]
 80006c0:	609a      	str	r2, [r3, #8]
 80006c2:	60da      	str	r2, [r3, #12]
 80006c4:	611a      	str	r2, [r3, #16]

  /** Configure the main internal regulator output voltage
  */
  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
 80006c6:	f44f 7000 	mov.w	r0, #512	; 0x200
 80006ca:	f000 ff6b 	bl	80015a4 <HAL_PWREx_ControlVoltageScaling>
 80006ce:	4603      	mov	r3, r0
 80006d0:	2b00      	cmp	r3, #0
 80006d2:	d001      	beq.n	80006d8 <SystemClock_Config+0x34>
  {
    Error_Handler();
 80006d4:	f000 f860 	bl	8000798 <Error_Handler>
  }

  /** Configure LSE Drive Capability
  */
  HAL_PWR_EnableBkUpAccess();
 80006d8:	f000 ff46 	bl	8001568 <HAL_PWR_EnableBkUpAccess>
  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
 80006dc:	4b24      	ldr	r3, [pc, #144]	; (8000770 <SystemClock_Config+0xcc>)
 80006de:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 80006e2:	4a23      	ldr	r2, [pc, #140]	; (8000770 <SystemClock_Config+0xcc>)
 80006e4:	f023 0318 	bic.w	r3, r3, #24
 80006e8:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE
 80006ec:	2316      	movs	r3, #22
 80006ee:	617b      	str	r3, [r7, #20]
                              |RCC_OSCILLATORTYPE_MSI;
  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
 80006f0:	2301      	movs	r3, #1
 80006f2:	61fb      	str	r3, [r7, #28]
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 80006f4:	f44f 7380 	mov.w	r3, #256	; 0x100
 80006f8:	623b      	str	r3, [r7, #32]
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 80006fa:	2310      	movs	r3, #16
 80006fc:	627b      	str	r3, [r7, #36]	; 0x24
  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
 80006fe:	2301      	movs	r3, #1
 8000700:	62fb      	str	r3, [r7, #44]	; 0x2c
  RCC_OscInitStruct.MSICalibrationValue = 0;
 8000702:	2300      	movs	r3, #0
 8000704:	633b      	str	r3, [r7, #48]	; 0x30
  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
 8000706:	2360      	movs	r3, #96	; 0x60
 8000708:	637b      	str	r3, [r7, #52]	; 0x34
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 800070a:	2302      	movs	r3, #2
 800070c:	63fb      	str	r3, [r7, #60]	; 0x3c
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
 800070e:	2302      	movs	r3, #2
 8000710:	643b      	str	r3, [r7, #64]	; 0x40
  RCC_OscInitStruct.PLL.PLLM = 1;
 8000712:	2301      	movs	r3, #1
 8000714:	647b      	str	r3, [r7, #68]	; 0x44
  RCC_OscInitStruct.PLL.PLLN = 10;
 8000716:	230a      	movs	r3, #10
 8000718:	64bb      	str	r3, [r7, #72]	; 0x48
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
 800071a:	2307      	movs	r3, #7
 800071c:	64fb      	str	r3, [r7, #76]	; 0x4c
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
 800071e:	2302      	movs	r3, #2
 8000720:	653b      	str	r3, [r7, #80]	; 0x50
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
 8000722:	2302      	movs	r3, #2
 8000724:	657b      	str	r3, [r7, #84]	; 0x54
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8000726:	f107 0314 	add.w	r3, r7, #20
 800072a:	4618      	mov	r0, r3
 800072c:	f000 ff90 	bl	8001650 <HAL_RCC_OscConfig>
 8000730:	4603      	mov	r3, r0
 8000732:	2b00      	cmp	r3, #0
 8000734:	d001      	beq.n	800073a <SystemClock_Config+0x96>
  {
    Error_Handler();
 8000736:	f000 f82f 	bl	8000798 <Error_Handler>
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 800073a:	230f      	movs	r3, #15
 800073c:	603b      	str	r3, [r7, #0]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 800073e:	2303      	movs	r3, #3
 8000740:	607b      	str	r3, [r7, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8000742:	2300      	movs	r3, #0
 8000744:	60bb      	str	r3, [r7, #8]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 8000746:	2300      	movs	r3, #0
 8000748:	60fb      	str	r3, [r7, #12]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 800074a:	2300      	movs	r3, #0
 800074c:	613b      	str	r3, [r7, #16]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
 800074e:	463b      	mov	r3, r7
 8000750:	2104      	movs	r1, #4
 8000752:	4618      	mov	r0, r3
 8000754:	f001 fb58 	bl	8001e08 <HAL_RCC_ClockConfig>
 8000758:	4603      	mov	r3, r0
 800075a:	2b00      	cmp	r3, #0
 800075c:	d001      	beq.n	8000762 <SystemClock_Config+0xbe>
  {
    Error_Handler();
 800075e:	f000 f81b 	bl	8000798 <Error_Handler>
  }

  /** Enable MSI Auto calibration
  */
  HAL_RCCEx_EnableMSIPLLMode();
 8000762:	f002 f891 	bl	8002888 <HAL_RCCEx_EnableMSIPLLMode>
}
 8000766:	bf00      	nop
 8000768:	3758      	adds	r7, #88	; 0x58
 800076a:	46bd      	mov	sp, r7
 800076c:	bd80      	pop	{r7, pc}
 800076e:	bf00      	nop
 8000770:	40021000 	.word	0x40021000

08000774 <HAL_TIM_PeriodElapsedCallback>:
  * a global variable "uwTick" used as application time base.
  * @param  htim : TIM handle
  * @retval None
  */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
 8000774:	b580      	push	{r7, lr}
 8000776:	b082      	sub	sp, #8
 8000778:	af00      	add	r7, sp, #0
 800077a:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN Callback 0 */

  /* USER CODE END Callback 0 */
  if (htim->Instance == TIM17) {
 800077c:	687b      	ldr	r3, [r7, #4]
 800077e:	681b      	ldr	r3, [r3, #0]
 8000780:	4a04      	ldr	r2, [pc, #16]	; (8000794 <HAL_TIM_PeriodElapsedCallback+0x20>)
 8000782:	4293      	cmp	r3, r2
 8000784:	d101      	bne.n	800078a <HAL_TIM_PeriodElapsedCallback+0x16>
    HAL_IncTick();
 8000786:	f000 faa9 	bl	8000cdc <HAL_IncTick>
  }
  /* USER CODE BEGIN Callback 1 */

  /* USER CODE END Callback 1 */
}
 800078a:	bf00      	nop
 800078c:	3708      	adds	r7, #8
 800078e:	46bd      	mov	sp, r7
 8000790:	bd80      	pop	{r7, pc}
 8000792:	bf00      	nop
 8000794:	40014800 	.word	0x40014800

08000798 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8000798:	b480      	push	{r7}
 800079a:	af00      	add	r7, sp, #0
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 800079c:	b672      	cpsid	i
}
 800079e:	bf00      	nop
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 80007a0:	e7fe      	b.n	80007a0 <Error_Handler+0x8>
	...

080007a4 <MX_RNG_Init>:

RNG_HandleTypeDef hrng;

/* RNG init function */
void MX_RNG_Init(void)
{
 80007a4:	b580      	push	{r7, lr}
 80007a6:	af00      	add	r7, sp, #0
  /* USER CODE END RNG_Init 0 */

  /* USER CODE BEGIN RNG_Init 1 */

  /* USER CODE END RNG_Init 1 */
  hrng.Instance = RNG;
 80007a8:	4b06      	ldr	r3, [pc, #24]	; (80007c4 <MX_RNG_Init+0x20>)
 80007aa:	4a07      	ldr	r2, [pc, #28]	; (80007c8 <MX_RNG_Init+0x24>)
 80007ac:	601a      	str	r2, [r3, #0]
  if (HAL_RNG_Init(&hrng) != HAL_OK)
 80007ae:	4805      	ldr	r0, [pc, #20]	; (80007c4 <MX_RNG_Init+0x20>)
 80007b0:	f002 fa4c 	bl	8002c4c <HAL_RNG_Init>
 80007b4:	4603      	mov	r3, r0
 80007b6:	2b00      	cmp	r3, #0
 80007b8:	d001      	beq.n	80007be <MX_RNG_Init+0x1a>
  {
    Error_Handler();
 80007ba:	f7ff ffed 	bl	8000798 <Error_Handler>
  }
  /* USER CODE BEGIN RNG_Init 2 */

  /* USER CODE END RNG_Init 2 */

}
 80007be:	bf00      	nop
 80007c0:	bd80      	pop	{r7, pc}
 80007c2:	bf00      	nop
 80007c4:	200000a8 	.word	0x200000a8
 80007c8:	50060800 	.word	0x50060800

080007cc <HAL_RNG_MspInit>:

void HAL_RNG_MspInit(RNG_HandleTypeDef* rngHandle)
{
 80007cc:	b580      	push	{r7, lr}
 80007ce:	b0a6      	sub	sp, #152	; 0x98
 80007d0:	af00      	add	r7, sp, #0
 80007d2:	6078      	str	r0, [r7, #4]

  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 80007d4:	f107 0310 	add.w	r3, r7, #16
 80007d8:	2288      	movs	r2, #136	; 0x88
 80007da:	2100      	movs	r1, #0
 80007dc:	4618      	mov	r0, r3
 80007de:	f006 f969 	bl	8006ab4 <memset>
  if(rngHandle->Instance==RNG)
 80007e2:	687b      	ldr	r3, [r7, #4]
 80007e4:	681b      	ldr	r3, [r3, #0]
 80007e6:	4a12      	ldr	r2, [pc, #72]	; (8000830 <HAL_RNG_MspInit+0x64>)
 80007e8:	4293      	cmp	r3, r2
 80007ea:	d11c      	bne.n	8000826 <HAL_RNG_MspInit+0x5a>

  /* USER CODE END RNG_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RNG;
 80007ec:	f44f 2380 	mov.w	r3, #262144	; 0x40000
 80007f0:	613b      	str	r3, [r7, #16]
    PeriphClkInit.RngClockSelection = RCC_RNGCLKSOURCE_MSI;
 80007f2:	f04f 6340 	mov.w	r3, #201326592	; 0xc000000
 80007f6:	f8c7 3084 	str.w	r3, [r7, #132]	; 0x84
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 80007fa:	f107 0310 	add.w	r3, r7, #16
 80007fe:	4618      	mov	r0, r3
 8000800:	f001 fd58 	bl	80022b4 <HAL_RCCEx_PeriphCLKConfig>
 8000804:	4603      	mov	r3, r0
 8000806:	2b00      	cmp	r3, #0
 8000808:	d001      	beq.n	800080e <HAL_RNG_MspInit+0x42>
    {
      Error_Handler();
 800080a:	f7ff ffc5 	bl	8000798 <Error_Handler>
    }

    /* RNG clock enable */
    __HAL_RCC_RNG_CLK_ENABLE();
 800080e:	4b09      	ldr	r3, [pc, #36]	; (8000834 <HAL_RNG_MspInit+0x68>)
 8000810:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8000812:	4a08      	ldr	r2, [pc, #32]	; (8000834 <HAL_RNG_MspInit+0x68>)
 8000814:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8000818:	64d3      	str	r3, [r2, #76]	; 0x4c
 800081a:	4b06      	ldr	r3, [pc, #24]	; (8000834 <HAL_RNG_MspInit+0x68>)
 800081c:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 800081e:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
 8000822:	60fb      	str	r3, [r7, #12]
 8000824:	68fb      	ldr	r3, [r7, #12]
  /* USER CODE BEGIN RNG_MspInit 1 */

  /* USER CODE END RNG_MspInit 1 */
  }
}
 8000826:	bf00      	nop
 8000828:	3798      	adds	r7, #152	; 0x98
 800082a:	46bd      	mov	sp, r7
 800082c:	bd80      	pop	{r7, pc}
 800082e:	bf00      	nop
 8000830:	50060800 	.word	0x50060800
 8000834:	40021000 	.word	0x40021000

08000838 <MX_RTC_Init>:

RTC_HandleTypeDef hrtc;

/* RTC init function */
void MX_RTC_Init(void)
{
 8000838:	b580      	push	{r7, lr}
 800083a:	af00      	add	r7, sp, #0

  /* USER CODE END RTC_Init 1 */

  /** Initialize RTC Only
  */
  hrtc.Instance = RTC;
 800083c:	4b10      	ldr	r3, [pc, #64]	; (8000880 <MX_RTC_Init+0x48>)
 800083e:	4a11      	ldr	r2, [pc, #68]	; (8000884 <MX_RTC_Init+0x4c>)
 8000840:	601a      	str	r2, [r3, #0]
  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
 8000842:	4b0f      	ldr	r3, [pc, #60]	; (8000880 <MX_RTC_Init+0x48>)
 8000844:	2200      	movs	r2, #0
 8000846:	605a      	str	r2, [r3, #4]
  hrtc.Init.AsynchPrediv = 127;
 8000848:	4b0d      	ldr	r3, [pc, #52]	; (8000880 <MX_RTC_Init+0x48>)
 800084a:	227f      	movs	r2, #127	; 0x7f
 800084c:	609a      	str	r2, [r3, #8]
  hrtc.Init.SynchPrediv = 255;
 800084e:	4b0c      	ldr	r3, [pc, #48]	; (8000880 <MX_RTC_Init+0x48>)
 8000850:	22ff      	movs	r2, #255	; 0xff
 8000852:	60da      	str	r2, [r3, #12]
  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
 8000854:	4b0a      	ldr	r3, [pc, #40]	; (8000880 <MX_RTC_Init+0x48>)
 8000856:	2200      	movs	r2, #0
 8000858:	611a      	str	r2, [r3, #16]
  hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE;
 800085a:	4b09      	ldr	r3, [pc, #36]	; (8000880 <MX_RTC_Init+0x48>)
 800085c:	2200      	movs	r2, #0
 800085e:	615a      	str	r2, [r3, #20]
  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
 8000860:	4b07      	ldr	r3, [pc, #28]	; (8000880 <MX_RTC_Init+0x48>)
 8000862:	2200      	movs	r2, #0
 8000864:	619a      	str	r2, [r3, #24]
  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
 8000866:	4b06      	ldr	r3, [pc, #24]	; (8000880 <MX_RTC_Init+0x48>)
 8000868:	2200      	movs	r2, #0
 800086a:	61da      	str	r2, [r3, #28]
  if (HAL_RTC_Init(&hrtc) != HAL_OK)
 800086c:	4804      	ldr	r0, [pc, #16]	; (8000880 <MX_RTC_Init+0x48>)
 800086e:	f002 fa44 	bl	8002cfa <HAL_RTC_Init>
 8000872:	4603      	mov	r3, r0
 8000874:	2b00      	cmp	r3, #0
 8000876:	d001      	beq.n	800087c <MX_RTC_Init+0x44>
  {
    Error_Handler();
 8000878:	f7ff ff8e 	bl	8000798 <Error_Handler>
  }
  /* USER CODE BEGIN RTC_Init 2 */

  /* USER CODE END RTC_Init 2 */

}
 800087c:	bf00      	nop
 800087e:	bd80      	pop	{r7, pc}
 8000880:	200000b8 	.word	0x200000b8
 8000884:	40002800 	.word	0x40002800

08000888 <HAL_RTC_MspInit>:

void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle)
{
 8000888:	b580      	push	{r7, lr}
 800088a:	b0a4      	sub	sp, #144	; 0x90
 800088c:	af00      	add	r7, sp, #0
 800088e:	6078      	str	r0, [r7, #4]

  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8000890:	f107 0308 	add.w	r3, r7, #8
 8000894:	2288      	movs	r2, #136	; 0x88
 8000896:	2100      	movs	r1, #0
 8000898:	4618      	mov	r0, r3
 800089a:	f006 f90b 	bl	8006ab4 <memset>
  if(rtcHandle->Instance==RTC)
 800089e:	687b      	ldr	r3, [r7, #4]
 80008a0:	681b      	ldr	r3, [r3, #0]
 80008a2:	4a10      	ldr	r2, [pc, #64]	; (80008e4 <HAL_RTC_MspInit+0x5c>)
 80008a4:	4293      	cmp	r3, r2
 80008a6:	d118      	bne.n	80008da <HAL_RTC_MspInit+0x52>

  /* USER CODE END RTC_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC;
 80008a8:	f44f 3300 	mov.w	r3, #131072	; 0x20000
 80008ac:	60bb      	str	r3, [r7, #8]
    PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
 80008ae:	f44f 7380 	mov.w	r3, #256	; 0x100
 80008b2:	f8c7 308c 	str.w	r3, [r7, #140]	; 0x8c
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 80008b6:	f107 0308 	add.w	r3, r7, #8
 80008ba:	4618      	mov	r0, r3
 80008bc:	f001 fcfa 	bl	80022b4 <HAL_RCCEx_PeriphCLKConfig>
 80008c0:	4603      	mov	r3, r0
 80008c2:	2b00      	cmp	r3, #0
 80008c4:	d001      	beq.n	80008ca <HAL_RTC_MspInit+0x42>
    {
      Error_Handler();
 80008c6:	f7ff ff67 	bl	8000798 <Error_Handler>
    }

    /* RTC clock enable */
    __HAL_RCC_RTC_ENABLE();
 80008ca:	4b07      	ldr	r3, [pc, #28]	; (80008e8 <HAL_RTC_MspInit+0x60>)
 80008cc:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 80008d0:	4a05      	ldr	r2, [pc, #20]	; (80008e8 <HAL_RTC_MspInit+0x60>)
 80008d2:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
 80008d6:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
  /* USER CODE BEGIN RTC_MspInit 1 */

  /* USER CODE END RTC_MspInit 1 */
  }
}
 80008da:	bf00      	nop
 80008dc:	3790      	adds	r7, #144	; 0x90
 80008de:	46bd      	mov	sp, r7
 80008e0:	bd80      	pop	{r7, pc}
 80008e2:	bf00      	nop
 80008e4:	40002800 	.word	0x40002800
 80008e8:	40021000 	.word	0x40021000

080008ec <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 80008ec:	b580      	push	{r7, lr}
 80008ee:	b082      	sub	sp, #8
 80008f0:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 80008f2:	4b11      	ldr	r3, [pc, #68]	; (8000938 <HAL_MspInit+0x4c>)
 80008f4:	6e1b      	ldr	r3, [r3, #96]	; 0x60
 80008f6:	4a10      	ldr	r2, [pc, #64]	; (8000938 <HAL_MspInit+0x4c>)
 80008f8:	f043 0301 	orr.w	r3, r3, #1
 80008fc:	6613      	str	r3, [r2, #96]	; 0x60
 80008fe:	4b0e      	ldr	r3, [pc, #56]	; (8000938 <HAL_MspInit+0x4c>)
 8000900:	6e1b      	ldr	r3, [r3, #96]	; 0x60
 8000902:	f003 0301 	and.w	r3, r3, #1
 8000906:	607b      	str	r3, [r7, #4]
 8000908:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 800090a:	4b0b      	ldr	r3, [pc, #44]	; (8000938 <HAL_MspInit+0x4c>)
 800090c:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 800090e:	4a0a      	ldr	r2, [pc, #40]	; (8000938 <HAL_MspInit+0x4c>)
 8000910:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8000914:	6593      	str	r3, [r2, #88]	; 0x58
 8000916:	4b08      	ldr	r3, [pc, #32]	; (8000938 <HAL_MspInit+0x4c>)
 8000918:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 800091a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 800091e:	603b      	str	r3, [r7, #0]
 8000920:	683b      	ldr	r3, [r7, #0]

  /* System interrupt init*/
  /* PendSV_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 8000922:	2200      	movs	r2, #0
 8000924:	210f      	movs	r1, #15
 8000926:	f06f 0001 	mvn.w	r0, #1
 800092a:	f000 faaf 	bl	8000e8c <HAL_NVIC_SetPriority>

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 800092e:	bf00      	nop
 8000930:	3708      	adds	r7, #8
 8000932:	46bd      	mov	sp, r7
 8000934:	bd80      	pop	{r7, pc}
 8000936:	bf00      	nop
 8000938:	40021000 	.word	0x40021000

0800093c <HAL_InitTick>:
  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
  * @param  TickPriority: Tick interrupt priority.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 800093c:	b580      	push	{r7, lr}
 800093e:	b08c      	sub	sp, #48	; 0x30
 8000940:	af00      	add	r7, sp, #0
 8000942:	6078      	str	r0, [r7, #4]
  RCC_ClkInitTypeDef    clkconfig;
  uint32_t              uwTimclock = 0;
 8000944:	2300      	movs	r3, #0
 8000946:	62fb      	str	r3, [r7, #44]	; 0x2c
  uint32_t              uwPrescalerValue = 0;
 8000948:	2300      	movs	r3, #0
 800094a:	62bb      	str	r3, [r7, #40]	; 0x28
  uint32_t              pFLatency;
  /*Configure the TIM17 IRQ priority */
  HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority ,0);
 800094c:	2200      	movs	r2, #0
 800094e:	6879      	ldr	r1, [r7, #4]
 8000950:	201a      	movs	r0, #26
 8000952:	f000 fa9b 	bl	8000e8c <HAL_NVIC_SetPriority>

  /* Enable the TIM17 global Interrupt */
  HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn);
 8000956:	201a      	movs	r0, #26
 8000958:	f000 fab4 	bl	8000ec4 <HAL_NVIC_EnableIRQ>

  /* Enable TIM17 clock */
  __HAL_RCC_TIM17_CLK_ENABLE();
 800095c:	4b1e      	ldr	r3, [pc, #120]	; (80009d8 <HAL_InitTick+0x9c>)
 800095e:	6e1b      	ldr	r3, [r3, #96]	; 0x60
 8000960:	4a1d      	ldr	r2, [pc, #116]	; (80009d8 <HAL_InitTick+0x9c>)
 8000962:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8000966:	6613      	str	r3, [r2, #96]	; 0x60
 8000968:	4b1b      	ldr	r3, [pc, #108]	; (80009d8 <HAL_InitTick+0x9c>)
 800096a:	6e1b      	ldr	r3, [r3, #96]	; 0x60
 800096c:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
 8000970:	60fb      	str	r3, [r7, #12]
 8000972:	68fb      	ldr	r3, [r7, #12]

  /* Get clock configuration */
  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
 8000974:	f107 0210 	add.w	r2, r7, #16
 8000978:	f107 0314 	add.w	r3, r7, #20
 800097c:	4611      	mov	r1, r2
 800097e:	4618      	mov	r0, r3
 8000980:	f001 fc06 	bl	8002190 <HAL_RCC_GetClockConfig>

  /* Compute TIM17 clock */
  uwTimclock = HAL_RCC_GetPCLK2Freq();
 8000984:	f001 fbee 	bl	8002164 <HAL_RCC_GetPCLK2Freq>
 8000988:	62f8      	str	r0, [r7, #44]	; 0x2c
  /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
 800098a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 800098c:	4a13      	ldr	r2, [pc, #76]	; (80009dc <HAL_InitTick+0xa0>)
 800098e:	fba2 2303 	umull	r2, r3, r2, r3
 8000992:	0c9b      	lsrs	r3, r3, #18
 8000994:	3b01      	subs	r3, #1
 8000996:	62bb      	str	r3, [r7, #40]	; 0x28

  /* Initialize TIM17 */
  htim17.Instance = TIM17;
 8000998:	4b11      	ldr	r3, [pc, #68]	; (80009e0 <HAL_InitTick+0xa4>)
 800099a:	4a12      	ldr	r2, [pc, #72]	; (80009e4 <HAL_InitTick+0xa8>)
 800099c:	601a      	str	r2, [r3, #0]
  + Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
  + ClockDivision = 0
  + Counter direction = Up
  */
  htim17.Init.Period = (1000000U / 1000U) - 1U;
 800099e:	4b10      	ldr	r3, [pc, #64]	; (80009e0 <HAL_InitTick+0xa4>)
 80009a0:	f240 32e7 	movw	r2, #999	; 0x3e7
 80009a4:	60da      	str	r2, [r3, #12]
  htim17.Init.Prescaler = uwPrescalerValue;
 80009a6:	4a0e      	ldr	r2, [pc, #56]	; (80009e0 <HAL_InitTick+0xa4>)
 80009a8:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80009aa:	6053      	str	r3, [r2, #4]
  htim17.Init.ClockDivision = 0;
 80009ac:	4b0c      	ldr	r3, [pc, #48]	; (80009e0 <HAL_InitTick+0xa4>)
 80009ae:	2200      	movs	r2, #0
 80009b0:	611a      	str	r2, [r3, #16]
  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
 80009b2:	4b0b      	ldr	r3, [pc, #44]	; (80009e0 <HAL_InitTick+0xa4>)
 80009b4:	2200      	movs	r2, #0
 80009b6:	609a      	str	r2, [r3, #8]

  if(HAL_TIM_Base_Init(&htim17) == HAL_OK)
 80009b8:	4809      	ldr	r0, [pc, #36]	; (80009e0 <HAL_InitTick+0xa4>)
 80009ba:	f002 fab1 	bl	8002f20 <HAL_TIM_Base_Init>
 80009be:	4603      	mov	r3, r0
 80009c0:	2b00      	cmp	r3, #0
 80009c2:	d104      	bne.n	80009ce <HAL_InitTick+0x92>
  {
    /* Start the TIM time Base generation in interrupt mode */
    return HAL_TIM_Base_Start_IT(&htim17);
 80009c4:	4806      	ldr	r0, [pc, #24]	; (80009e0 <HAL_InitTick+0xa4>)
 80009c6:	f002 fb0d 	bl	8002fe4 <HAL_TIM_Base_Start_IT>
 80009ca:	4603      	mov	r3, r0
 80009cc:	e000      	b.n	80009d0 <HAL_InitTick+0x94>
  }

  /* Return function status */
  return HAL_ERROR;
 80009ce:	2301      	movs	r3, #1
}
 80009d0:	4618      	mov	r0, r3
 80009d2:	3730      	adds	r7, #48	; 0x30
 80009d4:	46bd      	mov	sp, r7
 80009d6:	bd80      	pop	{r7, pc}
 80009d8:	40021000 	.word	0x40021000
 80009dc:	431bde83 	.word	0x431bde83
 80009e0:	200000dc 	.word	0x200000dc
 80009e4:	40014800 	.word	0x40014800

080009e8 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 80009e8:	b480      	push	{r7}
 80009ea:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 80009ec:	e7fe      	b.n	80009ec <NMI_Handler+0x4>

080009ee <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 80009ee:	b480      	push	{r7}
 80009f0:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 80009f2:	e7fe      	b.n	80009f2 <HardFault_Handler+0x4>

080009f4 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 80009f4:	b480      	push	{r7}
 80009f6:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 80009f8:	e7fe      	b.n	80009f8 <MemManage_Handler+0x4>

080009fa <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 80009fa:	b480      	push	{r7}
 80009fc:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 80009fe:	e7fe      	b.n	80009fe <BusFault_Handler+0x4>

08000a00 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8000a00:	b480      	push	{r7}
 8000a02:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8000a04:	e7fe      	b.n	8000a04 <UsageFault_Handler+0x4>

08000a06 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8000a06:	b480      	push	{r7}
 8000a08:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8000a0a:	bf00      	nop
 8000a0c:	46bd      	mov	sp, r7
 8000a0e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000a12:	4770      	bx	lr

08000a14 <DMA1_Channel6_IRQHandler>:

/**
  * @brief This function handles DMA1 channel6 global interrupt.
  */
void DMA1_Channel6_IRQHandler(void)
{
 8000a14:	b580      	push	{r7, lr}
 8000a16:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Channel6_IRQn 0 */

  /* USER CODE END DMA1_Channel6_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart2_rx);
 8000a18:	4802      	ldr	r0, [pc, #8]	; (8000a24 <DMA1_Channel6_IRQHandler+0x10>)
 8000a1a:	f000 fb19 	bl	8001050 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Channel6_IRQn 1 */

  /* USER CODE END DMA1_Channel6_IRQn 1 */
}
 8000a1e:	bf00      	nop
 8000a20:	bd80      	pop	{r7, pc}
 8000a22:	bf00      	nop
 8000a24:	200001ac 	.word	0x200001ac

08000a28 <DMA1_Channel7_IRQHandler>:

/**
  * @brief This function handles DMA1 channel7 global interrupt.
  */
void DMA1_Channel7_IRQHandler(void)
{
 8000a28:	b580      	push	{r7, lr}
 8000a2a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Channel7_IRQn 0 */

  /* USER CODE END DMA1_Channel7_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart2_tx);
 8000a2c:	4802      	ldr	r0, [pc, #8]	; (8000a38 <DMA1_Channel7_IRQHandler+0x10>)
 8000a2e:	f000 fb0f 	bl	8001050 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Channel7_IRQn 1 */

  /* USER CODE END DMA1_Channel7_IRQn 1 */
}
 8000a32:	bf00      	nop
 8000a34:	bd80      	pop	{r7, pc}
 8000a36:	bf00      	nop
 8000a38:	200001f4 	.word	0x200001f4

08000a3c <TIM1_TRG_COM_TIM17_IRQHandler>:

/**
  * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
  */
void TIM1_TRG_COM_TIM17_IRQHandler(void)
{
 8000a3c:	b580      	push	{r7, lr}
 8000a3e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */

  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
  HAL_TIM_IRQHandler(&htim17);
 8000a40:	4802      	ldr	r0, [pc, #8]	; (8000a4c <TIM1_TRG_COM_TIM17_IRQHandler+0x10>)
 8000a42:	f002 fb3f 	bl	80030c4 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */

  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
}
 8000a46:	bf00      	nop
 8000a48:	bd80      	pop	{r7, pc}
 8000a4a:	bf00      	nop
 8000a4c:	200000dc 	.word	0x200000dc

08000a50 <SystemInit>:
  * @brief  Setup the microcontroller system.
  * @retval None
  */

void SystemInit(void)
{
 8000a50:	b480      	push	{r7}
 8000a52:	af00      	add	r7, sp, #0
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif

  /* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
 8000a54:	4b06      	ldr	r3, [pc, #24]	; (8000a70 <SystemInit+0x20>)
 8000a56:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8000a5a:	4a05      	ldr	r2, [pc, #20]	; (8000a70 <SystemInit+0x20>)
 8000a5c:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
 8000a60:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
#endif
}
 8000a64:	bf00      	nop
 8000a66:	46bd      	mov	sp, r7
 8000a68:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000a6c:	4770      	bx	lr
 8000a6e:	bf00      	nop
 8000a70:	e000ed00 	.word	0xe000ed00

08000a74 <MX_USART2_UART_Init>:
DMA_HandleTypeDef hdma_usart2_tx;

/* USART2 init function */

void MX_USART2_UART_Init(void)
{
 8000a74:	b580      	push	{r7, lr}
 8000a76:	af00      	add	r7, sp, #0
  /* USER CODE END USART2_Init 0 */

  /* USER CODE BEGIN USART2_Init 1 */

  /* USER CODE END USART2_Init 1 */
  huart2.Instance = USART2;
 8000a78:	4b14      	ldr	r3, [pc, #80]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000a7a:	4a15      	ldr	r2, [pc, #84]	; (8000ad0 <MX_USART2_UART_Init+0x5c>)
 8000a7c:	601a      	str	r2, [r3, #0]
  huart2.Init.BaudRate = 115200;
 8000a7e:	4b13      	ldr	r3, [pc, #76]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000a80:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
 8000a84:	605a      	str	r2, [r3, #4]
  huart2.Init.WordLength = UART_WORDLENGTH_8B;
 8000a86:	4b11      	ldr	r3, [pc, #68]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000a88:	2200      	movs	r2, #0
 8000a8a:	609a      	str	r2, [r3, #8]
  huart2.Init.StopBits = UART_STOPBITS_1;
 8000a8c:	4b0f      	ldr	r3, [pc, #60]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000a8e:	2200      	movs	r2, #0
 8000a90:	60da      	str	r2, [r3, #12]
  huart2.Init.Parity = UART_PARITY_NONE;
 8000a92:	4b0e      	ldr	r3, [pc, #56]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000a94:	2200      	movs	r2, #0
 8000a96:	611a      	str	r2, [r3, #16]
  huart2.Init.Mode = UART_MODE_TX_RX;
 8000a98:	4b0c      	ldr	r3, [pc, #48]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000a9a:	220c      	movs	r2, #12
 8000a9c:	615a      	str	r2, [r3, #20]
  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8000a9e:	4b0b      	ldr	r3, [pc, #44]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000aa0:	2200      	movs	r2, #0
 8000aa2:	619a      	str	r2, [r3, #24]
  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 8000aa4:	4b09      	ldr	r3, [pc, #36]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000aa6:	2200      	movs	r2, #0
 8000aa8:	61da      	str	r2, [r3, #28]
  huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 8000aaa:	4b08      	ldr	r3, [pc, #32]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000aac:	2200      	movs	r2, #0
 8000aae:	621a      	str	r2, [r3, #32]
  huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 8000ab0:	4b06      	ldr	r3, [pc, #24]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000ab2:	2200      	movs	r2, #0
 8000ab4:	625a      	str	r2, [r3, #36]	; 0x24
  if (HAL_UART_Init(&huart2) != HAL_OK)
 8000ab6:	4805      	ldr	r0, [pc, #20]	; (8000acc <MX_USART2_UART_Init+0x58>)
 8000ab8:	f002 fd04 	bl	80034c4 <HAL_UART_Init>
 8000abc:	4603      	mov	r3, r0
 8000abe:	2b00      	cmp	r3, #0
 8000ac0:	d001      	beq.n	8000ac6 <MX_USART2_UART_Init+0x52>
  {
    Error_Handler();
 8000ac2:	f7ff fe69 	bl	8000798 <Error_Handler>
  }
  /* USER CODE BEGIN USART2_Init 2 */

  /* USER CODE END USART2_Init 2 */

}
 8000ac6:	bf00      	nop
 8000ac8:	bd80      	pop	{r7, pc}
 8000aca:	bf00      	nop
 8000acc:	20000128 	.word	0x20000128
 8000ad0:	40004400 	.word	0x40004400

08000ad4 <HAL_UART_MspInit>:

void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
 8000ad4:	b580      	push	{r7, lr}
 8000ad6:	b0ac      	sub	sp, #176	; 0xb0
 8000ad8:	af00      	add	r7, sp, #0
 8000ada:	6078      	str	r0, [r7, #4]

  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000adc:	f107 039c 	add.w	r3, r7, #156	; 0x9c
 8000ae0:	2200      	movs	r2, #0
 8000ae2:	601a      	str	r2, [r3, #0]
 8000ae4:	605a      	str	r2, [r3, #4]
 8000ae6:	609a      	str	r2, [r3, #8]
 8000ae8:	60da      	str	r2, [r3, #12]
 8000aea:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8000aec:	f107 0314 	add.w	r3, r7, #20
 8000af0:	2288      	movs	r2, #136	; 0x88
 8000af2:	2100      	movs	r1, #0
 8000af4:	4618      	mov	r0, r3
 8000af6:	f005 ffdd 	bl	8006ab4 <memset>
  if(uartHandle->Instance==USART2)
 8000afa:	687b      	ldr	r3, [r7, #4]
 8000afc:	681b      	ldr	r3, [r3, #0]
 8000afe:	4a4c      	ldr	r2, [pc, #304]	; (8000c30 <HAL_UART_MspInit+0x15c>)
 8000b00:	4293      	cmp	r3, r2
 8000b02:	f040 8090 	bne.w	8000c26 <HAL_UART_MspInit+0x152>

  /* USER CODE END USART2_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
 8000b06:	2302      	movs	r3, #2
 8000b08:	617b      	str	r3, [r7, #20]
    PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
 8000b0a:	2300      	movs	r3, #0
 8000b0c:	653b      	str	r3, [r7, #80]	; 0x50
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8000b0e:	f107 0314 	add.w	r3, r7, #20
 8000b12:	4618      	mov	r0, r3
 8000b14:	f001 fbce 	bl	80022b4 <HAL_RCCEx_PeriphCLKConfig>
 8000b18:	4603      	mov	r3, r0
 8000b1a:	2b00      	cmp	r3, #0
 8000b1c:	d001      	beq.n	8000b22 <HAL_UART_MspInit+0x4e>
    {
      Error_Handler();
 8000b1e:	f7ff fe3b 	bl	8000798 <Error_Handler>
    }

    /* USART2 clock enable */
    __HAL_RCC_USART2_CLK_ENABLE();
 8000b22:	4b44      	ldr	r3, [pc, #272]	; (8000c34 <HAL_UART_MspInit+0x160>)
 8000b24:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8000b26:	4a43      	ldr	r2, [pc, #268]	; (8000c34 <HAL_UART_MspInit+0x160>)
 8000b28:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 8000b2c:	6593      	str	r3, [r2, #88]	; 0x58
 8000b2e:	4b41      	ldr	r3, [pc, #260]	; (8000c34 <HAL_UART_MspInit+0x160>)
 8000b30:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8000b32:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8000b36:	613b      	str	r3, [r7, #16]
 8000b38:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8000b3a:	4b3e      	ldr	r3, [pc, #248]	; (8000c34 <HAL_UART_MspInit+0x160>)
 8000b3c:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8000b3e:	4a3d      	ldr	r2, [pc, #244]	; (8000c34 <HAL_UART_MspInit+0x160>)
 8000b40:	f043 0301 	orr.w	r3, r3, #1
 8000b44:	64d3      	str	r3, [r2, #76]	; 0x4c
 8000b46:	4b3b      	ldr	r3, [pc, #236]	; (8000c34 <HAL_UART_MspInit+0x160>)
 8000b48:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8000b4a:	f003 0301 	and.w	r3, r3, #1
 8000b4e:	60fb      	str	r3, [r7, #12]
 8000b50:	68fb      	ldr	r3, [r7, #12]
    /**USART2 GPIO Configuration
    PA2     ------> USART2_TX
    PA3     ------> USART2_RX
    */
    GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
 8000b52:	230c      	movs	r3, #12
 8000b54:	f8c7 309c 	str.w	r3, [r7, #156]	; 0x9c
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000b58:	2302      	movs	r3, #2
 8000b5a:	f8c7 30a0 	str.w	r3, [r7, #160]	; 0xa0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000b5e:	2300      	movs	r3, #0
 8000b60:	f8c7 30a4 	str.w	r3, [r7, #164]	; 0xa4
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000b64:	2303      	movs	r3, #3
 8000b66:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
 8000b6a:	2307      	movs	r3, #7
 8000b6c:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000b70:	f107 039c 	add.w	r3, r7, #156	; 0x9c
 8000b74:	4619      	mov	r1, r3
 8000b76:	f04f 4090 	mov.w	r0, #1207959552	; 0x48000000
 8000b7a:	f000 fb19 	bl	80011b0 <HAL_GPIO_Init>

    /* USART2 DMA Init */
    /* USART2_RX Init */
    hdma_usart2_rx.Instance = DMA1_Channel6;
 8000b7e:	4b2e      	ldr	r3, [pc, #184]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000b80:	4a2e      	ldr	r2, [pc, #184]	; (8000c3c <HAL_UART_MspInit+0x168>)
 8000b82:	601a      	str	r2, [r3, #0]
    hdma_usart2_rx.Init.Request = DMA_REQUEST_2;
 8000b84:	4b2c      	ldr	r3, [pc, #176]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000b86:	2202      	movs	r2, #2
 8000b88:	605a      	str	r2, [r3, #4]
    hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8000b8a:	4b2b      	ldr	r3, [pc, #172]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000b8c:	2200      	movs	r2, #0
 8000b8e:	609a      	str	r2, [r3, #8]
    hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
 8000b90:	4b29      	ldr	r3, [pc, #164]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000b92:	2200      	movs	r2, #0
 8000b94:	60da      	str	r2, [r3, #12]
    hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
 8000b96:	4b28      	ldr	r3, [pc, #160]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000b98:	2280      	movs	r2, #128	; 0x80
 8000b9a:	611a      	str	r2, [r3, #16]
    hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 8000b9c:	4b26      	ldr	r3, [pc, #152]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000b9e:	2200      	movs	r2, #0
 8000ba0:	615a      	str	r2, [r3, #20]
    hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 8000ba2:	4b25      	ldr	r3, [pc, #148]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000ba4:	2200      	movs	r2, #0
 8000ba6:	619a      	str	r2, [r3, #24]
    hdma_usart2_rx.Init.Mode = DMA_NORMAL;
 8000ba8:	4b23      	ldr	r3, [pc, #140]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000baa:	2200      	movs	r2, #0
 8000bac:	61da      	str	r2, [r3, #28]
    hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
 8000bae:	4b22      	ldr	r3, [pc, #136]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000bb0:	f44f 5280 	mov.w	r2, #4096	; 0x1000
 8000bb4:	621a      	str	r2, [r3, #32]
    if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
 8000bb6:	4820      	ldr	r0, [pc, #128]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000bb8:	f000 f992 	bl	8000ee0 <HAL_DMA_Init>
 8000bbc:	4603      	mov	r3, r0
 8000bbe:	2b00      	cmp	r3, #0
 8000bc0:	d001      	beq.n	8000bc6 <HAL_UART_MspInit+0xf2>
    {
      Error_Handler();
 8000bc2:	f7ff fde9 	bl	8000798 <Error_Handler>
    }

    __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx);
 8000bc6:	687b      	ldr	r3, [r7, #4]
 8000bc8:	4a1b      	ldr	r2, [pc, #108]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000bca:	671a      	str	r2, [r3, #112]	; 0x70
 8000bcc:	4a1a      	ldr	r2, [pc, #104]	; (8000c38 <HAL_UART_MspInit+0x164>)
 8000bce:	687b      	ldr	r3, [r7, #4]
 8000bd0:	6293      	str	r3, [r2, #40]	; 0x28

    /* USART2_TX Init */
    hdma_usart2_tx.Instance = DMA1_Channel7;
 8000bd2:	4b1b      	ldr	r3, [pc, #108]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000bd4:	4a1b      	ldr	r2, [pc, #108]	; (8000c44 <HAL_UART_MspInit+0x170>)
 8000bd6:	601a      	str	r2, [r3, #0]
    hdma_usart2_tx.Init.Request = DMA_REQUEST_2;
 8000bd8:	4b19      	ldr	r3, [pc, #100]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000bda:	2202      	movs	r2, #2
 8000bdc:	605a      	str	r2, [r3, #4]
    hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 8000bde:	4b18      	ldr	r3, [pc, #96]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000be0:	2210      	movs	r2, #16
 8000be2:	609a      	str	r2, [r3, #8]
    hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 8000be4:	4b16      	ldr	r3, [pc, #88]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000be6:	2200      	movs	r2, #0
 8000be8:	60da      	str	r2, [r3, #12]
    hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
 8000bea:	4b15      	ldr	r3, [pc, #84]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000bec:	2280      	movs	r2, #128	; 0x80
 8000bee:	611a      	str	r2, [r3, #16]
    hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 8000bf0:	4b13      	ldr	r3, [pc, #76]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000bf2:	2200      	movs	r2, #0
 8000bf4:	615a      	str	r2, [r3, #20]
    hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 8000bf6:	4b12      	ldr	r3, [pc, #72]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000bf8:	2200      	movs	r2, #0
 8000bfa:	619a      	str	r2, [r3, #24]
    hdma_usart2_tx.Init.Mode = DMA_NORMAL;
 8000bfc:	4b10      	ldr	r3, [pc, #64]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000bfe:	2200      	movs	r2, #0
 8000c00:	61da      	str	r2, [r3, #28]
    hdma_usart2_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
 8000c02:	4b0f      	ldr	r3, [pc, #60]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000c04:	f44f 5280 	mov.w	r2, #4096	; 0x1000
 8000c08:	621a      	str	r2, [r3, #32]
    if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
 8000c0a:	480d      	ldr	r0, [pc, #52]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000c0c:	f000 f968 	bl	8000ee0 <HAL_DMA_Init>
 8000c10:	4603      	mov	r3, r0
 8000c12:	2b00      	cmp	r3, #0
 8000c14:	d001      	beq.n	8000c1a <HAL_UART_MspInit+0x146>
    {
      Error_Handler();
 8000c16:	f7ff fdbf 	bl	8000798 <Error_Handler>
    }

    __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx);
 8000c1a:	687b      	ldr	r3, [r7, #4]
 8000c1c:	4a08      	ldr	r2, [pc, #32]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000c1e:	66da      	str	r2, [r3, #108]	; 0x6c
 8000c20:	4a07      	ldr	r2, [pc, #28]	; (8000c40 <HAL_UART_MspInit+0x16c>)
 8000c22:	687b      	ldr	r3, [r7, #4]
 8000c24:	6293      	str	r3, [r2, #40]	; 0x28

  /* USER CODE BEGIN USART2_MspInit 1 */

  /* USER CODE END USART2_MspInit 1 */
  }
}
 8000c26:	bf00      	nop
 8000c28:	37b0      	adds	r7, #176	; 0xb0
 8000c2a:	46bd      	mov	sp, r7
 8000c2c:	bd80      	pop	{r7, pc}
 8000c2e:	bf00      	nop
 8000c30:	40004400 	.word	0x40004400
 8000c34:	40021000 	.word	0x40021000
 8000c38:	200001ac 	.word	0x200001ac
 8000c3c:	4002006c 	.word	0x4002006c
 8000c40:	200001f4 	.word	0x200001f4
 8000c44:	40020080 	.word	0x40020080

08000c48 <Reset_Handler>:

    .section	.text.Reset_Handler
	.weak	Reset_Handler
	.type	Reset_Handler, %function
Reset_Handler:
  ldr   sp, =_estack    /* Set stack pointer */
 8000c48:	f8df d034 	ldr.w	sp, [pc, #52]	; 8000c80 <LoopForever+0x2>

/* Call the clock system initialization function.*/
    bl  SystemInit
 8000c4c:	f7ff ff00 	bl	8000a50 <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 8000c50:	480c      	ldr	r0, [pc, #48]	; (8000c84 <LoopForever+0x6>)
  ldr r1, =_edata
 8000c52:	490d      	ldr	r1, [pc, #52]	; (8000c88 <LoopForever+0xa>)
  ldr r2, =_sidata
 8000c54:	4a0d      	ldr	r2, [pc, #52]	; (8000c8c <LoopForever+0xe>)
  movs r3, #0
 8000c56:	2300      	movs	r3, #0
  b LoopCopyDataInit
 8000c58:	e002      	b.n	8000c60 <LoopCopyDataInit>

08000c5a <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 8000c5a:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 8000c5c:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 8000c5e:	3304      	adds	r3, #4

08000c60 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8000c60:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8000c62:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8000c64:	d3f9      	bcc.n	8000c5a <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 8000c66:	4a0a      	ldr	r2, [pc, #40]	; (8000c90 <LoopForever+0x12>)
  ldr r4, =_ebss
 8000c68:	4c0a      	ldr	r4, [pc, #40]	; (8000c94 <LoopForever+0x16>)
  movs r3, #0
 8000c6a:	2300      	movs	r3, #0
  b LoopFillZerobss
 8000c6c:	e001      	b.n	8000c72 <LoopFillZerobss>

08000c6e <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 8000c6e:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8000c70:	3204      	adds	r2, #4

08000c72 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8000c72:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8000c74:	d3fb      	bcc.n	8000c6e <FillZerobss>

/* Call static constructors */
    bl __libc_init_array
 8000c76:	f005 fee9 	bl	8006a4c <__libc_init_array>
/* Call the application's entry point.*/
	bl	main
 8000c7a:	f7ff fcfb 	bl	8000674 <main>

08000c7e <LoopForever>:

LoopForever:
    b LoopForever
 8000c7e:	e7fe      	b.n	8000c7e <LoopForever>
  ldr   sp, =_estack    /* Set stack pointer */
 8000c80:	20018000 	.word	0x20018000
  ldr r0, =_sdata
 8000c84:	20000000 	.word	0x20000000
  ldr r1, =_edata
 8000c88:	20000084 	.word	0x20000084
  ldr r2, =_sidata
 8000c8c:	08006d90 	.word	0x08006d90
  ldr r2, =_sbss
 8000c90:	20000084 	.word	0x20000084
  ldr r4, =_ebss
 8000c94:	20003f38 	.word	0x20003f38

08000c98 <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section	.text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
	b	Infinite_Loop
 8000c98:	e7fe      	b.n	8000c98 <ADC1_2_IRQHandler>
	...

08000c9c <HAL_Init>:
  *         each 1ms in the SysTick_Handler() interrupt handler.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 8000c9c:	b580      	push	{r7, lr}
 8000c9e:	b082      	sub	sp, #8
 8000ca0:	af00      	add	r7, sp, #0
  HAL_StatusTypeDef  status = HAL_OK;
 8000ca2:	2300      	movs	r3, #0
 8000ca4:	71fb      	strb	r3, [r7, #7]
#if (DATA_CACHE_ENABLE == 0)
   __HAL_FLASH_DATA_CACHE_DISABLE();
#endif /* DATA_CACHE_ENABLE */

#if (PREFETCH_ENABLE != 0)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8000ca6:	4b0c      	ldr	r3, [pc, #48]	; (8000cd8 <HAL_Init+0x3c>)
 8000ca8:	681b      	ldr	r3, [r3, #0]
 8000caa:	4a0b      	ldr	r2, [pc, #44]	; (8000cd8 <HAL_Init+0x3c>)
 8000cac:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8000cb0:	6013      	str	r3, [r2, #0]
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8000cb2:	2003      	movs	r0, #3
 8000cb4:	f000 f8df 	bl	8000e76 <HAL_NVIC_SetPriorityGrouping>

  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 8000cb8:	200f      	movs	r0, #15
 8000cba:	f7ff fe3f 	bl	800093c <HAL_InitTick>
 8000cbe:	4603      	mov	r3, r0
 8000cc0:	2b00      	cmp	r3, #0
 8000cc2:	d002      	beq.n	8000cca <HAL_Init+0x2e>
  {
    status = HAL_ERROR;
 8000cc4:	2301      	movs	r3, #1
 8000cc6:	71fb      	strb	r3, [r7, #7]
 8000cc8:	e001      	b.n	8000cce <HAL_Init+0x32>
  }
  else
  {
    /* Init the low level hardware */
    HAL_MspInit();
 8000cca:	f7ff fe0f 	bl	80008ec <HAL_MspInit>
  }

  /* Return function status */
  return status;
 8000cce:	79fb      	ldrb	r3, [r7, #7]
}
 8000cd0:	4618      	mov	r0, r3
 8000cd2:	3708      	adds	r7, #8
 8000cd4:	46bd      	mov	sp, r7
 8000cd6:	bd80      	pop	{r7, pc}
 8000cd8:	40022000 	.word	0x40022000

08000cdc <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8000cdc:	b480      	push	{r7}
 8000cde:	af00      	add	r7, sp, #0
  uwTick += (uint32_t)uwTickFreq;
 8000ce0:	4b06      	ldr	r3, [pc, #24]	; (8000cfc <HAL_IncTick+0x20>)
 8000ce2:	781b      	ldrb	r3, [r3, #0]
 8000ce4:	461a      	mov	r2, r3
 8000ce6:	4b06      	ldr	r3, [pc, #24]	; (8000d00 <HAL_IncTick+0x24>)
 8000ce8:	681b      	ldr	r3, [r3, #0]
 8000cea:	4413      	add	r3, r2
 8000cec:	4a04      	ldr	r2, [pc, #16]	; (8000d00 <HAL_IncTick+0x24>)
 8000cee:	6013      	str	r3, [r2, #0]
}
 8000cf0:	bf00      	nop
 8000cf2:	46bd      	mov	sp, r7
 8000cf4:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000cf8:	4770      	bx	lr
 8000cfa:	bf00      	nop
 8000cfc:	20000008 	.word	0x20000008
 8000d00:	2000023c 	.word	0x2000023c

08000d04 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8000d04:	b480      	push	{r7}
 8000d06:	af00      	add	r7, sp, #0
  return uwTick;
 8000d08:	4b03      	ldr	r3, [pc, #12]	; (8000d18 <HAL_GetTick+0x14>)
 8000d0a:	681b      	ldr	r3, [r3, #0]
}
 8000d0c:	4618      	mov	r0, r3
 8000d0e:	46bd      	mov	sp, r7
 8000d10:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000d14:	4770      	bx	lr
 8000d16:	bf00      	nop
 8000d18:	2000023c 	.word	0x2000023c

08000d1c <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8000d1c:	b480      	push	{r7}
 8000d1e:	b085      	sub	sp, #20
 8000d20:	af00      	add	r7, sp, #0
 8000d22:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8000d24:	687b      	ldr	r3, [r7, #4]
 8000d26:	f003 0307 	and.w	r3, r3, #7
 8000d2a:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8000d2c:	4b0c      	ldr	r3, [pc, #48]	; (8000d60 <__NVIC_SetPriorityGrouping+0x44>)
 8000d2e:	68db      	ldr	r3, [r3, #12]
 8000d30:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8000d32:	68ba      	ldr	r2, [r7, #8]
 8000d34:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
 8000d38:	4013      	ands	r3, r2
 8000d3a:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 8000d3c:	68fb      	ldr	r3, [r7, #12]
 8000d3e:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 8000d40:	68bb      	ldr	r3, [r7, #8]
 8000d42:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 8000d44:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 8000d48:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 8000d4c:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 8000d4e:	4a04      	ldr	r2, [pc, #16]	; (8000d60 <__NVIC_SetPriorityGrouping+0x44>)
 8000d50:	68bb      	ldr	r3, [r7, #8]
 8000d52:	60d3      	str	r3, [r2, #12]
}
 8000d54:	bf00      	nop
 8000d56:	3714      	adds	r7, #20
 8000d58:	46bd      	mov	sp, r7
 8000d5a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000d5e:	4770      	bx	lr
 8000d60:	e000ed00 	.word	0xe000ed00

08000d64 <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 8000d64:	b480      	push	{r7}
 8000d66:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8000d68:	4b04      	ldr	r3, [pc, #16]	; (8000d7c <__NVIC_GetPriorityGrouping+0x18>)
 8000d6a:	68db      	ldr	r3, [r3, #12]
 8000d6c:	0a1b      	lsrs	r3, r3, #8
 8000d6e:	f003 0307 	and.w	r3, r3, #7
}
 8000d72:	4618      	mov	r0, r3
 8000d74:	46bd      	mov	sp, r7
 8000d76:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000d7a:	4770      	bx	lr
 8000d7c:	e000ed00 	.word	0xe000ed00

08000d80 <__NVIC_EnableIRQ>:
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
 8000d80:	b480      	push	{r7}
 8000d82:	b083      	sub	sp, #12
 8000d84:	af00      	add	r7, sp, #0
 8000d86:	4603      	mov	r3, r0
 8000d88:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8000d8a:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000d8e:	2b00      	cmp	r3, #0
 8000d90:	db0b      	blt.n	8000daa <__NVIC_EnableIRQ+0x2a>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 8000d92:	79fb      	ldrb	r3, [r7, #7]
 8000d94:	f003 021f 	and.w	r2, r3, #31
 8000d98:	4907      	ldr	r1, [pc, #28]	; (8000db8 <__NVIC_EnableIRQ+0x38>)
 8000d9a:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000d9e:	095b      	lsrs	r3, r3, #5
 8000da0:	2001      	movs	r0, #1
 8000da2:	fa00 f202 	lsl.w	r2, r0, r2
 8000da6:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    __COMPILER_BARRIER();
  }
}
 8000daa:	bf00      	nop
 8000dac:	370c      	adds	r7, #12
 8000dae:	46bd      	mov	sp, r7
 8000db0:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000db4:	4770      	bx	lr
 8000db6:	bf00      	nop
 8000db8:	e000e100 	.word	0xe000e100

08000dbc <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8000dbc:	b480      	push	{r7}
 8000dbe:	b083      	sub	sp, #12
 8000dc0:	af00      	add	r7, sp, #0
 8000dc2:	4603      	mov	r3, r0
 8000dc4:	6039      	str	r1, [r7, #0]
 8000dc6:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8000dc8:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000dcc:	2b00      	cmp	r3, #0
 8000dce:	db0a      	blt.n	8000de6 <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000dd0:	683b      	ldr	r3, [r7, #0]
 8000dd2:	b2da      	uxtb	r2, r3
 8000dd4:	490c      	ldr	r1, [pc, #48]	; (8000e08 <__NVIC_SetPriority+0x4c>)
 8000dd6:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000dda:	0112      	lsls	r2, r2, #4
 8000ddc:	b2d2      	uxtb	r2, r2
 8000dde:	440b      	add	r3, r1
 8000de0:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 8000de4:	e00a      	b.n	8000dfc <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000de6:	683b      	ldr	r3, [r7, #0]
 8000de8:	b2da      	uxtb	r2, r3
 8000dea:	4908      	ldr	r1, [pc, #32]	; (8000e0c <__NVIC_SetPriority+0x50>)
 8000dec:	79fb      	ldrb	r3, [r7, #7]
 8000dee:	f003 030f 	and.w	r3, r3, #15
 8000df2:	3b04      	subs	r3, #4
 8000df4:	0112      	lsls	r2, r2, #4
 8000df6:	b2d2      	uxtb	r2, r2
 8000df8:	440b      	add	r3, r1
 8000dfa:	761a      	strb	r2, [r3, #24]
}
 8000dfc:	bf00      	nop
 8000dfe:	370c      	adds	r7, #12
 8000e00:	46bd      	mov	sp, r7
 8000e02:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000e06:	4770      	bx	lr
 8000e08:	e000e100 	.word	0xe000e100
 8000e0c:	e000ed00 	.word	0xe000ed00

08000e10 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8000e10:	b480      	push	{r7}
 8000e12:	b089      	sub	sp, #36	; 0x24
 8000e14:	af00      	add	r7, sp, #0
 8000e16:	60f8      	str	r0, [r7, #12]
 8000e18:	60b9      	str	r1, [r7, #8]
 8000e1a:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8000e1c:	68fb      	ldr	r3, [r7, #12]
 8000e1e:	f003 0307 	and.w	r3, r3, #7
 8000e22:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8000e24:	69fb      	ldr	r3, [r7, #28]
 8000e26:	f1c3 0307 	rsb	r3, r3, #7
 8000e2a:	2b04      	cmp	r3, #4
 8000e2c:	bf28      	it	cs
 8000e2e:	2304      	movcs	r3, #4
 8000e30:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000e32:	69fb      	ldr	r3, [r7, #28]
 8000e34:	3304      	adds	r3, #4
 8000e36:	2b06      	cmp	r3, #6
 8000e38:	d902      	bls.n	8000e40 <NVIC_EncodePriority+0x30>
 8000e3a:	69fb      	ldr	r3, [r7, #28]
 8000e3c:	3b03      	subs	r3, #3
 8000e3e:	e000      	b.n	8000e42 <NVIC_EncodePriority+0x32>
 8000e40:	2300      	movs	r3, #0
 8000e42:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000e44:	f04f 32ff 	mov.w	r2, #4294967295
 8000e48:	69bb      	ldr	r3, [r7, #24]
 8000e4a:	fa02 f303 	lsl.w	r3, r2, r3
 8000e4e:	43da      	mvns	r2, r3
 8000e50:	68bb      	ldr	r3, [r7, #8]
 8000e52:	401a      	ands	r2, r3
 8000e54:	697b      	ldr	r3, [r7, #20]
 8000e56:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8000e58:	f04f 31ff 	mov.w	r1, #4294967295
 8000e5c:	697b      	ldr	r3, [r7, #20]
 8000e5e:	fa01 f303 	lsl.w	r3, r1, r3
 8000e62:	43d9      	mvns	r1, r3
 8000e64:	687b      	ldr	r3, [r7, #4]
 8000e66:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000e68:	4313      	orrs	r3, r2
         );
}
 8000e6a:	4618      	mov	r0, r3
 8000e6c:	3724      	adds	r7, #36	; 0x24
 8000e6e:	46bd      	mov	sp, r7
 8000e70:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000e74:	4770      	bx	lr

08000e76 <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
  *         The pending IRQ priority will be managed only by the subpriority.
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8000e76:	b580      	push	{r7, lr}
 8000e78:	b082      	sub	sp, #8
 8000e7a:	af00      	add	r7, sp, #0
 8000e7c:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));

  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 8000e7e:	6878      	ldr	r0, [r7, #4]
 8000e80:	f7ff ff4c 	bl	8000d1c <__NVIC_SetPriorityGrouping>
}
 8000e84:	bf00      	nop
 8000e86:	3708      	adds	r7, #8
 8000e88:	46bd      	mov	sp, r7
 8000e8a:	bd80      	pop	{r7, pc}

08000e8c <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8000e8c:	b580      	push	{r7, lr}
 8000e8e:	b086      	sub	sp, #24
 8000e90:	af00      	add	r7, sp, #0
 8000e92:	4603      	mov	r3, r0
 8000e94:	60b9      	str	r1, [r7, #8]
 8000e96:	607a      	str	r2, [r7, #4]
 8000e98:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00;
 8000e9a:	2300      	movs	r3, #0
 8000e9c:	617b      	str	r3, [r7, #20]

  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));

  prioritygroup = NVIC_GetPriorityGrouping();
 8000e9e:	f7ff ff61 	bl	8000d64 <__NVIC_GetPriorityGrouping>
 8000ea2:	6178      	str	r0, [r7, #20]

  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 8000ea4:	687a      	ldr	r2, [r7, #4]
 8000ea6:	68b9      	ldr	r1, [r7, #8]
 8000ea8:	6978      	ldr	r0, [r7, #20]
 8000eaa:	f7ff ffb1 	bl	8000e10 <NVIC_EncodePriority>
 8000eae:	4602      	mov	r2, r0
 8000eb0:	f997 300f 	ldrsb.w	r3, [r7, #15]
 8000eb4:	4611      	mov	r1, r2
 8000eb6:	4618      	mov	r0, r3
 8000eb8:	f7ff ff80 	bl	8000dbc <__NVIC_SetPriority>
}
 8000ebc:	bf00      	nop
 8000ebe:	3718      	adds	r7, #24
 8000ec0:	46bd      	mov	sp, r7
 8000ec2:	bd80      	pop	{r7, pc}

08000ec4 <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 8000ec4:	b580      	push	{r7, lr}
 8000ec6:	b082      	sub	sp, #8
 8000ec8:	af00      	add	r7, sp, #0
 8000eca:	4603      	mov	r3, r0
 8000ecc:	71fb      	strb	r3, [r7, #7]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 8000ece:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000ed2:	4618      	mov	r0, r3
 8000ed4:	f7ff ff54 	bl	8000d80 <__NVIC_EnableIRQ>
}
 8000ed8:	bf00      	nop
 8000eda:	3708      	adds	r7, #8
 8000edc:	46bd      	mov	sp, r7
 8000ede:	bd80      	pop	{r7, pc}

08000ee0 <HAL_DMA_Init>:
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  *              the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 8000ee0:	b480      	push	{r7}
 8000ee2:	b085      	sub	sp, #20
 8000ee4:	af00      	add	r7, sp, #0
 8000ee6:	6078      	str	r0, [r7, #4]
  uint32_t tmp;

  /* Check the DMA handle allocation */
  if(hdma == NULL)
 8000ee8:	687b      	ldr	r3, [r7, #4]
 8000eea:	2b00      	cmp	r3, #0
 8000eec:	d101      	bne.n	8000ef2 <HAL_DMA_Init+0x12>
  {
    return HAL_ERROR;
 8000eee:	2301      	movs	r3, #1
 8000ef0:	e098      	b.n	8001024 <HAL_DMA_Init+0x144>
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

  assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));

  /* Compute the channel index */
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 8000ef2:	687b      	ldr	r3, [r7, #4]
 8000ef4:	681b      	ldr	r3, [r3, #0]
 8000ef6:	461a      	mov	r2, r3
 8000ef8:	4b4d      	ldr	r3, [pc, #308]	; (8001030 <HAL_DMA_Init+0x150>)
 8000efa:	429a      	cmp	r2, r3
 8000efc:	d80f      	bhi.n	8000f1e <HAL_DMA_Init+0x3e>
  {
    /* DMA1 */
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
 8000efe:	687b      	ldr	r3, [r7, #4]
 8000f00:	681b      	ldr	r3, [r3, #0]
 8000f02:	461a      	mov	r2, r3
 8000f04:	4b4b      	ldr	r3, [pc, #300]	; (8001034 <HAL_DMA_Init+0x154>)
 8000f06:	4413      	add	r3, r2
 8000f08:	4a4b      	ldr	r2, [pc, #300]	; (8001038 <HAL_DMA_Init+0x158>)
 8000f0a:	fba2 2303 	umull	r2, r3, r2, r3
 8000f0e:	091b      	lsrs	r3, r3, #4
 8000f10:	009a      	lsls	r2, r3, #2
 8000f12:	687b      	ldr	r3, [r7, #4]
 8000f14:	645a      	str	r2, [r3, #68]	; 0x44
    hdma->DmaBaseAddress = DMA1;
 8000f16:	687b      	ldr	r3, [r7, #4]
 8000f18:	4a48      	ldr	r2, [pc, #288]	; (800103c <HAL_DMA_Init+0x15c>)
 8000f1a:	641a      	str	r2, [r3, #64]	; 0x40
 8000f1c:	e00e      	b.n	8000f3c <HAL_DMA_Init+0x5c>
  }
  else
  {
    /* DMA2 */
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
 8000f1e:	687b      	ldr	r3, [r7, #4]
 8000f20:	681b      	ldr	r3, [r3, #0]
 8000f22:	461a      	mov	r2, r3
 8000f24:	4b46      	ldr	r3, [pc, #280]	; (8001040 <HAL_DMA_Init+0x160>)
 8000f26:	4413      	add	r3, r2
 8000f28:	4a43      	ldr	r2, [pc, #268]	; (8001038 <HAL_DMA_Init+0x158>)
 8000f2a:	fba2 2303 	umull	r2, r3, r2, r3
 8000f2e:	091b      	lsrs	r3, r3, #4
 8000f30:	009a      	lsls	r2, r3, #2
 8000f32:	687b      	ldr	r3, [r7, #4]
 8000f34:	645a      	str	r2, [r3, #68]	; 0x44
    hdma->DmaBaseAddress = DMA2;
 8000f36:	687b      	ldr	r3, [r7, #4]
 8000f38:	4a42      	ldr	r2, [pc, #264]	; (8001044 <HAL_DMA_Init+0x164>)
 8000f3a:	641a      	str	r2, [r3, #64]	; 0x40
  }

  /* Change DMA peripheral state */
  hdma->State = HAL_DMA_STATE_BUSY;
 8000f3c:	687b      	ldr	r3, [r7, #4]
 8000f3e:	2202      	movs	r2, #2
 8000f40:	f883 2025 	strb.w	r2, [r3, #37]	; 0x25

  /* Get the CR register value */
  tmp = hdma->Instance->CCR;
 8000f44:	687b      	ldr	r3, [r7, #4]
 8000f46:	681b      	ldr	r3, [r3, #0]
 8000f48:	681b      	ldr	r3, [r3, #0]
 8000f4a:	60fb      	str	r3, [r7, #12]

  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  |
 8000f4c:	68fb      	ldr	r3, [r7, #12]
 8000f4e:	f423 43ff 	bic.w	r3, r3, #32640	; 0x7f80
 8000f52:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 8000f56:	60fb      	str	r3, [r7, #12]
                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
                      DMA_CCR_DIR   | DMA_CCR_MEM2MEM));

  /* Prepare the DMA Channel configuration */
  tmp |=  hdma->Init.Direction        |
 8000f58:	687b      	ldr	r3, [r7, #4]
 8000f5a:	689a      	ldr	r2, [r3, #8]
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8000f5c:	687b      	ldr	r3, [r7, #4]
 8000f5e:	68db      	ldr	r3, [r3, #12]
  tmp |=  hdma->Init.Direction        |
 8000f60:	431a      	orrs	r2, r3
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8000f62:	687b      	ldr	r3, [r7, #4]
 8000f64:	691b      	ldr	r3, [r3, #16]
 8000f66:	431a      	orrs	r2, r3
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8000f68:	687b      	ldr	r3, [r7, #4]
 8000f6a:	695b      	ldr	r3, [r3, #20]
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8000f6c:	431a      	orrs	r2, r3
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8000f6e:	687b      	ldr	r3, [r7, #4]
 8000f70:	699b      	ldr	r3, [r3, #24]
 8000f72:	431a      	orrs	r2, r3
          hdma->Init.Mode                | hdma->Init.Priority;
 8000f74:	687b      	ldr	r3, [r7, #4]
 8000f76:	69db      	ldr	r3, [r3, #28]
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8000f78:	431a      	orrs	r2, r3
          hdma->Init.Mode                | hdma->Init.Priority;
 8000f7a:	687b      	ldr	r3, [r7, #4]
 8000f7c:	6a1b      	ldr	r3, [r3, #32]
 8000f7e:	4313      	orrs	r3, r2
  tmp |=  hdma->Init.Direction        |
 8000f80:	68fa      	ldr	r2, [r7, #12]
 8000f82:	4313      	orrs	r3, r2
 8000f84:	60fb      	str	r3, [r7, #12]

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;
 8000f86:	687b      	ldr	r3, [r7, #4]
 8000f88:	681b      	ldr	r3, [r3, #0]
 8000f8a:	68fa      	ldr	r2, [r7, #12]
 8000f8c:	601a      	str	r2, [r3, #0]
#endif /* DMAMUX1 */

#if !defined (DMAMUX1)

  /* Set request selection */
  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
 8000f8e:	687b      	ldr	r3, [r7, #4]
 8000f90:	689b      	ldr	r3, [r3, #8]
 8000f92:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
 8000f96:	d039      	beq.n	800100c <HAL_DMA_Init+0x12c>
  {
    /* Write to DMA channel selection register */
    if (DMA1 == hdma->DmaBaseAddress)
 8000f98:	687b      	ldr	r3, [r7, #4]
 8000f9a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000f9c:	4a27      	ldr	r2, [pc, #156]	; (800103c <HAL_DMA_Init+0x15c>)
 8000f9e:	4293      	cmp	r3, r2
 8000fa0:	d11a      	bne.n	8000fd8 <HAL_DMA_Init+0xf8>
    {
      /* Reset request selection for DMA1 Channelx */
      DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
 8000fa2:	4b29      	ldr	r3, [pc, #164]	; (8001048 <HAL_DMA_Init+0x168>)
 8000fa4:	681a      	ldr	r2, [r3, #0]
 8000fa6:	687b      	ldr	r3, [r7, #4]
 8000fa8:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000faa:	f003 031c 	and.w	r3, r3, #28
 8000fae:	210f      	movs	r1, #15
 8000fb0:	fa01 f303 	lsl.w	r3, r1, r3
 8000fb4:	43db      	mvns	r3, r3
 8000fb6:	4924      	ldr	r1, [pc, #144]	; (8001048 <HAL_DMA_Init+0x168>)
 8000fb8:	4013      	ands	r3, r2
 8000fba:	600b      	str	r3, [r1, #0]

      /* Configure request selection for DMA1 Channelx */
      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
 8000fbc:	4b22      	ldr	r3, [pc, #136]	; (8001048 <HAL_DMA_Init+0x168>)
 8000fbe:	681a      	ldr	r2, [r3, #0]
 8000fc0:	687b      	ldr	r3, [r7, #4]
 8000fc2:	6859      	ldr	r1, [r3, #4]
 8000fc4:	687b      	ldr	r3, [r7, #4]
 8000fc6:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000fc8:	f003 031c 	and.w	r3, r3, #28
 8000fcc:	fa01 f303 	lsl.w	r3, r1, r3
 8000fd0:	491d      	ldr	r1, [pc, #116]	; (8001048 <HAL_DMA_Init+0x168>)
 8000fd2:	4313      	orrs	r3, r2
 8000fd4:	600b      	str	r3, [r1, #0]
 8000fd6:	e019      	b.n	800100c <HAL_DMA_Init+0x12c>
    }
    else /* DMA2 */
    {
      /* Reset request selection for DMA2 Channelx */
      DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
 8000fd8:	4b1c      	ldr	r3, [pc, #112]	; (800104c <HAL_DMA_Init+0x16c>)
 8000fda:	681a      	ldr	r2, [r3, #0]
 8000fdc:	687b      	ldr	r3, [r7, #4]
 8000fde:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000fe0:	f003 031c 	and.w	r3, r3, #28
 8000fe4:	210f      	movs	r1, #15
 8000fe6:	fa01 f303 	lsl.w	r3, r1, r3
 8000fea:	43db      	mvns	r3, r3
 8000fec:	4917      	ldr	r1, [pc, #92]	; (800104c <HAL_DMA_Init+0x16c>)
 8000fee:	4013      	ands	r3, r2
 8000ff0:	600b      	str	r3, [r1, #0]

      /* Configure request selection for DMA2 Channelx */
      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
 8000ff2:	4b16      	ldr	r3, [pc, #88]	; (800104c <HAL_DMA_Init+0x16c>)
 8000ff4:	681a      	ldr	r2, [r3, #0]
 8000ff6:	687b      	ldr	r3, [r7, #4]
 8000ff8:	6859      	ldr	r1, [r3, #4]
 8000ffa:	687b      	ldr	r3, [r7, #4]
 8000ffc:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000ffe:	f003 031c 	and.w	r3, r3, #28
 8001002:	fa01 f303 	lsl.w	r3, r1, r3
 8001006:	4911      	ldr	r1, [pc, #68]	; (800104c <HAL_DMA_Init+0x16c>)
 8001008:	4313      	orrs	r3, r2
 800100a:	600b      	str	r3, [r1, #0]
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
       /* STM32L496xx || STM32L4A6xx                                              */

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 800100c:	687b      	ldr	r3, [r7, #4]
 800100e:	2200      	movs	r2, #0
 8001010:	63da      	str	r2, [r3, #60]	; 0x3c

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 8001012:	687b      	ldr	r3, [r7, #4]
 8001014:	2201      	movs	r2, #1
 8001016:	f883 2025 	strb.w	r2, [r3, #37]	; 0x25

  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;
 800101a:	687b      	ldr	r3, [r7, #4]
 800101c:	2200      	movs	r2, #0
 800101e:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24

  return HAL_OK;
 8001022:	2300      	movs	r3, #0
}
 8001024:	4618      	mov	r0, r3
 8001026:	3714      	adds	r7, #20
 8001028:	46bd      	mov	sp, r7
 800102a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800102e:	4770      	bx	lr
 8001030:	40020407 	.word	0x40020407
 8001034:	bffdfff8 	.word	0xbffdfff8
 8001038:	cccccccd 	.word	0xcccccccd
 800103c:	40020000 	.word	0x40020000
 8001040:	bffdfbf8 	.word	0xbffdfbf8
 8001044:	40020400 	.word	0x40020400
 8001048:	400200a8 	.word	0x400200a8
 800104c:	400204a8 	.word	0x400204a8

08001050 <HAL_DMA_IRQHandler>:
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval None
  */
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
 8001050:	b580      	push	{r7, lr}
 8001052:	b084      	sub	sp, #16
 8001054:	af00      	add	r7, sp, #0
 8001056:	6078      	str	r0, [r7, #4]
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 8001058:	687b      	ldr	r3, [r7, #4]
 800105a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800105c:	681b      	ldr	r3, [r3, #0]
 800105e:	60fb      	str	r3, [r7, #12]
  uint32_t source_it = hdma->Instance->CCR;
 8001060:	687b      	ldr	r3, [r7, #4]
 8001062:	681b      	ldr	r3, [r3, #0]
 8001064:	681b      	ldr	r3, [r3, #0]
 8001066:	60bb      	str	r3, [r7, #8]

  /* Half Transfer Complete Interrupt management ******************************/
  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
 8001068:	687b      	ldr	r3, [r7, #4]
 800106a:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 800106c:	f003 031c 	and.w	r3, r3, #28
 8001070:	2204      	movs	r2, #4
 8001072:	409a      	lsls	r2, r3
 8001074:	68fb      	ldr	r3, [r7, #12]
 8001076:	4013      	ands	r3, r2
 8001078:	2b00      	cmp	r3, #0
 800107a:	d026      	beq.n	80010ca <HAL_DMA_IRQHandler+0x7a>
 800107c:	68bb      	ldr	r3, [r7, #8]
 800107e:	f003 0304 	and.w	r3, r3, #4
 8001082:	2b00      	cmp	r3, #0
 8001084:	d021      	beq.n	80010ca <HAL_DMA_IRQHandler+0x7a>
  {
      /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8001086:	687b      	ldr	r3, [r7, #4]
 8001088:	681b      	ldr	r3, [r3, #0]
 800108a:	681b      	ldr	r3, [r3, #0]
 800108c:	f003 0320 	and.w	r3, r3, #32
 8001090:	2b00      	cmp	r3, #0
 8001092:	d107      	bne.n	80010a4 <HAL_DMA_IRQHandler+0x54>
      {
        /* Disable the half transfer interrupt */
        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 8001094:	687b      	ldr	r3, [r7, #4]
 8001096:	681b      	ldr	r3, [r3, #0]
 8001098:	681a      	ldr	r2, [r3, #0]
 800109a:	687b      	ldr	r3, [r7, #4]
 800109c:	681b      	ldr	r3, [r3, #0]
 800109e:	f022 0204 	bic.w	r2, r2, #4
 80010a2:	601a      	str	r2, [r3, #0]
      }
      /* Clear the half transfer complete flag */
      hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
 80010a4:	687b      	ldr	r3, [r7, #4]
 80010a6:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 80010a8:	f003 021c 	and.w	r2, r3, #28
 80010ac:	687b      	ldr	r3, [r7, #4]
 80010ae:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80010b0:	2104      	movs	r1, #4
 80010b2:	fa01 f202 	lsl.w	r2, r1, r2
 80010b6:	605a      	str	r2, [r3, #4]

      /* DMA peripheral state is not updated in Half Transfer */
      /* but in Transfer Complete case */

      if(hdma->XferHalfCpltCallback != NULL)
 80010b8:	687b      	ldr	r3, [r7, #4]
 80010ba:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80010bc:	2b00      	cmp	r3, #0
 80010be:	d071      	beq.n	80011a4 <HAL_DMA_IRQHandler+0x154>
      {
        /* Half transfer callback */
        hdma->XferHalfCpltCallback(hdma);
 80010c0:	687b      	ldr	r3, [r7, #4]
 80010c2:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80010c4:	6878      	ldr	r0, [r7, #4]
 80010c6:	4798      	blx	r3
      if(hdma->XferHalfCpltCallback != NULL)
 80010c8:	e06c      	b.n	80011a4 <HAL_DMA_IRQHandler+0x154>
      }
  }

  /* Transfer Complete Interrupt management ***********************************/
  else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
 80010ca:	687b      	ldr	r3, [r7, #4]
 80010cc:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 80010ce:	f003 031c 	and.w	r3, r3, #28
 80010d2:	2202      	movs	r2, #2
 80010d4:	409a      	lsls	r2, r3
 80010d6:	68fb      	ldr	r3, [r7, #12]
 80010d8:	4013      	ands	r3, r2
 80010da:	2b00      	cmp	r3, #0
 80010dc:	d02e      	beq.n	800113c <HAL_DMA_IRQHandler+0xec>
 80010de:	68bb      	ldr	r3, [r7, #8]
 80010e0:	f003 0302 	and.w	r3, r3, #2
 80010e4:	2b00      	cmp	r3, #0
 80010e6:	d029      	beq.n	800113c <HAL_DMA_IRQHandler+0xec>
  {
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80010e8:	687b      	ldr	r3, [r7, #4]
 80010ea:	681b      	ldr	r3, [r3, #0]
 80010ec:	681b      	ldr	r3, [r3, #0]
 80010ee:	f003 0320 	and.w	r3, r3, #32
 80010f2:	2b00      	cmp	r3, #0
 80010f4:	d10b      	bne.n	800110e <HAL_DMA_IRQHandler+0xbe>
    {
      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
      /* Disable the transfer complete and error interrupt */
      /* if the DMA mode is not CIRCULAR  */
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
 80010f6:	687b      	ldr	r3, [r7, #4]
 80010f8:	681b      	ldr	r3, [r3, #0]
 80010fa:	681a      	ldr	r2, [r3, #0]
 80010fc:	687b      	ldr	r3, [r7, #4]
 80010fe:	681b      	ldr	r3, [r3, #0]
 8001100:	f022 020a 	bic.w	r2, r2, #10
 8001104:	601a      	str	r2, [r3, #0]

      /* Change the DMA state */
      hdma->State = HAL_DMA_STATE_READY;
 8001106:	687b      	ldr	r3, [r7, #4]
 8001108:	2201      	movs	r2, #1
 800110a:	f883 2025 	strb.w	r2, [r3, #37]	; 0x25
    }
    /* Clear the transfer complete flag */
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));
 800110e:	687b      	ldr	r3, [r7, #4]
 8001110:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8001112:	f003 021c 	and.w	r2, r3, #28
 8001116:	687b      	ldr	r3, [r7, #4]
 8001118:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800111a:	2102      	movs	r1, #2
 800111c:	fa01 f202 	lsl.w	r2, r1, r2
 8001120:	605a      	str	r2, [r3, #4]

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8001122:	687b      	ldr	r3, [r7, #4]
 8001124:	2200      	movs	r2, #0
 8001126:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24

    if(hdma->XferCpltCallback != NULL)
 800112a:	687b      	ldr	r3, [r7, #4]
 800112c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 800112e:	2b00      	cmp	r3, #0
 8001130:	d038      	beq.n	80011a4 <HAL_DMA_IRQHandler+0x154>
    {
      /* Transfer complete callback */
      hdma->XferCpltCallback(hdma);
 8001132:	687b      	ldr	r3, [r7, #4]
 8001134:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8001136:	6878      	ldr	r0, [r7, #4]
 8001138:	4798      	blx	r3
    if(hdma->XferCpltCallback != NULL)
 800113a:	e033      	b.n	80011a4 <HAL_DMA_IRQHandler+0x154>
    }
  }

  /* Transfer Error Interrupt management **************************************/
  else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) !=  0U))
 800113c:	687b      	ldr	r3, [r7, #4]
 800113e:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8001140:	f003 031c 	and.w	r3, r3, #28
 8001144:	2208      	movs	r2, #8
 8001146:	409a      	lsls	r2, r3
 8001148:	68fb      	ldr	r3, [r7, #12]
 800114a:	4013      	ands	r3, r2
 800114c:	2b00      	cmp	r3, #0
 800114e:	d02a      	beq.n	80011a6 <HAL_DMA_IRQHandler+0x156>
 8001150:	68bb      	ldr	r3, [r7, #8]
 8001152:	f003 0308 	and.w	r3, r3, #8
 8001156:	2b00      	cmp	r3, #0
 8001158:	d025      	beq.n	80011a6 <HAL_DMA_IRQHandler+0x156>
  {
    /* When a DMA transfer error occurs */
    /* A hardware clear of its EN bits is performed */
    /* Disable ALL DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 800115a:	687b      	ldr	r3, [r7, #4]
 800115c:	681b      	ldr	r3, [r3, #0]
 800115e:	681a      	ldr	r2, [r3, #0]
 8001160:	687b      	ldr	r3, [r7, #4]
 8001162:	681b      	ldr	r3, [r3, #0]
 8001164:	f022 020e 	bic.w	r2, r2, #14
 8001168:	601a      	str	r2, [r3, #0]

    /* Clear all flags */
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 800116a:	687b      	ldr	r3, [r7, #4]
 800116c:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 800116e:	f003 021c 	and.w	r2, r3, #28
 8001172:	687b      	ldr	r3, [r7, #4]
 8001174:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001176:	2101      	movs	r1, #1
 8001178:	fa01 f202 	lsl.w	r2, r1, r2
 800117c:	605a      	str	r2, [r3, #4]

    /* Update error code */
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 800117e:	687b      	ldr	r3, [r7, #4]
 8001180:	2201      	movs	r2, #1
 8001182:	63da      	str	r2, [r3, #60]	; 0x3c

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 8001184:	687b      	ldr	r3, [r7, #4]
 8001186:	2201      	movs	r2, #1
 8001188:	f883 2025 	strb.w	r2, [r3, #37]	; 0x25

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 800118c:	687b      	ldr	r3, [r7, #4]
 800118e:	2200      	movs	r2, #0
 8001190:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24

    if (hdma->XferErrorCallback != NULL)
 8001194:	687b      	ldr	r3, [r7, #4]
 8001196:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8001198:	2b00      	cmp	r3, #0
 800119a:	d004      	beq.n	80011a6 <HAL_DMA_IRQHandler+0x156>
    {
      /* Transfer error callback */
      hdma->XferErrorCallback(hdma);
 800119c:	687b      	ldr	r3, [r7, #4]
 800119e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 80011a0:	6878      	ldr	r0, [r7, #4]
 80011a2:	4798      	blx	r3
  }
  else
  {
    /* Nothing To Do */
  }
  return;
 80011a4:	bf00      	nop
 80011a6:	bf00      	nop
}
 80011a8:	3710      	adds	r7, #16
 80011aa:	46bd      	mov	sp, r7
 80011ac:	bd80      	pop	{r7, pc}
	...

080011b0 <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 80011b0:	b480      	push	{r7}
 80011b2:	b087      	sub	sp, #28
 80011b4:	af00      	add	r7, sp, #0
 80011b6:	6078      	str	r0, [r7, #4]
 80011b8:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00u;
 80011ba:	2300      	movs	r3, #0
 80011bc:	617b      	str	r3, [r7, #20]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 80011be:	e17f      	b.n	80014c0 <HAL_GPIO_Init+0x310>
  {
    /* Get current io position */
    iocurrent = (GPIO_Init->Pin) & (1uL << position);
 80011c0:	683b      	ldr	r3, [r7, #0]
 80011c2:	681a      	ldr	r2, [r3, #0]
 80011c4:	2101      	movs	r1, #1
 80011c6:	697b      	ldr	r3, [r7, #20]
 80011c8:	fa01 f303 	lsl.w	r3, r1, r3
 80011cc:	4013      	ands	r3, r2
 80011ce:	60fb      	str	r3, [r7, #12]

    if (iocurrent != 0x00u)
 80011d0:	68fb      	ldr	r3, [r7, #12]
 80011d2:	2b00      	cmp	r3, #0
 80011d4:	f000 8171 	beq.w	80014ba <HAL_GPIO_Init+0x30a>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
 80011d8:	683b      	ldr	r3, [r7, #0]
 80011da:	685b      	ldr	r3, [r3, #4]
 80011dc:	f003 0303 	and.w	r3, r3, #3
 80011e0:	2b01      	cmp	r3, #1
 80011e2:	d005      	beq.n	80011f0 <HAL_GPIO_Init+0x40>
 80011e4:	683b      	ldr	r3, [r7, #0]
 80011e6:	685b      	ldr	r3, [r3, #4]
 80011e8:	f003 0303 	and.w	r3, r3, #3
 80011ec:	2b02      	cmp	r3, #2
 80011ee:	d130      	bne.n	8001252 <HAL_GPIO_Init+0xa2>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));

        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 80011f0:	687b      	ldr	r3, [r7, #4]
 80011f2:	689b      	ldr	r3, [r3, #8]
 80011f4:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
 80011f6:	697b      	ldr	r3, [r7, #20]
 80011f8:	005b      	lsls	r3, r3, #1
 80011fa:	2203      	movs	r2, #3
 80011fc:	fa02 f303 	lsl.w	r3, r2, r3
 8001200:	43db      	mvns	r3, r3
 8001202:	693a      	ldr	r2, [r7, #16]
 8001204:	4013      	ands	r3, r2
 8001206:	613b      	str	r3, [r7, #16]
        temp |= (GPIO_Init->Speed << (position * 2u));
 8001208:	683b      	ldr	r3, [r7, #0]
 800120a:	68da      	ldr	r2, [r3, #12]
 800120c:	697b      	ldr	r3, [r7, #20]
 800120e:	005b      	lsls	r3, r3, #1
 8001210:	fa02 f303 	lsl.w	r3, r2, r3
 8001214:	693a      	ldr	r2, [r7, #16]
 8001216:	4313      	orrs	r3, r2
 8001218:	613b      	str	r3, [r7, #16]
        GPIOx->OSPEEDR = temp;
 800121a:	687b      	ldr	r3, [r7, #4]
 800121c:	693a      	ldr	r2, [r7, #16]
 800121e:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 8001220:	687b      	ldr	r3, [r7, #4]
 8001222:	685b      	ldr	r3, [r3, #4]
 8001224:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_OTYPER_OT0 << position) ;
 8001226:	2201      	movs	r2, #1
 8001228:	697b      	ldr	r3, [r7, #20]
 800122a:	fa02 f303 	lsl.w	r3, r2, r3
 800122e:	43db      	mvns	r3, r3
 8001230:	693a      	ldr	r2, [r7, #16]
 8001232:	4013      	ands	r3, r2
 8001234:	613b      	str	r3, [r7, #16]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 8001236:	683b      	ldr	r3, [r7, #0]
 8001238:	685b      	ldr	r3, [r3, #4]
 800123a:	091b      	lsrs	r3, r3, #4
 800123c:	f003 0201 	and.w	r2, r3, #1
 8001240:	697b      	ldr	r3, [r7, #20]
 8001242:	fa02 f303 	lsl.w	r3, r2, r3
 8001246:	693a      	ldr	r2, [r7, #16]
 8001248:	4313      	orrs	r3, r2
 800124a:	613b      	str	r3, [r7, #16]
        GPIOx->OTYPER = temp;
 800124c:	687b      	ldr	r3, [r7, #4]
 800124e:	693a      	ldr	r2, [r7, #16]
 8001250:	605a      	str	r2, [r3, #4]
      }

#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)

      /* In case of Analog mode, check if ADC control mode is selected */
      if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
 8001252:	683b      	ldr	r3, [r7, #0]
 8001254:	685b      	ldr	r3, [r3, #4]
 8001256:	f003 0303 	and.w	r3, r3, #3
 800125a:	2b03      	cmp	r3, #3
 800125c:	d118      	bne.n	8001290 <HAL_GPIO_Init+0xe0>
      {
        /* Configure the IO Output Type */
        temp = GPIOx->ASCR;
 800125e:	687b      	ldr	r3, [r7, #4]
 8001260:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8001262:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_ASCR_ASC0 << position) ;
 8001264:	2201      	movs	r2, #1
 8001266:	697b      	ldr	r3, [r7, #20]
 8001268:	fa02 f303 	lsl.w	r3, r2, r3
 800126c:	43db      	mvns	r3, r3
 800126e:	693a      	ldr	r2, [r7, #16]
 8001270:	4013      	ands	r3, r2
 8001272:	613b      	str	r3, [r7, #16]
        temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
 8001274:	683b      	ldr	r3, [r7, #0]
 8001276:	685b      	ldr	r3, [r3, #4]
 8001278:	08db      	lsrs	r3, r3, #3
 800127a:	f003 0201 	and.w	r2, r3, #1
 800127e:	697b      	ldr	r3, [r7, #20]
 8001280:	fa02 f303 	lsl.w	r3, r2, r3
 8001284:	693a      	ldr	r2, [r7, #16]
 8001286:	4313      	orrs	r3, r2
 8001288:	613b      	str	r3, [r7, #16]
        GPIOx->ASCR = temp;
 800128a:	687b      	ldr	r3, [r7, #4]
 800128c:	693a      	ldr	r2, [r7, #16]
 800128e:	62da      	str	r2, [r3, #44]	; 0x2c
      }

#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */

      /* Activate the Pull-up or Pull down resistor for the current IO */
      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 8001290:	683b      	ldr	r3, [r7, #0]
 8001292:	685b      	ldr	r3, [r3, #4]
 8001294:	f003 0303 	and.w	r3, r3, #3
 8001298:	2b03      	cmp	r3, #3
 800129a:	d017      	beq.n	80012cc <HAL_GPIO_Init+0x11c>
      {
        /* Check the Pull parameter */
        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

        temp = GPIOx->PUPDR;
 800129c:	687b      	ldr	r3, [r7, #4]
 800129e:	68db      	ldr	r3, [r3, #12]
 80012a0:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 80012a2:	697b      	ldr	r3, [r7, #20]
 80012a4:	005b      	lsls	r3, r3, #1
 80012a6:	2203      	movs	r2, #3
 80012a8:	fa02 f303 	lsl.w	r3, r2, r3
 80012ac:	43db      	mvns	r3, r3
 80012ae:	693a      	ldr	r2, [r7, #16]
 80012b0:	4013      	ands	r3, r2
 80012b2:	613b      	str	r3, [r7, #16]
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 80012b4:	683b      	ldr	r3, [r7, #0]
 80012b6:	689a      	ldr	r2, [r3, #8]
 80012b8:	697b      	ldr	r3, [r7, #20]
 80012ba:	005b      	lsls	r3, r3, #1
 80012bc:	fa02 f303 	lsl.w	r3, r2, r3
 80012c0:	693a      	ldr	r2, [r7, #16]
 80012c2:	4313      	orrs	r3, r2
 80012c4:	613b      	str	r3, [r7, #16]
        GPIOx->PUPDR = temp;
 80012c6:	687b      	ldr	r3, [r7, #4]
 80012c8:	693a      	ldr	r2, [r7, #16]
 80012ca:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 80012cc:	683b      	ldr	r3, [r7, #0]
 80012ce:	685b      	ldr	r3, [r3, #4]
 80012d0:	f003 0303 	and.w	r3, r3, #3
 80012d4:	2b02      	cmp	r3, #2
 80012d6:	d123      	bne.n	8001320 <HAL_GPIO_Init+0x170>
        /* Check the Alternate function parameters */
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3u];
 80012d8:	697b      	ldr	r3, [r7, #20]
 80012da:	08da      	lsrs	r2, r3, #3
 80012dc:	687b      	ldr	r3, [r7, #4]
 80012de:	3208      	adds	r2, #8
 80012e0:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 80012e4:	613b      	str	r3, [r7, #16]
        temp &= ~(0xFu << ((position & 0x07u) * 4u));
 80012e6:	697b      	ldr	r3, [r7, #20]
 80012e8:	f003 0307 	and.w	r3, r3, #7
 80012ec:	009b      	lsls	r3, r3, #2
 80012ee:	220f      	movs	r2, #15
 80012f0:	fa02 f303 	lsl.w	r3, r2, r3
 80012f4:	43db      	mvns	r3, r3
 80012f6:	693a      	ldr	r2, [r7, #16]
 80012f8:	4013      	ands	r3, r2
 80012fa:	613b      	str	r3, [r7, #16]
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
 80012fc:	683b      	ldr	r3, [r7, #0]
 80012fe:	691a      	ldr	r2, [r3, #16]
 8001300:	697b      	ldr	r3, [r7, #20]
 8001302:	f003 0307 	and.w	r3, r3, #7
 8001306:	009b      	lsls	r3, r3, #2
 8001308:	fa02 f303 	lsl.w	r3, r2, r3
 800130c:	693a      	ldr	r2, [r7, #16]
 800130e:	4313      	orrs	r3, r2
 8001310:	613b      	str	r3, [r7, #16]
        GPIOx->AFR[position >> 3u] = temp;
 8001312:	697b      	ldr	r3, [r7, #20]
 8001314:	08da      	lsrs	r2, r3, #3
 8001316:	687b      	ldr	r3, [r7, #4]
 8001318:	3208      	adds	r2, #8
 800131a:	6939      	ldr	r1, [r7, #16]
 800131c:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 8001320:	687b      	ldr	r3, [r7, #4]
 8001322:	681b      	ldr	r3, [r3, #0]
 8001324:	613b      	str	r3, [r7, #16]
      temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
 8001326:	697b      	ldr	r3, [r7, #20]
 8001328:	005b      	lsls	r3, r3, #1
 800132a:	2203      	movs	r2, #3
 800132c:	fa02 f303 	lsl.w	r3, r2, r3
 8001330:	43db      	mvns	r3, r3
 8001332:	693a      	ldr	r2, [r7, #16]
 8001334:	4013      	ands	r3, r2
 8001336:	613b      	str	r3, [r7, #16]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
 8001338:	683b      	ldr	r3, [r7, #0]
 800133a:	685b      	ldr	r3, [r3, #4]
 800133c:	f003 0203 	and.w	r2, r3, #3
 8001340:	697b      	ldr	r3, [r7, #20]
 8001342:	005b      	lsls	r3, r3, #1
 8001344:	fa02 f303 	lsl.w	r3, r2, r3
 8001348:	693a      	ldr	r2, [r7, #16]
 800134a:	4313      	orrs	r3, r2
 800134c:	613b      	str	r3, [r7, #16]
      GPIOx->MODER = temp;
 800134e:	687b      	ldr	r3, [r7, #4]
 8001350:	693a      	ldr	r2, [r7, #16]
 8001352:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
 8001354:	683b      	ldr	r3, [r7, #0]
 8001356:	685b      	ldr	r3, [r3, #4]
 8001358:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 800135c:	2b00      	cmp	r3, #0
 800135e:	f000 80ac 	beq.w	80014ba <HAL_GPIO_Init+0x30a>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 8001362:	4b5f      	ldr	r3, [pc, #380]	; (80014e0 <HAL_GPIO_Init+0x330>)
 8001364:	6e1b      	ldr	r3, [r3, #96]	; 0x60
 8001366:	4a5e      	ldr	r2, [pc, #376]	; (80014e0 <HAL_GPIO_Init+0x330>)
 8001368:	f043 0301 	orr.w	r3, r3, #1
 800136c:	6613      	str	r3, [r2, #96]	; 0x60
 800136e:	4b5c      	ldr	r3, [pc, #368]	; (80014e0 <HAL_GPIO_Init+0x330>)
 8001370:	6e1b      	ldr	r3, [r3, #96]	; 0x60
 8001372:	f003 0301 	and.w	r3, r3, #1
 8001376:	60bb      	str	r3, [r7, #8]
 8001378:	68bb      	ldr	r3, [r7, #8]

        temp = SYSCFG->EXTICR[position >> 2u];
 800137a:	4a5a      	ldr	r2, [pc, #360]	; (80014e4 <HAL_GPIO_Init+0x334>)
 800137c:	697b      	ldr	r3, [r7, #20]
 800137e:	089b      	lsrs	r3, r3, #2
 8001380:	3302      	adds	r3, #2
 8001382:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8001386:	613b      	str	r3, [r7, #16]
        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
 8001388:	697b      	ldr	r3, [r7, #20]
 800138a:	f003 0303 	and.w	r3, r3, #3
 800138e:	009b      	lsls	r3, r3, #2
 8001390:	220f      	movs	r2, #15
 8001392:	fa02 f303 	lsl.w	r3, r2, r3
 8001396:	43db      	mvns	r3, r3
 8001398:	693a      	ldr	r2, [r7, #16]
 800139a:	4013      	ands	r3, r2
 800139c:	613b      	str	r3, [r7, #16]
        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
 800139e:	687b      	ldr	r3, [r7, #4]
 80013a0:	f1b3 4f90 	cmp.w	r3, #1207959552	; 0x48000000
 80013a4:	d025      	beq.n	80013f2 <HAL_GPIO_Init+0x242>
 80013a6:	687b      	ldr	r3, [r7, #4]
 80013a8:	4a4f      	ldr	r2, [pc, #316]	; (80014e8 <HAL_GPIO_Init+0x338>)
 80013aa:	4293      	cmp	r3, r2
 80013ac:	d01f      	beq.n	80013ee <HAL_GPIO_Init+0x23e>
 80013ae:	687b      	ldr	r3, [r7, #4]
 80013b0:	4a4e      	ldr	r2, [pc, #312]	; (80014ec <HAL_GPIO_Init+0x33c>)
 80013b2:	4293      	cmp	r3, r2
 80013b4:	d019      	beq.n	80013ea <HAL_GPIO_Init+0x23a>
 80013b6:	687b      	ldr	r3, [r7, #4]
 80013b8:	4a4d      	ldr	r2, [pc, #308]	; (80014f0 <HAL_GPIO_Init+0x340>)
 80013ba:	4293      	cmp	r3, r2
 80013bc:	d013      	beq.n	80013e6 <HAL_GPIO_Init+0x236>
 80013be:	687b      	ldr	r3, [r7, #4]
 80013c0:	4a4c      	ldr	r2, [pc, #304]	; (80014f4 <HAL_GPIO_Init+0x344>)
 80013c2:	4293      	cmp	r3, r2
 80013c4:	d00d      	beq.n	80013e2 <HAL_GPIO_Init+0x232>
 80013c6:	687b      	ldr	r3, [r7, #4]
 80013c8:	4a4b      	ldr	r2, [pc, #300]	; (80014f8 <HAL_GPIO_Init+0x348>)
 80013ca:	4293      	cmp	r3, r2
 80013cc:	d007      	beq.n	80013de <HAL_GPIO_Init+0x22e>
 80013ce:	687b      	ldr	r3, [r7, #4]
 80013d0:	4a4a      	ldr	r2, [pc, #296]	; (80014fc <HAL_GPIO_Init+0x34c>)
 80013d2:	4293      	cmp	r3, r2
 80013d4:	d101      	bne.n	80013da <HAL_GPIO_Init+0x22a>
 80013d6:	2306      	movs	r3, #6
 80013d8:	e00c      	b.n	80013f4 <HAL_GPIO_Init+0x244>
 80013da:	2307      	movs	r3, #7
 80013dc:	e00a      	b.n	80013f4 <HAL_GPIO_Init+0x244>
 80013de:	2305      	movs	r3, #5
 80013e0:	e008      	b.n	80013f4 <HAL_GPIO_Init+0x244>
 80013e2:	2304      	movs	r3, #4
 80013e4:	e006      	b.n	80013f4 <HAL_GPIO_Init+0x244>
 80013e6:	2303      	movs	r3, #3
 80013e8:	e004      	b.n	80013f4 <HAL_GPIO_Init+0x244>
 80013ea:	2302      	movs	r3, #2
 80013ec:	e002      	b.n	80013f4 <HAL_GPIO_Init+0x244>
 80013ee:	2301      	movs	r3, #1
 80013f0:	e000      	b.n	80013f4 <HAL_GPIO_Init+0x244>
 80013f2:	2300      	movs	r3, #0
 80013f4:	697a      	ldr	r2, [r7, #20]
 80013f6:	f002 0203 	and.w	r2, r2, #3
 80013fa:	0092      	lsls	r2, r2, #2
 80013fc:	4093      	lsls	r3, r2
 80013fe:	693a      	ldr	r2, [r7, #16]
 8001400:	4313      	orrs	r3, r2
 8001402:	613b      	str	r3, [r7, #16]
        SYSCFG->EXTICR[position >> 2u] = temp;
 8001404:	4937      	ldr	r1, [pc, #220]	; (80014e4 <HAL_GPIO_Init+0x334>)
 8001406:	697b      	ldr	r3, [r7, #20]
 8001408:	089b      	lsrs	r3, r3, #2
 800140a:	3302      	adds	r3, #2
 800140c:	693a      	ldr	r2, [r7, #16]
 800140e:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR1;
 8001412:	4b3b      	ldr	r3, [pc, #236]	; (8001500 <HAL_GPIO_Init+0x350>)
 8001414:	689b      	ldr	r3, [r3, #8]
 8001416:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001418:	68fb      	ldr	r3, [r7, #12]
 800141a:	43db      	mvns	r3, r3
 800141c:	693a      	ldr	r2, [r7, #16]
 800141e:	4013      	ands	r3, r2
 8001420:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
 8001422:	683b      	ldr	r3, [r7, #0]
 8001424:	685b      	ldr	r3, [r3, #4]
 8001426:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
 800142a:	2b00      	cmp	r3, #0
 800142c:	d003      	beq.n	8001436 <HAL_GPIO_Init+0x286>
        {
          temp |= iocurrent;
 800142e:	693a      	ldr	r2, [r7, #16]
 8001430:	68fb      	ldr	r3, [r7, #12]
 8001432:	4313      	orrs	r3, r2
 8001434:	613b      	str	r3, [r7, #16]
        }
        EXTI->RTSR1 = temp;
 8001436:	4a32      	ldr	r2, [pc, #200]	; (8001500 <HAL_GPIO_Init+0x350>)
 8001438:	693b      	ldr	r3, [r7, #16]
 800143a:	6093      	str	r3, [r2, #8]

        temp = EXTI->FTSR1;
 800143c:	4b30      	ldr	r3, [pc, #192]	; (8001500 <HAL_GPIO_Init+0x350>)
 800143e:	68db      	ldr	r3, [r3, #12]
 8001440:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001442:	68fb      	ldr	r3, [r7, #12]
 8001444:	43db      	mvns	r3, r3
 8001446:	693a      	ldr	r2, [r7, #16]
 8001448:	4013      	ands	r3, r2
 800144a:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
 800144c:	683b      	ldr	r3, [r7, #0]
 800144e:	685b      	ldr	r3, [r3, #4]
 8001450:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
 8001454:	2b00      	cmp	r3, #0
 8001456:	d003      	beq.n	8001460 <HAL_GPIO_Init+0x2b0>
        {
          temp |= iocurrent;
 8001458:	693a      	ldr	r2, [r7, #16]
 800145a:	68fb      	ldr	r3, [r7, #12]
 800145c:	4313      	orrs	r3, r2
 800145e:	613b      	str	r3, [r7, #16]
        }
        EXTI->FTSR1 = temp;
 8001460:	4a27      	ldr	r2, [pc, #156]	; (8001500 <HAL_GPIO_Init+0x350>)
 8001462:	693b      	ldr	r3, [r7, #16]
 8001464:	60d3      	str	r3, [r2, #12]

        /* Clear EXTI line configuration */
        temp = EXTI->EMR1;
 8001466:	4b26      	ldr	r3, [pc, #152]	; (8001500 <HAL_GPIO_Init+0x350>)
 8001468:	685b      	ldr	r3, [r3, #4]
 800146a:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 800146c:	68fb      	ldr	r3, [r7, #12]
 800146e:	43db      	mvns	r3, r3
 8001470:	693a      	ldr	r2, [r7, #16]
 8001472:	4013      	ands	r3, r2
 8001474:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
 8001476:	683b      	ldr	r3, [r7, #0]
 8001478:	685b      	ldr	r3, [r3, #4]
 800147a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 800147e:	2b00      	cmp	r3, #0
 8001480:	d003      	beq.n	800148a <HAL_GPIO_Init+0x2da>
        {
          temp |= iocurrent;
 8001482:	693a      	ldr	r2, [r7, #16]
 8001484:	68fb      	ldr	r3, [r7, #12]
 8001486:	4313      	orrs	r3, r2
 8001488:	613b      	str	r3, [r7, #16]
        }
        EXTI->EMR1 = temp;
 800148a:	4a1d      	ldr	r2, [pc, #116]	; (8001500 <HAL_GPIO_Init+0x350>)
 800148c:	693b      	ldr	r3, [r7, #16]
 800148e:	6053      	str	r3, [r2, #4]

        temp = EXTI->IMR1;
 8001490:	4b1b      	ldr	r3, [pc, #108]	; (8001500 <HAL_GPIO_Init+0x350>)
 8001492:	681b      	ldr	r3, [r3, #0]
 8001494:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8001496:	68fb      	ldr	r3, [r7, #12]
 8001498:	43db      	mvns	r3, r3
 800149a:	693a      	ldr	r2, [r7, #16]
 800149c:	4013      	ands	r3, r2
 800149e:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
 80014a0:	683b      	ldr	r3, [r7, #0]
 80014a2:	685b      	ldr	r3, [r3, #4]
 80014a4:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 80014a8:	2b00      	cmp	r3, #0
 80014aa:	d003      	beq.n	80014b4 <HAL_GPIO_Init+0x304>
        {
          temp |= iocurrent;
 80014ac:	693a      	ldr	r2, [r7, #16]
 80014ae:	68fb      	ldr	r3, [r7, #12]
 80014b0:	4313      	orrs	r3, r2
 80014b2:	613b      	str	r3, [r7, #16]
        }
        EXTI->IMR1 = temp;
 80014b4:	4a12      	ldr	r2, [pc, #72]	; (8001500 <HAL_GPIO_Init+0x350>)
 80014b6:	693b      	ldr	r3, [r7, #16]
 80014b8:	6013      	str	r3, [r2, #0]
      }
    }

    position++;
 80014ba:	697b      	ldr	r3, [r7, #20]
 80014bc:	3301      	adds	r3, #1
 80014be:	617b      	str	r3, [r7, #20]
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 80014c0:	683b      	ldr	r3, [r7, #0]
 80014c2:	681a      	ldr	r2, [r3, #0]
 80014c4:	697b      	ldr	r3, [r7, #20]
 80014c6:	fa22 f303 	lsr.w	r3, r2, r3
 80014ca:	2b00      	cmp	r3, #0
 80014cc:	f47f ae78 	bne.w	80011c0 <HAL_GPIO_Init+0x10>
  }
}
 80014d0:	bf00      	nop
 80014d2:	bf00      	nop
 80014d4:	371c      	adds	r7, #28
 80014d6:	46bd      	mov	sp, r7
 80014d8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80014dc:	4770      	bx	lr
 80014de:	bf00      	nop
 80014e0:	40021000 	.word	0x40021000
 80014e4:	40010000 	.word	0x40010000
 80014e8:	48000400 	.word	0x48000400
 80014ec:	48000800 	.word	0x48000800
 80014f0:	48000c00 	.word	0x48000c00
 80014f4:	48001000 	.word	0x48001000
 80014f8:	48001400 	.word	0x48001400
 80014fc:	48001800 	.word	0x48001800
 8001500:	40010400 	.word	0x40010400

08001504 <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 8001504:	b480      	push	{r7}
 8001506:	b083      	sub	sp, #12
 8001508:	af00      	add	r7, sp, #0
 800150a:	6078      	str	r0, [r7, #4]
 800150c:	460b      	mov	r3, r1
 800150e:	807b      	strh	r3, [r7, #2]
 8001510:	4613      	mov	r3, r2
 8001512:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if(PinState != GPIO_PIN_RESET)
 8001514:	787b      	ldrb	r3, [r7, #1]
 8001516:	2b00      	cmp	r3, #0
 8001518:	d003      	beq.n	8001522 <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin;
 800151a:	887a      	ldrh	r2, [r7, #2]
 800151c:	687b      	ldr	r3, [r7, #4]
 800151e:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BRR = (uint32_t)GPIO_Pin;
  }
}
 8001520:	e002      	b.n	8001528 <HAL_GPIO_WritePin+0x24>
    GPIOx->BRR = (uint32_t)GPIO_Pin;
 8001522:	887a      	ldrh	r2, [r7, #2]
 8001524:	687b      	ldr	r3, [r7, #4]
 8001526:	629a      	str	r2, [r3, #40]	; 0x28
}
 8001528:	bf00      	nop
 800152a:	370c      	adds	r7, #12
 800152c:	46bd      	mov	sp, r7
 800152e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001532:	4770      	bx	lr

08001534 <HAL_GPIO_TogglePin>:
  * @param  GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
  * @param  GPIO_Pin specifies the pin to be toggled.
  * @retval None
  */
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
 8001534:	b480      	push	{r7}
 8001536:	b085      	sub	sp, #20
 8001538:	af00      	add	r7, sp, #0
 800153a:	6078      	str	r0, [r7, #4]
 800153c:	460b      	mov	r3, r1
 800153e:	807b      	strh	r3, [r7, #2]

  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  /* get current Output Data Register value */
  odr = GPIOx->ODR;
 8001540:	687b      	ldr	r3, [r7, #4]
 8001542:	695b      	ldr	r3, [r3, #20]
 8001544:	60fb      	str	r3, [r7, #12]

  /* Set selected pins that were at low level, and reset ones that were high */
  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
 8001546:	887a      	ldrh	r2, [r7, #2]
 8001548:	68fb      	ldr	r3, [r7, #12]
 800154a:	4013      	ands	r3, r2
 800154c:	041a      	lsls	r2, r3, #16
 800154e:	68fb      	ldr	r3, [r7, #12]
 8001550:	43d9      	mvns	r1, r3
 8001552:	887b      	ldrh	r3, [r7, #2]
 8001554:	400b      	ands	r3, r1
 8001556:	431a      	orrs	r2, r3
 8001558:	687b      	ldr	r3, [r7, #4]
 800155a:	619a      	str	r2, [r3, #24]
}
 800155c:	bf00      	nop
 800155e:	3714      	adds	r7, #20
 8001560:	46bd      	mov	sp, r7
 8001562:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001566:	4770      	bx	lr

08001568 <HAL_PWR_EnableBkUpAccess>:
  * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
  *        back-up domain.
  * @retval None
  */
void HAL_PWR_EnableBkUpAccess(void)
{
 8001568:	b480      	push	{r7}
 800156a:	af00      	add	r7, sp, #0
  SET_BIT(PWR->CR1, PWR_CR1_DBP);
 800156c:	4b05      	ldr	r3, [pc, #20]	; (8001584 <HAL_PWR_EnableBkUpAccess+0x1c>)
 800156e:	681b      	ldr	r3, [r3, #0]
 8001570:	4a04      	ldr	r2, [pc, #16]	; (8001584 <HAL_PWR_EnableBkUpAccess+0x1c>)
 8001572:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8001576:	6013      	str	r3, [r2, #0]
}
 8001578:	bf00      	nop
 800157a:	46bd      	mov	sp, r7
 800157c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001580:	4770      	bx	lr
 8001582:	bf00      	nop
 8001584:	40007000 	.word	0x40007000

08001588 <HAL_PWREx_GetVoltageRange>:
  * @brief Return Voltage Scaling Range.
  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
  *         or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
  */
uint32_t HAL_PWREx_GetVoltageRange(void)
{
 8001588:	b480      	push	{r7}
 800158a:	af00      	add	r7, sp, #0
    else
    {
      return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
    }
#else
  return  (PWR->CR1 & PWR_CR1_VOS);
 800158c:	4b04      	ldr	r3, [pc, #16]	; (80015a0 <HAL_PWREx_GetVoltageRange+0x18>)
 800158e:	681b      	ldr	r3, [r3, #0]
 8001590:	f403 63c0 	and.w	r3, r3, #1536	; 0x600
#endif
}
 8001594:	4618      	mov	r0, r3
 8001596:	46bd      	mov	sp, r7
 8001598:	f85d 7b04 	ldr.w	r7, [sp], #4
 800159c:	4770      	bx	lr
 800159e:	bf00      	nop
 80015a0:	40007000 	.word	0x40007000

080015a4 <HAL_PWREx_ControlVoltageScaling>:
  *        cleared before returning the status. If the flag is not cleared within
  *        50 microseconds, HAL_TIMEOUT status is reported.
  * @retval HAL Status
  */
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
 80015a4:	b480      	push	{r7}
 80015a6:	b085      	sub	sp, #20
 80015a8:	af00      	add	r7, sp, #0
 80015aa:	6078      	str	r0, [r7, #4]
  }

#else

  /* If Set Range 1 */
  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
 80015ac:	687b      	ldr	r3, [r7, #4]
 80015ae:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 80015b2:	d130      	bne.n	8001616 <HAL_PWREx_ControlVoltageScaling+0x72>
  {
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
 80015b4:	4b23      	ldr	r3, [pc, #140]	; (8001644 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80015b6:	681b      	ldr	r3, [r3, #0]
 80015b8:	f403 63c0 	and.w	r3, r3, #1536	; 0x600
 80015bc:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 80015c0:	d038      	beq.n	8001634 <HAL_PWREx_ControlVoltageScaling+0x90>
    {
      /* Set Range 1 */
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
 80015c2:	4b20      	ldr	r3, [pc, #128]	; (8001644 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80015c4:	681b      	ldr	r3, [r3, #0]
 80015c6:	f423 63c0 	bic.w	r3, r3, #1536	; 0x600
 80015ca:	4a1e      	ldr	r2, [pc, #120]	; (8001644 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80015cc:	f443 7300 	orr.w	r3, r3, #512	; 0x200
 80015d0:	6013      	str	r3, [r2, #0]

      /* Wait until VOSF is cleared */
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 80015d2:	4b1d      	ldr	r3, [pc, #116]	; (8001648 <HAL_PWREx_ControlVoltageScaling+0xa4>)
 80015d4:	681b      	ldr	r3, [r3, #0]
 80015d6:	2232      	movs	r2, #50	; 0x32
 80015d8:	fb02 f303 	mul.w	r3, r2, r3
 80015dc:	4a1b      	ldr	r2, [pc, #108]	; (800164c <HAL_PWREx_ControlVoltageScaling+0xa8>)
 80015de:	fba2 2303 	umull	r2, r3, r2, r3
 80015e2:	0c9b      	lsrs	r3, r3, #18
 80015e4:	3301      	adds	r3, #1
 80015e6:	60fb      	str	r3, [r7, #12]
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 80015e8:	e002      	b.n	80015f0 <HAL_PWREx_ControlVoltageScaling+0x4c>
      {
        wait_loop_index--;
 80015ea:	68fb      	ldr	r3, [r7, #12]
 80015ec:	3b01      	subs	r3, #1
 80015ee:	60fb      	str	r3, [r7, #12]
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 80015f0:	4b14      	ldr	r3, [pc, #80]	; (8001644 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 80015f2:	695b      	ldr	r3, [r3, #20]
 80015f4:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 80015f8:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 80015fc:	d102      	bne.n	8001604 <HAL_PWREx_ControlVoltageScaling+0x60>
 80015fe:	68fb      	ldr	r3, [r7, #12]
 8001600:	2b00      	cmp	r3, #0
 8001602:	d1f2      	bne.n	80015ea <HAL_PWREx_ControlVoltageScaling+0x46>
      }
      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
 8001604:	4b0f      	ldr	r3, [pc, #60]	; (8001644 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8001606:	695b      	ldr	r3, [r3, #20]
 8001608:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 800160c:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 8001610:	d110      	bne.n	8001634 <HAL_PWREx_ControlVoltageScaling+0x90>
      {
        return HAL_TIMEOUT;
 8001612:	2303      	movs	r3, #3
 8001614:	e00f      	b.n	8001636 <HAL_PWREx_ControlVoltageScaling+0x92>
      }
    }
  }
  else
  {
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
 8001616:	4b0b      	ldr	r3, [pc, #44]	; (8001644 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8001618:	681b      	ldr	r3, [r3, #0]
 800161a:	f403 63c0 	and.w	r3, r3, #1536	; 0x600
 800161e:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 8001622:	d007      	beq.n	8001634 <HAL_PWREx_ControlVoltageScaling+0x90>
    {
      /* Set Range 2 */
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
 8001624:	4b07      	ldr	r3, [pc, #28]	; (8001644 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8001626:	681b      	ldr	r3, [r3, #0]
 8001628:	f423 63c0 	bic.w	r3, r3, #1536	; 0x600
 800162c:	4a05      	ldr	r2, [pc, #20]	; (8001644 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 800162e:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
 8001632:	6013      	str	r3, [r2, #0]
      /* No need to wait for VOSF to be cleared for this transition */
    }
  }
#endif

  return HAL_OK;
 8001634:	2300      	movs	r3, #0
}
 8001636:	4618      	mov	r0, r3
 8001638:	3714      	adds	r7, #20
 800163a:	46bd      	mov	sp, r7
 800163c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001640:	4770      	bx	lr
 8001642:	bf00      	nop
 8001644:	40007000 	.word	0x40007000
 8001648:	20000000 	.word	0x20000000
 800164c:	431bde83 	.word	0x431bde83

08001650 <HAL_RCC_OscConfig>:
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8001650:	b580      	push	{r7, lr}
 8001652:	b088      	sub	sp, #32
 8001654:	af00      	add	r7, sp, #0
 8001656:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  HAL_StatusTypeDef status;
  uint32_t sysclk_source, pll_config;

  /* Check Null pointer */
  if(RCC_OscInitStruct == NULL)
 8001658:	687b      	ldr	r3, [r7, #4]
 800165a:	2b00      	cmp	r3, #0
 800165c:	d101      	bne.n	8001662 <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 800165e:	2301      	movs	r3, #1
 8001660:	e3ca      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 8001662:	4b97      	ldr	r3, [pc, #604]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001664:	689b      	ldr	r3, [r3, #8]
 8001666:	f003 030c 	and.w	r3, r3, #12
 800166a:	61bb      	str	r3, [r7, #24]
  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
 800166c:	4b94      	ldr	r3, [pc, #592]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 800166e:	68db      	ldr	r3, [r3, #12]
 8001670:	f003 0303 	and.w	r3, r3, #3
 8001674:	617b      	str	r3, [r7, #20]

  /*----------------------------- MSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
 8001676:	687b      	ldr	r3, [r7, #4]
 8001678:	681b      	ldr	r3, [r3, #0]
 800167a:	f003 0310 	and.w	r3, r3, #16
 800167e:	2b00      	cmp	r3, #0
 8001680:	f000 80e4 	beq.w	800184c <HAL_RCC_OscConfig+0x1fc>
    assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
    assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
    assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

    /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_CFGR_SWS_MSI) ||
 8001684:	69bb      	ldr	r3, [r7, #24]
 8001686:	2b00      	cmp	r3, #0
 8001688:	d007      	beq.n	800169a <HAL_RCC_OscConfig+0x4a>
 800168a:	69bb      	ldr	r3, [r7, #24]
 800168c:	2b0c      	cmp	r3, #12
 800168e:	f040 808b 	bne.w	80017a8 <HAL_RCC_OscConfig+0x158>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
 8001692:	697b      	ldr	r3, [r7, #20]
 8001694:	2b01      	cmp	r3, #1
 8001696:	f040 8087 	bne.w	80017a8 <HAL_RCC_OscConfig+0x158>
    {
      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 800169a:	4b89      	ldr	r3, [pc, #548]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 800169c:	681b      	ldr	r3, [r3, #0]
 800169e:	f003 0302 	and.w	r3, r3, #2
 80016a2:	2b00      	cmp	r3, #0
 80016a4:	d005      	beq.n	80016b2 <HAL_RCC_OscConfig+0x62>
 80016a6:	687b      	ldr	r3, [r7, #4]
 80016a8:	699b      	ldr	r3, [r3, #24]
 80016aa:	2b00      	cmp	r3, #0
 80016ac:	d101      	bne.n	80016b2 <HAL_RCC_OscConfig+0x62>
      {
        return HAL_ERROR;
 80016ae:	2301      	movs	r3, #1
 80016b0:	e3a2      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      else
      {
        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
           must be correctly programmed according to the frequency of the CPU clock
           (HCLK) and the supply voltage of the device. */
        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
 80016b2:	687b      	ldr	r3, [r7, #4]
 80016b4:	6a1a      	ldr	r2, [r3, #32]
 80016b6:	4b82      	ldr	r3, [pc, #520]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80016b8:	681b      	ldr	r3, [r3, #0]
 80016ba:	f003 0308 	and.w	r3, r3, #8
 80016be:	2b00      	cmp	r3, #0
 80016c0:	d004      	beq.n	80016cc <HAL_RCC_OscConfig+0x7c>
 80016c2:	4b7f      	ldr	r3, [pc, #508]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80016c4:	681b      	ldr	r3, [r3, #0]
 80016c6:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 80016ca:	e005      	b.n	80016d8 <HAL_RCC_OscConfig+0x88>
 80016cc:	4b7c      	ldr	r3, [pc, #496]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80016ce:	f8d3 3094 	ldr.w	r3, [r3, #148]	; 0x94
 80016d2:	091b      	lsrs	r3, r3, #4
 80016d4:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 80016d8:	4293      	cmp	r3, r2
 80016da:	d223      	bcs.n	8001724 <HAL_RCC_OscConfig+0xd4>
        {
          /* First increase number of wait states update if necessary */
          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 80016dc:	687b      	ldr	r3, [r7, #4]
 80016de:	6a1b      	ldr	r3, [r3, #32]
 80016e0:	4618      	mov	r0, r3
 80016e2:	f000 fd87 	bl	80021f4 <RCC_SetFlashLatencyFromMSIRange>
 80016e6:	4603      	mov	r3, r0
 80016e8:	2b00      	cmp	r3, #0
 80016ea:	d001      	beq.n	80016f0 <HAL_RCC_OscConfig+0xa0>
          {
            return HAL_ERROR;
 80016ec:	2301      	movs	r3, #1
 80016ee:	e383      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
          }

          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 80016f0:	4b73      	ldr	r3, [pc, #460]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80016f2:	681b      	ldr	r3, [r3, #0]
 80016f4:	4a72      	ldr	r2, [pc, #456]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80016f6:	f043 0308 	orr.w	r3, r3, #8
 80016fa:	6013      	str	r3, [r2, #0]
 80016fc:	4b70      	ldr	r3, [pc, #448]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80016fe:	681b      	ldr	r3, [r3, #0]
 8001700:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8001704:	687b      	ldr	r3, [r7, #4]
 8001706:	6a1b      	ldr	r3, [r3, #32]
 8001708:	496d      	ldr	r1, [pc, #436]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 800170a:	4313      	orrs	r3, r2
 800170c:	600b      	str	r3, [r1, #0]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 800170e:	4b6c      	ldr	r3, [pc, #432]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001710:	685b      	ldr	r3, [r3, #4]
 8001712:	f423 427f 	bic.w	r2, r3, #65280	; 0xff00
 8001716:	687b      	ldr	r3, [r7, #4]
 8001718:	69db      	ldr	r3, [r3, #28]
 800171a:	021b      	lsls	r3, r3, #8
 800171c:	4968      	ldr	r1, [pc, #416]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 800171e:	4313      	orrs	r3, r2
 8001720:	604b      	str	r3, [r1, #4]
 8001722:	e025      	b.n	8001770 <HAL_RCC_OscConfig+0x120>
        }
        else
        {
          /* Else, keep current flash latency while decreasing applies */
          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8001724:	4b66      	ldr	r3, [pc, #408]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001726:	681b      	ldr	r3, [r3, #0]
 8001728:	4a65      	ldr	r2, [pc, #404]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 800172a:	f043 0308 	orr.w	r3, r3, #8
 800172e:	6013      	str	r3, [r2, #0]
 8001730:	4b63      	ldr	r3, [pc, #396]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001732:	681b      	ldr	r3, [r3, #0]
 8001734:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8001738:	687b      	ldr	r3, [r7, #4]
 800173a:	6a1b      	ldr	r3, [r3, #32]
 800173c:	4960      	ldr	r1, [pc, #384]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 800173e:	4313      	orrs	r3, r2
 8001740:	600b      	str	r3, [r1, #0]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8001742:	4b5f      	ldr	r3, [pc, #380]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001744:	685b      	ldr	r3, [r3, #4]
 8001746:	f423 427f 	bic.w	r2, r3, #65280	; 0xff00
 800174a:	687b      	ldr	r3, [r7, #4]
 800174c:	69db      	ldr	r3, [r3, #28]
 800174e:	021b      	lsls	r3, r3, #8
 8001750:	495b      	ldr	r1, [pc, #364]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001752:	4313      	orrs	r3, r2
 8001754:	604b      	str	r3, [r1, #4]

          /* Decrease number of wait states update if necessary */
          /* Only possible when MSI is the System clock source  */
          if(sysclk_source == RCC_CFGR_SWS_MSI)
 8001756:	69bb      	ldr	r3, [r7, #24]
 8001758:	2b00      	cmp	r3, #0
 800175a:	d109      	bne.n	8001770 <HAL_RCC_OscConfig+0x120>
          {
            if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 800175c:	687b      	ldr	r3, [r7, #4]
 800175e:	6a1b      	ldr	r3, [r3, #32]
 8001760:	4618      	mov	r0, r3
 8001762:	f000 fd47 	bl	80021f4 <RCC_SetFlashLatencyFromMSIRange>
 8001766:	4603      	mov	r3, r0
 8001768:	2b00      	cmp	r3, #0
 800176a:	d001      	beq.n	8001770 <HAL_RCC_OscConfig+0x120>
            {
              return HAL_ERROR;
 800176c:	2301      	movs	r3, #1
 800176e:	e343      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
            }
          }
        }

        /* Update the SystemCoreClock global variable */
        SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
 8001770:	f000 fc4a 	bl	8002008 <HAL_RCC_GetSysClockFreq>
 8001774:	4602      	mov	r2, r0
 8001776:	4b52      	ldr	r3, [pc, #328]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001778:	689b      	ldr	r3, [r3, #8]
 800177a:	091b      	lsrs	r3, r3, #4
 800177c:	f003 030f 	and.w	r3, r3, #15
 8001780:	4950      	ldr	r1, [pc, #320]	; (80018c4 <HAL_RCC_OscConfig+0x274>)
 8001782:	5ccb      	ldrb	r3, [r1, r3]
 8001784:	f003 031f 	and.w	r3, r3, #31
 8001788:	fa22 f303 	lsr.w	r3, r2, r3
 800178c:	4a4e      	ldr	r2, [pc, #312]	; (80018c8 <HAL_RCC_OscConfig+0x278>)
 800178e:	6013      	str	r3, [r2, #0]

        /* Configure the source of time base considering new system clocks settings*/
        status = HAL_InitTick(uwTickPrio);
 8001790:	4b4e      	ldr	r3, [pc, #312]	; (80018cc <HAL_RCC_OscConfig+0x27c>)
 8001792:	681b      	ldr	r3, [r3, #0]
 8001794:	4618      	mov	r0, r3
 8001796:	f7ff f8d1 	bl	800093c <HAL_InitTick>
 800179a:	4603      	mov	r3, r0
 800179c:	73fb      	strb	r3, [r7, #15]
        if(status != HAL_OK)
 800179e:	7bfb      	ldrb	r3, [r7, #15]
 80017a0:	2b00      	cmp	r3, #0
 80017a2:	d052      	beq.n	800184a <HAL_RCC_OscConfig+0x1fa>
        {
          return status;
 80017a4:	7bfb      	ldrb	r3, [r7, #15]
 80017a6:	e327      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      }
    }
    else
    {
      /* Check the MSI State */
      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
 80017a8:	687b      	ldr	r3, [r7, #4]
 80017aa:	699b      	ldr	r3, [r3, #24]
 80017ac:	2b00      	cmp	r3, #0
 80017ae:	d032      	beq.n	8001816 <HAL_RCC_OscConfig+0x1c6>
      {
        /* Enable the Internal High Speed oscillator (MSI). */
        __HAL_RCC_MSI_ENABLE();
 80017b0:	4b43      	ldr	r3, [pc, #268]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80017b2:	681b      	ldr	r3, [r3, #0]
 80017b4:	4a42      	ldr	r2, [pc, #264]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80017b6:	f043 0301 	orr.w	r3, r3, #1
 80017ba:	6013      	str	r3, [r2, #0]

        /* Get timeout */
        tickstart = HAL_GetTick();
 80017bc:	f7ff faa2 	bl	8000d04 <HAL_GetTick>
 80017c0:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 80017c2:	e008      	b.n	80017d6 <HAL_RCC_OscConfig+0x186>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 80017c4:	f7ff fa9e 	bl	8000d04 <HAL_GetTick>
 80017c8:	4602      	mov	r2, r0
 80017ca:	693b      	ldr	r3, [r7, #16]
 80017cc:	1ad3      	subs	r3, r2, r3
 80017ce:	2b02      	cmp	r3, #2
 80017d0:	d901      	bls.n	80017d6 <HAL_RCC_OscConfig+0x186>
          {
            return HAL_TIMEOUT;
 80017d2:	2303      	movs	r3, #3
 80017d4:	e310      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 80017d6:	4b3a      	ldr	r3, [pc, #232]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80017d8:	681b      	ldr	r3, [r3, #0]
 80017da:	f003 0302 	and.w	r3, r3, #2
 80017de:	2b00      	cmp	r3, #0
 80017e0:	d0f0      	beq.n	80017c4 <HAL_RCC_OscConfig+0x174>
          }
        }
         /* Selects the Multiple Speed oscillator (MSI) clock range .*/
        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 80017e2:	4b37      	ldr	r3, [pc, #220]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80017e4:	681b      	ldr	r3, [r3, #0]
 80017e6:	4a36      	ldr	r2, [pc, #216]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80017e8:	f043 0308 	orr.w	r3, r3, #8
 80017ec:	6013      	str	r3, [r2, #0]
 80017ee:	4b34      	ldr	r3, [pc, #208]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80017f0:	681b      	ldr	r3, [r3, #0]
 80017f2:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 80017f6:	687b      	ldr	r3, [r7, #4]
 80017f8:	6a1b      	ldr	r3, [r3, #32]
 80017fa:	4931      	ldr	r1, [pc, #196]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80017fc:	4313      	orrs	r3, r2
 80017fe:	600b      	str	r3, [r1, #0]
         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8001800:	4b2f      	ldr	r3, [pc, #188]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001802:	685b      	ldr	r3, [r3, #4]
 8001804:	f423 427f 	bic.w	r2, r3, #65280	; 0xff00
 8001808:	687b      	ldr	r3, [r7, #4]
 800180a:	69db      	ldr	r3, [r3, #28]
 800180c:	021b      	lsls	r3, r3, #8
 800180e:	492c      	ldr	r1, [pc, #176]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001810:	4313      	orrs	r3, r2
 8001812:	604b      	str	r3, [r1, #4]
 8001814:	e01a      	b.n	800184c <HAL_RCC_OscConfig+0x1fc>

      }
      else
      {
        /* Disable the Internal High Speed oscillator (MSI). */
        __HAL_RCC_MSI_DISABLE();
 8001816:	4b2a      	ldr	r3, [pc, #168]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001818:	681b      	ldr	r3, [r3, #0]
 800181a:	4a29      	ldr	r2, [pc, #164]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 800181c:	f023 0301 	bic.w	r3, r3, #1
 8001820:	6013      	str	r3, [r2, #0]

        /* Get timeout */
        tickstart = HAL_GetTick();
 8001822:	f7ff fa6f 	bl	8000d04 <HAL_GetTick>
 8001826:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
 8001828:	e008      	b.n	800183c <HAL_RCC_OscConfig+0x1ec>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 800182a:	f7ff fa6b 	bl	8000d04 <HAL_GetTick>
 800182e:	4602      	mov	r2, r0
 8001830:	693b      	ldr	r3, [r7, #16]
 8001832:	1ad3      	subs	r3, r2, r3
 8001834:	2b02      	cmp	r3, #2
 8001836:	d901      	bls.n	800183c <HAL_RCC_OscConfig+0x1ec>
          {
            return HAL_TIMEOUT;
 8001838:	2303      	movs	r3, #3
 800183a:	e2dd      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
 800183c:	4b20      	ldr	r3, [pc, #128]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 800183e:	681b      	ldr	r3, [r3, #0]
 8001840:	f003 0302 	and.w	r3, r3, #2
 8001844:	2b00      	cmp	r3, #0
 8001846:	d1f0      	bne.n	800182a <HAL_RCC_OscConfig+0x1da>
 8001848:	e000      	b.n	800184c <HAL_RCC_OscConfig+0x1fc>
      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 800184a:	bf00      	nop
        }
      }
    }
  }
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 800184c:	687b      	ldr	r3, [r7, #4]
 800184e:	681b      	ldr	r3, [r3, #0]
 8001850:	f003 0301 	and.w	r3, r3, #1
 8001854:	2b00      	cmp	r3, #0
 8001856:	d074      	beq.n	8001942 <HAL_RCC_OscConfig+0x2f2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if((sysclk_source == RCC_CFGR_SWS_HSE) ||
 8001858:	69bb      	ldr	r3, [r7, #24]
 800185a:	2b08      	cmp	r3, #8
 800185c:	d005      	beq.n	800186a <HAL_RCC_OscConfig+0x21a>
 800185e:	69bb      	ldr	r3, [r7, #24]
 8001860:	2b0c      	cmp	r3, #12
 8001862:	d10e      	bne.n	8001882 <HAL_RCC_OscConfig+0x232>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
 8001864:	697b      	ldr	r3, [r7, #20]
 8001866:	2b03      	cmp	r3, #3
 8001868:	d10b      	bne.n	8001882 <HAL_RCC_OscConfig+0x232>
    {
      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 800186a:	4b15      	ldr	r3, [pc, #84]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 800186c:	681b      	ldr	r3, [r3, #0]
 800186e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001872:	2b00      	cmp	r3, #0
 8001874:	d064      	beq.n	8001940 <HAL_RCC_OscConfig+0x2f0>
 8001876:	687b      	ldr	r3, [r7, #4]
 8001878:	685b      	ldr	r3, [r3, #4]
 800187a:	2b00      	cmp	r3, #0
 800187c:	d160      	bne.n	8001940 <HAL_RCC_OscConfig+0x2f0>
      {
        return HAL_ERROR;
 800187e:	2301      	movs	r3, #1
 8001880:	e2ba      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8001882:	687b      	ldr	r3, [r7, #4]
 8001884:	685b      	ldr	r3, [r3, #4]
 8001886:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 800188a:	d106      	bne.n	800189a <HAL_RCC_OscConfig+0x24a>
 800188c:	4b0c      	ldr	r3, [pc, #48]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 800188e:	681b      	ldr	r3, [r3, #0]
 8001890:	4a0b      	ldr	r2, [pc, #44]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 8001892:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8001896:	6013      	str	r3, [r2, #0]
 8001898:	e026      	b.n	80018e8 <HAL_RCC_OscConfig+0x298>
 800189a:	687b      	ldr	r3, [r7, #4]
 800189c:	685b      	ldr	r3, [r3, #4]
 800189e:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 80018a2:	d115      	bne.n	80018d0 <HAL_RCC_OscConfig+0x280>
 80018a4:	4b06      	ldr	r3, [pc, #24]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80018a6:	681b      	ldr	r3, [r3, #0]
 80018a8:	4a05      	ldr	r2, [pc, #20]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80018aa:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 80018ae:	6013      	str	r3, [r2, #0]
 80018b0:	4b03      	ldr	r3, [pc, #12]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80018b2:	681b      	ldr	r3, [r3, #0]
 80018b4:	4a02      	ldr	r2, [pc, #8]	; (80018c0 <HAL_RCC_OscConfig+0x270>)
 80018b6:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 80018ba:	6013      	str	r3, [r2, #0]
 80018bc:	e014      	b.n	80018e8 <HAL_RCC_OscConfig+0x298>
 80018be:	bf00      	nop
 80018c0:	40021000 	.word	0x40021000
 80018c4:	08006cd8 	.word	0x08006cd8
 80018c8:	20000000 	.word	0x20000000
 80018cc:	20000004 	.word	0x20000004
 80018d0:	4ba0      	ldr	r3, [pc, #640]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 80018d2:	681b      	ldr	r3, [r3, #0]
 80018d4:	4a9f      	ldr	r2, [pc, #636]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 80018d6:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 80018da:	6013      	str	r3, [r2, #0]
 80018dc:	4b9d      	ldr	r3, [pc, #628]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 80018de:	681b      	ldr	r3, [r3, #0]
 80018e0:	4a9c      	ldr	r2, [pc, #624]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 80018e2:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 80018e6:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 80018e8:	687b      	ldr	r3, [r7, #4]
 80018ea:	685b      	ldr	r3, [r3, #4]
 80018ec:	2b00      	cmp	r3, #0
 80018ee:	d013      	beq.n	8001918 <HAL_RCC_OscConfig+0x2c8>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80018f0:	f7ff fa08 	bl	8000d04 <HAL_GetTick>
 80018f4:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 80018f6:	e008      	b.n	800190a <HAL_RCC_OscConfig+0x2ba>
        {
          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 80018f8:	f7ff fa04 	bl	8000d04 <HAL_GetTick>
 80018fc:	4602      	mov	r2, r0
 80018fe:	693b      	ldr	r3, [r7, #16]
 8001900:	1ad3      	subs	r3, r2, r3
 8001902:	2b64      	cmp	r3, #100	; 0x64
 8001904:	d901      	bls.n	800190a <HAL_RCC_OscConfig+0x2ba>
          {
            return HAL_TIMEOUT;
 8001906:	2303      	movs	r3, #3
 8001908:	e276      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 800190a:	4b92      	ldr	r3, [pc, #584]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 800190c:	681b      	ldr	r3, [r3, #0]
 800190e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001912:	2b00      	cmp	r3, #0
 8001914:	d0f0      	beq.n	80018f8 <HAL_RCC_OscConfig+0x2a8>
 8001916:	e014      	b.n	8001942 <HAL_RCC_OscConfig+0x2f2>
        }
      }
      else
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001918:	f7ff f9f4 	bl	8000d04 <HAL_GetTick>
 800191c:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 800191e:	e008      	b.n	8001932 <HAL_RCC_OscConfig+0x2e2>
        {
          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8001920:	f7ff f9f0 	bl	8000d04 <HAL_GetTick>
 8001924:	4602      	mov	r2, r0
 8001926:	693b      	ldr	r3, [r7, #16]
 8001928:	1ad3      	subs	r3, r2, r3
 800192a:	2b64      	cmp	r3, #100	; 0x64
 800192c:	d901      	bls.n	8001932 <HAL_RCC_OscConfig+0x2e2>
          {
            return HAL_TIMEOUT;
 800192e:	2303      	movs	r3, #3
 8001930:	e262      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 8001932:	4b88      	ldr	r3, [pc, #544]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001934:	681b      	ldr	r3, [r3, #0]
 8001936:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 800193a:	2b00      	cmp	r3, #0
 800193c:	d1f0      	bne.n	8001920 <HAL_RCC_OscConfig+0x2d0>
 800193e:	e000      	b.n	8001942 <HAL_RCC_OscConfig+0x2f2>
      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8001940:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8001942:	687b      	ldr	r3, [r7, #4]
 8001944:	681b      	ldr	r3, [r3, #0]
 8001946:	f003 0302 	and.w	r3, r3, #2
 800194a:	2b00      	cmp	r3, #0
 800194c:	d060      	beq.n	8001a10 <HAL_RCC_OscConfig+0x3c0>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_CFGR_SWS_HSI) ||
 800194e:	69bb      	ldr	r3, [r7, #24]
 8001950:	2b04      	cmp	r3, #4
 8001952:	d005      	beq.n	8001960 <HAL_RCC_OscConfig+0x310>
 8001954:	69bb      	ldr	r3, [r7, #24]
 8001956:	2b0c      	cmp	r3, #12
 8001958:	d119      	bne.n	800198e <HAL_RCC_OscConfig+0x33e>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
 800195a:	697b      	ldr	r3, [r7, #20]
 800195c:	2b02      	cmp	r3, #2
 800195e:	d116      	bne.n	800198e <HAL_RCC_OscConfig+0x33e>
    {
      /* When HSI is used as system clock it will not be disabled */
      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 8001960:	4b7c      	ldr	r3, [pc, #496]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001962:	681b      	ldr	r3, [r3, #0]
 8001964:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8001968:	2b00      	cmp	r3, #0
 800196a:	d005      	beq.n	8001978 <HAL_RCC_OscConfig+0x328>
 800196c:	687b      	ldr	r3, [r7, #4]
 800196e:	68db      	ldr	r3, [r3, #12]
 8001970:	2b00      	cmp	r3, #0
 8001972:	d101      	bne.n	8001978 <HAL_RCC_OscConfig+0x328>
      {
        return HAL_ERROR;
 8001974:	2301      	movs	r3, #1
 8001976:	e23f      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8001978:	4b76      	ldr	r3, [pc, #472]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 800197a:	685b      	ldr	r3, [r3, #4]
 800197c:	f023 52f8 	bic.w	r2, r3, #520093696	; 0x1f000000
 8001980:	687b      	ldr	r3, [r7, #4]
 8001982:	691b      	ldr	r3, [r3, #16]
 8001984:	061b      	lsls	r3, r3, #24
 8001986:	4973      	ldr	r1, [pc, #460]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001988:	4313      	orrs	r3, r2
 800198a:	604b      	str	r3, [r1, #4]
      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 800198c:	e040      	b.n	8001a10 <HAL_RCC_OscConfig+0x3c0>
      }
    }
    else
    {
      /* Check the HSI State */
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 800198e:	687b      	ldr	r3, [r7, #4]
 8001990:	68db      	ldr	r3, [r3, #12]
 8001992:	2b00      	cmp	r3, #0
 8001994:	d023      	beq.n	80019de <HAL_RCC_OscConfig+0x38e>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 8001996:	4b6f      	ldr	r3, [pc, #444]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001998:	681b      	ldr	r3, [r3, #0]
 800199a:	4a6e      	ldr	r2, [pc, #440]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 800199c:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 80019a0:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80019a2:	f7ff f9af 	bl	8000d04 <HAL_GetTick>
 80019a6:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 80019a8:	e008      	b.n	80019bc <HAL_RCC_OscConfig+0x36c>
        {
          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 80019aa:	f7ff f9ab 	bl	8000d04 <HAL_GetTick>
 80019ae:	4602      	mov	r2, r0
 80019b0:	693b      	ldr	r3, [r7, #16]
 80019b2:	1ad3      	subs	r3, r2, r3
 80019b4:	2b02      	cmp	r3, #2
 80019b6:	d901      	bls.n	80019bc <HAL_RCC_OscConfig+0x36c>
          {
            return HAL_TIMEOUT;
 80019b8:	2303      	movs	r3, #3
 80019ba:	e21d      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 80019bc:	4b65      	ldr	r3, [pc, #404]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 80019be:	681b      	ldr	r3, [r3, #0]
 80019c0:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 80019c4:	2b00      	cmp	r3, #0
 80019c6:	d0f0      	beq.n	80019aa <HAL_RCC_OscConfig+0x35a>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80019c8:	4b62      	ldr	r3, [pc, #392]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 80019ca:	685b      	ldr	r3, [r3, #4]
 80019cc:	f023 52f8 	bic.w	r2, r3, #520093696	; 0x1f000000
 80019d0:	687b      	ldr	r3, [r7, #4]
 80019d2:	691b      	ldr	r3, [r3, #16]
 80019d4:	061b      	lsls	r3, r3, #24
 80019d6:	495f      	ldr	r1, [pc, #380]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 80019d8:	4313      	orrs	r3, r2
 80019da:	604b      	str	r3, [r1, #4]
 80019dc:	e018      	b.n	8001a10 <HAL_RCC_OscConfig+0x3c0>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 80019de:	4b5d      	ldr	r3, [pc, #372]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 80019e0:	681b      	ldr	r3, [r3, #0]
 80019e2:	4a5c      	ldr	r2, [pc, #368]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 80019e4:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 80019e8:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80019ea:	f7ff f98b 	bl	8000d04 <HAL_GetTick>
 80019ee:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 80019f0:	e008      	b.n	8001a04 <HAL_RCC_OscConfig+0x3b4>
        {
          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 80019f2:	f7ff f987 	bl	8000d04 <HAL_GetTick>
 80019f6:	4602      	mov	r2, r0
 80019f8:	693b      	ldr	r3, [r7, #16]
 80019fa:	1ad3      	subs	r3, r2, r3
 80019fc:	2b02      	cmp	r3, #2
 80019fe:	d901      	bls.n	8001a04 <HAL_RCC_OscConfig+0x3b4>
          {
            return HAL_TIMEOUT;
 8001a00:	2303      	movs	r3, #3
 8001a02:	e1f9      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 8001a04:	4b53      	ldr	r3, [pc, #332]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001a06:	681b      	ldr	r3, [r3, #0]
 8001a08:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8001a0c:	2b00      	cmp	r3, #0
 8001a0e:	d1f0      	bne.n	80019f2 <HAL_RCC_OscConfig+0x3a2>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8001a10:	687b      	ldr	r3, [r7, #4]
 8001a12:	681b      	ldr	r3, [r3, #0]
 8001a14:	f003 0308 	and.w	r3, r3, #8
 8001a18:	2b00      	cmp	r3, #0
 8001a1a:	d03c      	beq.n	8001a96 <HAL_RCC_OscConfig+0x446>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8001a1c:	687b      	ldr	r3, [r7, #4]
 8001a1e:	695b      	ldr	r3, [r3, #20]
 8001a20:	2b00      	cmp	r3, #0
 8001a22:	d01c      	beq.n	8001a5e <HAL_RCC_OscConfig+0x40e>
        MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
      }
#endif /* RCC_CSR_LSIPREDIV */

      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8001a24:	4b4b      	ldr	r3, [pc, #300]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001a26:	f8d3 3094 	ldr.w	r3, [r3, #148]	; 0x94
 8001a2a:	4a4a      	ldr	r2, [pc, #296]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001a2c:	f043 0301 	orr.w	r3, r3, #1
 8001a30:	f8c2 3094 	str.w	r3, [r2, #148]	; 0x94

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8001a34:	f7ff f966 	bl	8000d04 <HAL_GetTick>
 8001a38:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8001a3a:	e008      	b.n	8001a4e <HAL_RCC_OscConfig+0x3fe>
      {
        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8001a3c:	f7ff f962 	bl	8000d04 <HAL_GetTick>
 8001a40:	4602      	mov	r2, r0
 8001a42:	693b      	ldr	r3, [r7, #16]
 8001a44:	1ad3      	subs	r3, r2, r3
 8001a46:	2b02      	cmp	r3, #2
 8001a48:	d901      	bls.n	8001a4e <HAL_RCC_OscConfig+0x3fe>
        {
          return HAL_TIMEOUT;
 8001a4a:	2303      	movs	r3, #3
 8001a4c:	e1d4      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8001a4e:	4b41      	ldr	r3, [pc, #260]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001a50:	f8d3 3094 	ldr.w	r3, [r3, #148]	; 0x94
 8001a54:	f003 0302 	and.w	r3, r3, #2
 8001a58:	2b00      	cmp	r3, #0
 8001a5a:	d0ef      	beq.n	8001a3c <HAL_RCC_OscConfig+0x3ec>
 8001a5c:	e01b      	b.n	8001a96 <HAL_RCC_OscConfig+0x446>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8001a5e:	4b3d      	ldr	r3, [pc, #244]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001a60:	f8d3 3094 	ldr.w	r3, [r3, #148]	; 0x94
 8001a64:	4a3b      	ldr	r2, [pc, #236]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001a66:	f023 0301 	bic.w	r3, r3, #1
 8001a6a:	f8c2 3094 	str.w	r3, [r2, #148]	; 0x94

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8001a6e:	f7ff f949 	bl	8000d04 <HAL_GetTick>
 8001a72:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is disabled */
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 8001a74:	e008      	b.n	8001a88 <HAL_RCC_OscConfig+0x438>
      {
        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8001a76:	f7ff f945 	bl	8000d04 <HAL_GetTick>
 8001a7a:	4602      	mov	r2, r0
 8001a7c:	693b      	ldr	r3, [r7, #16]
 8001a7e:	1ad3      	subs	r3, r2, r3
 8001a80:	2b02      	cmp	r3, #2
 8001a82:	d901      	bls.n	8001a88 <HAL_RCC_OscConfig+0x438>
        {
          return HAL_TIMEOUT;
 8001a84:	2303      	movs	r3, #3
 8001a86:	e1b7      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 8001a88:	4b32      	ldr	r3, [pc, #200]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001a8a:	f8d3 3094 	ldr.w	r3, [r3, #148]	; 0x94
 8001a8e:	f003 0302 	and.w	r3, r3, #2
 8001a92:	2b00      	cmp	r3, #0
 8001a94:	d1ef      	bne.n	8001a76 <HAL_RCC_OscConfig+0x426>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8001a96:	687b      	ldr	r3, [r7, #4]
 8001a98:	681b      	ldr	r3, [r3, #0]
 8001a9a:	f003 0304 	and.w	r3, r3, #4
 8001a9e:	2b00      	cmp	r3, #0
 8001aa0:	f000 80a6 	beq.w	8001bf0 <HAL_RCC_OscConfig+0x5a0>
  {
    FlagStatus       pwrclkchanged = RESET;
 8001aa4:	2300      	movs	r3, #0
 8001aa6:	77fb      	strb	r3, [r7, #31]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
 8001aa8:	4b2a      	ldr	r3, [pc, #168]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001aaa:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8001aac:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001ab0:	2b00      	cmp	r3, #0
 8001ab2:	d10d      	bne.n	8001ad0 <HAL_RCC_OscConfig+0x480>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8001ab4:	4b27      	ldr	r3, [pc, #156]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001ab6:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8001ab8:	4a26      	ldr	r2, [pc, #152]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001aba:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8001abe:	6593      	str	r3, [r2, #88]	; 0x58
 8001ac0:	4b24      	ldr	r3, [pc, #144]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001ac2:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8001ac4:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001ac8:	60bb      	str	r3, [r7, #8]
 8001aca:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8001acc:	2301      	movs	r3, #1
 8001ace:	77fb      	strb	r3, [r7, #31]
    }

    if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8001ad0:	4b21      	ldr	r3, [pc, #132]	; (8001b58 <HAL_RCC_OscConfig+0x508>)
 8001ad2:	681b      	ldr	r3, [r3, #0]
 8001ad4:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8001ad8:	2b00      	cmp	r3, #0
 8001ada:	d118      	bne.n	8001b0e <HAL_RCC_OscConfig+0x4be>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8001adc:	4b1e      	ldr	r3, [pc, #120]	; (8001b58 <HAL_RCC_OscConfig+0x508>)
 8001ade:	681b      	ldr	r3, [r3, #0]
 8001ae0:	4a1d      	ldr	r2, [pc, #116]	; (8001b58 <HAL_RCC_OscConfig+0x508>)
 8001ae2:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8001ae6:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8001ae8:	f7ff f90c 	bl	8000d04 <HAL_GetTick>
 8001aec:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8001aee:	e008      	b.n	8001b02 <HAL_RCC_OscConfig+0x4b2>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8001af0:	f7ff f908 	bl	8000d04 <HAL_GetTick>
 8001af4:	4602      	mov	r2, r0
 8001af6:	693b      	ldr	r3, [r7, #16]
 8001af8:	1ad3      	subs	r3, r2, r3
 8001afa:	2b02      	cmp	r3, #2
 8001afc:	d901      	bls.n	8001b02 <HAL_RCC_OscConfig+0x4b2>
        {
          return HAL_TIMEOUT;
 8001afe:	2303      	movs	r3, #3
 8001b00:	e17a      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8001b02:	4b15      	ldr	r3, [pc, #84]	; (8001b58 <HAL_RCC_OscConfig+0x508>)
 8001b04:	681b      	ldr	r3, [r3, #0]
 8001b06:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8001b0a:	2b00      	cmp	r3, #0
 8001b0c:	d0f0      	beq.n	8001af0 <HAL_RCC_OscConfig+0x4a0>
    {
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
    }
#else
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8001b0e:	687b      	ldr	r3, [r7, #4]
 8001b10:	689b      	ldr	r3, [r3, #8]
 8001b12:	2b01      	cmp	r3, #1
 8001b14:	d108      	bne.n	8001b28 <HAL_RCC_OscConfig+0x4d8>
 8001b16:	4b0f      	ldr	r3, [pc, #60]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001b18:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8001b1c:	4a0d      	ldr	r2, [pc, #52]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001b1e:	f043 0301 	orr.w	r3, r3, #1
 8001b22:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
 8001b26:	e029      	b.n	8001b7c <HAL_RCC_OscConfig+0x52c>
 8001b28:	687b      	ldr	r3, [r7, #4]
 8001b2a:	689b      	ldr	r3, [r3, #8]
 8001b2c:	2b05      	cmp	r3, #5
 8001b2e:	d115      	bne.n	8001b5c <HAL_RCC_OscConfig+0x50c>
 8001b30:	4b08      	ldr	r3, [pc, #32]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001b32:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8001b36:	4a07      	ldr	r2, [pc, #28]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001b38:	f043 0304 	orr.w	r3, r3, #4
 8001b3c:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
 8001b40:	4b04      	ldr	r3, [pc, #16]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001b42:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8001b46:	4a03      	ldr	r2, [pc, #12]	; (8001b54 <HAL_RCC_OscConfig+0x504>)
 8001b48:	f043 0301 	orr.w	r3, r3, #1
 8001b4c:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
 8001b50:	e014      	b.n	8001b7c <HAL_RCC_OscConfig+0x52c>
 8001b52:	bf00      	nop
 8001b54:	40021000 	.word	0x40021000
 8001b58:	40007000 	.word	0x40007000
 8001b5c:	4b9c      	ldr	r3, [pc, #624]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001b5e:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8001b62:	4a9b      	ldr	r2, [pc, #620]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001b64:	f023 0301 	bic.w	r3, r3, #1
 8001b68:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
 8001b6c:	4b98      	ldr	r3, [pc, #608]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001b6e:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8001b72:	4a97      	ldr	r2, [pc, #604]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001b74:	f023 0304 	bic.w	r3, r3, #4
 8001b78:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
#endif /* RCC_BDCR_LSESYSDIS */

    /* Check the LSE State */
    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 8001b7c:	687b      	ldr	r3, [r7, #4]
 8001b7e:	689b      	ldr	r3, [r3, #8]
 8001b80:	2b00      	cmp	r3, #0
 8001b82:	d016      	beq.n	8001bb2 <HAL_RCC_OscConfig+0x562>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8001b84:	f7ff f8be 	bl	8000d04 <HAL_GetTick>
 8001b88:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8001b8a:	e00a      	b.n	8001ba2 <HAL_RCC_OscConfig+0x552>
      {
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8001b8c:	f7ff f8ba 	bl	8000d04 <HAL_GetTick>
 8001b90:	4602      	mov	r2, r0
 8001b92:	693b      	ldr	r3, [r7, #16]
 8001b94:	1ad3      	subs	r3, r2, r3
 8001b96:	f241 3288 	movw	r2, #5000	; 0x1388
 8001b9a:	4293      	cmp	r3, r2
 8001b9c:	d901      	bls.n	8001ba2 <HAL_RCC_OscConfig+0x552>
        {
          return HAL_TIMEOUT;
 8001b9e:	2303      	movs	r3, #3
 8001ba0:	e12a      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8001ba2:	4b8b      	ldr	r3, [pc, #556]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001ba4:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8001ba8:	f003 0302 	and.w	r3, r3, #2
 8001bac:	2b00      	cmp	r3, #0
 8001bae:	d0ed      	beq.n	8001b8c <HAL_RCC_OscConfig+0x53c>
 8001bb0:	e015      	b.n	8001bde <HAL_RCC_OscConfig+0x58e>
      }
    }
    else
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8001bb2:	f7ff f8a7 	bl	8000d04 <HAL_GetTick>
 8001bb6:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is disabled */
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 8001bb8:	e00a      	b.n	8001bd0 <HAL_RCC_OscConfig+0x580>
      {
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8001bba:	f7ff f8a3 	bl	8000d04 <HAL_GetTick>
 8001bbe:	4602      	mov	r2, r0
 8001bc0:	693b      	ldr	r3, [r7, #16]
 8001bc2:	1ad3      	subs	r3, r2, r3
 8001bc4:	f241 3288 	movw	r2, #5000	; 0x1388
 8001bc8:	4293      	cmp	r3, r2
 8001bca:	d901      	bls.n	8001bd0 <HAL_RCC_OscConfig+0x580>
        {
          return HAL_TIMEOUT;
 8001bcc:	2303      	movs	r3, #3
 8001bce:	e113      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 8001bd0:	4b7f      	ldr	r3, [pc, #508]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001bd2:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8001bd6:	f003 0302 	and.w	r3, r3, #2
 8001bda:	2b00      	cmp	r3, #0
 8001bdc:	d1ed      	bne.n	8001bba <HAL_RCC_OscConfig+0x56a>
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
#endif /* RCC_BDCR_LSESYSDIS */
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 8001bde:	7ffb      	ldrb	r3, [r7, #31]
 8001be0:	2b01      	cmp	r3, #1
 8001be2:	d105      	bne.n	8001bf0 <HAL_RCC_OscConfig+0x5a0>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8001be4:	4b7a      	ldr	r3, [pc, #488]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001be6:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8001be8:	4a79      	ldr	r2, [pc, #484]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001bea:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8001bee:	6593      	str	r3, [r2, #88]	; 0x58
#endif /* RCC_HSI48_SUPPORT */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));

  if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
 8001bf0:	687b      	ldr	r3, [r7, #4]
 8001bf2:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001bf4:	2b00      	cmp	r3, #0
 8001bf6:	f000 80fe 	beq.w	8001df6 <HAL_RCC_OscConfig+0x7a6>
  {
    /* PLL On ? */
    if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
 8001bfa:	687b      	ldr	r3, [r7, #4]
 8001bfc:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001bfe:	2b02      	cmp	r3, #2
 8001c00:	f040 80d0 	bne.w	8001da4 <HAL_RCC_OscConfig+0x754>
#endif /* RCC_PLLP_SUPPORT */
      assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
      assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));

      /* Do nothing if PLL configuration is the unchanged */
      pll_config = RCC->PLLCFGR;
 8001c04:	4b72      	ldr	r3, [pc, #456]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001c06:	68db      	ldr	r3, [r3, #12]
 8001c08:	617b      	str	r3, [r7, #20]
      if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8001c0a:	697b      	ldr	r3, [r7, #20]
 8001c0c:	f003 0203 	and.w	r2, r3, #3
 8001c10:	687b      	ldr	r3, [r7, #4]
 8001c12:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8001c14:	429a      	cmp	r2, r3
 8001c16:	d130      	bne.n	8001c7a <HAL_RCC_OscConfig+0x62a>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLM)    != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
 8001c18:	697b      	ldr	r3, [r7, #20]
 8001c1a:	f003 0270 	and.w	r2, r3, #112	; 0x70
 8001c1e:	687b      	ldr	r3, [r7, #4]
 8001c20:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001c22:	3b01      	subs	r3, #1
 8001c24:	011b      	lsls	r3, r3, #4
      if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8001c26:	429a      	cmp	r2, r3
 8001c28:	d127      	bne.n	8001c7a <HAL_RCC_OscConfig+0x62a>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLN)    != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
 8001c2a:	697b      	ldr	r3, [r7, #20]
 8001c2c:	f403 42fe 	and.w	r2, r3, #32512	; 0x7f00
 8001c30:	687b      	ldr	r3, [r7, #4]
 8001c32:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8001c34:	021b      	lsls	r3, r3, #8
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLM)    != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
 8001c36:	429a      	cmp	r2, r3
 8001c38:	d11f      	bne.n	8001c7a <HAL_RCC_OscConfig+0x62a>
#if defined(RCC_PLLP_SUPPORT)
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
#else
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLP)    != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
 8001c3a:	697b      	ldr	r3, [r7, #20]
 8001c3c:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001c40:	687a      	ldr	r2, [r7, #4]
 8001c42:	6b92      	ldr	r2, [r2, #56]	; 0x38
 8001c44:	2a07      	cmp	r2, #7
 8001c46:	bf14      	ite	ne
 8001c48:	2201      	movne	r2, #1
 8001c4a:	2200      	moveq	r2, #0
 8001c4c:	b2d2      	uxtb	r2, r2
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLN)    != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
 8001c4e:	4293      	cmp	r3, r2
 8001c50:	d113      	bne.n	8001c7a <HAL_RCC_OscConfig+0x62a>
#endif
#endif
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ)    != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
 8001c52:	697b      	ldr	r3, [r7, #20]
 8001c54:	f403 02c0 	and.w	r2, r3, #6291456	; 0x600000
 8001c58:	687b      	ldr	r3, [r7, #4]
 8001c5a:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8001c5c:	085b      	lsrs	r3, r3, #1
 8001c5e:	3b01      	subs	r3, #1
 8001c60:	055b      	lsls	r3, r3, #21
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLP)    != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
 8001c62:	429a      	cmp	r2, r3
 8001c64:	d109      	bne.n	8001c7a <HAL_RCC_OscConfig+0x62a>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLR)    != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
 8001c66:	697b      	ldr	r3, [r7, #20]
 8001c68:	f003 62c0 	and.w	r2, r3, #100663296	; 0x6000000
 8001c6c:	687b      	ldr	r3, [r7, #4]
 8001c6e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001c70:	085b      	lsrs	r3, r3, #1
 8001c72:	3b01      	subs	r3, #1
 8001c74:	065b      	lsls	r3, r3, #25
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ)    != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
 8001c76:	429a      	cmp	r2, r3
 8001c78:	d06e      	beq.n	8001d58 <HAL_RCC_OscConfig+0x708>
      {
        /* Check if the PLL is used as system clock or not */
        if(sysclk_source != RCC_CFGR_SWS_PLL)
 8001c7a:	69bb      	ldr	r3, [r7, #24]
 8001c7c:	2b0c      	cmp	r3, #12
 8001c7e:	d069      	beq.n	8001d54 <HAL_RCC_OscConfig+0x704>
        {
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
          /* Check if main PLL can be updated */
          /* Not possible if the source is shared by other enabled PLLSAIx */
          if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
 8001c80:	4b53      	ldr	r3, [pc, #332]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001c82:	681b      	ldr	r3, [r3, #0]
 8001c84:	f003 6380 	and.w	r3, r3, #67108864	; 0x4000000
 8001c88:	2b00      	cmp	r3, #0
 8001c8a:	d105      	bne.n	8001c98 <HAL_RCC_OscConfig+0x648>
#if defined(RCC_PLLSAI2_SUPPORT)
             || (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
 8001c8c:	4b50      	ldr	r3, [pc, #320]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001c8e:	681b      	ldr	r3, [r3, #0]
 8001c90:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001c94:	2b00      	cmp	r3, #0
 8001c96:	d001      	beq.n	8001c9c <HAL_RCC_OscConfig+0x64c>
#endif
            )
          {
            return HAL_ERROR;
 8001c98:	2301      	movs	r3, #1
 8001c9a:	e0ad      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
          }
          else
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
          {
            /* Disable the main PLL. */
            __HAL_RCC_PLL_DISABLE();
 8001c9c:	4b4c      	ldr	r3, [pc, #304]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001c9e:	681b      	ldr	r3, [r3, #0]
 8001ca0:	4a4b      	ldr	r2, [pc, #300]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001ca2:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
 8001ca6:	6013      	str	r3, [r2, #0]

            /* Get Start Tick*/
            tickstart = HAL_GetTick();
 8001ca8:	f7ff f82c 	bl	8000d04 <HAL_GetTick>
 8001cac:	6138      	str	r0, [r7, #16]

            /* Wait till PLL is ready */
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8001cae:	e008      	b.n	8001cc2 <HAL_RCC_OscConfig+0x672>
            {
              if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8001cb0:	f7ff f828 	bl	8000d04 <HAL_GetTick>
 8001cb4:	4602      	mov	r2, r0
 8001cb6:	693b      	ldr	r3, [r7, #16]
 8001cb8:	1ad3      	subs	r3, r2, r3
 8001cba:	2b02      	cmp	r3, #2
 8001cbc:	d901      	bls.n	8001cc2 <HAL_RCC_OscConfig+0x672>
              {
                return HAL_TIMEOUT;
 8001cbe:	2303      	movs	r3, #3
 8001cc0:	e09a      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8001cc2:	4b43      	ldr	r3, [pc, #268]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001cc4:	681b      	ldr	r3, [r3, #0]
 8001cc6:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8001cca:	2b00      	cmp	r3, #0
 8001ccc:	d1f0      	bne.n	8001cb0 <HAL_RCC_OscConfig+0x660>
              }
            }

            /* Configure the main PLL clock source, multiplication and division factors. */
#if defined(RCC_PLLP_SUPPORT)
            __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8001cce:	4b40      	ldr	r3, [pc, #256]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001cd0:	68da      	ldr	r2, [r3, #12]
 8001cd2:	4b40      	ldr	r3, [pc, #256]	; (8001dd4 <HAL_RCC_OscConfig+0x784>)
 8001cd4:	4013      	ands	r3, r2
 8001cd6:	687a      	ldr	r2, [r7, #4]
 8001cd8:	6ad1      	ldr	r1, [r2, #44]	; 0x2c
 8001cda:	687a      	ldr	r2, [r7, #4]
 8001cdc:	6b12      	ldr	r2, [r2, #48]	; 0x30
 8001cde:	3a01      	subs	r2, #1
 8001ce0:	0112      	lsls	r2, r2, #4
 8001ce2:	4311      	orrs	r1, r2
 8001ce4:	687a      	ldr	r2, [r7, #4]
 8001ce6:	6b52      	ldr	r2, [r2, #52]	; 0x34
 8001ce8:	0212      	lsls	r2, r2, #8
 8001cea:	4311      	orrs	r1, r2
 8001cec:	687a      	ldr	r2, [r7, #4]
 8001cee:	6bd2      	ldr	r2, [r2, #60]	; 0x3c
 8001cf0:	0852      	lsrs	r2, r2, #1
 8001cf2:	3a01      	subs	r2, #1
 8001cf4:	0552      	lsls	r2, r2, #21
 8001cf6:	4311      	orrs	r1, r2
 8001cf8:	687a      	ldr	r2, [r7, #4]
 8001cfa:	6c12      	ldr	r2, [r2, #64]	; 0x40
 8001cfc:	0852      	lsrs	r2, r2, #1
 8001cfe:	3a01      	subs	r2, #1
 8001d00:	0652      	lsls	r2, r2, #25
 8001d02:	4311      	orrs	r1, r2
 8001d04:	687a      	ldr	r2, [r7, #4]
 8001d06:	6b92      	ldr	r2, [r2, #56]	; 0x38
 8001d08:	0912      	lsrs	r2, r2, #4
 8001d0a:	0452      	lsls	r2, r2, #17
 8001d0c:	430a      	orrs	r2, r1
 8001d0e:	4930      	ldr	r1, [pc, #192]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d10:	4313      	orrs	r3, r2
 8001d12:	60cb      	str	r3, [r1, #12]
                                 RCC_OscInitStruct->PLL.PLLQ,
                                 RCC_OscInitStruct->PLL.PLLR);
#endif

            /* Enable the main PLL. */
            __HAL_RCC_PLL_ENABLE();
 8001d14:	4b2e      	ldr	r3, [pc, #184]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d16:	681b      	ldr	r3, [r3, #0]
 8001d18:	4a2d      	ldr	r2, [pc, #180]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d1a:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
 8001d1e:	6013      	str	r3, [r2, #0]

            /* Enable PLL System Clock output. */
            __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
 8001d20:	4b2b      	ldr	r3, [pc, #172]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d22:	68db      	ldr	r3, [r3, #12]
 8001d24:	4a2a      	ldr	r2, [pc, #168]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d26:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
 8001d2a:	60d3      	str	r3, [r2, #12]

            /* Get Start Tick*/
            tickstart = HAL_GetTick();
 8001d2c:	f7fe ffea 	bl	8000d04 <HAL_GetTick>
 8001d30:	6138      	str	r0, [r7, #16]

            /* Wait till PLL is ready */
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001d32:	e008      	b.n	8001d46 <HAL_RCC_OscConfig+0x6f6>
            {
              if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8001d34:	f7fe ffe6 	bl	8000d04 <HAL_GetTick>
 8001d38:	4602      	mov	r2, r0
 8001d3a:	693b      	ldr	r3, [r7, #16]
 8001d3c:	1ad3      	subs	r3, r2, r3
 8001d3e:	2b02      	cmp	r3, #2
 8001d40:	d901      	bls.n	8001d46 <HAL_RCC_OscConfig+0x6f6>
              {
                return HAL_TIMEOUT;
 8001d42:	2303      	movs	r3, #3
 8001d44:	e058      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001d46:	4b22      	ldr	r3, [pc, #136]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d48:	681b      	ldr	r3, [r3, #0]
 8001d4a:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8001d4e:	2b00      	cmp	r3, #0
 8001d50:	d0f0      	beq.n	8001d34 <HAL_RCC_OscConfig+0x6e4>
        if(sysclk_source != RCC_CFGR_SWS_PLL)
 8001d52:	e050      	b.n	8001df6 <HAL_RCC_OscConfig+0x7a6>
          }
        }
        else
        {
          /* PLL is already used as System core clock */
          return HAL_ERROR;
 8001d54:	2301      	movs	r3, #1
 8001d56:	e04f      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      }
      else
      {
        /* PLL configuration is unchanged */
        /* Re-enable PLL if it was disabled (ie. low power mode) */
        if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001d58:	4b1d      	ldr	r3, [pc, #116]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d5a:	681b      	ldr	r3, [r3, #0]
 8001d5c:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8001d60:	2b00      	cmp	r3, #0
 8001d62:	d148      	bne.n	8001df6 <HAL_RCC_OscConfig+0x7a6>
        {
          /* Enable the main PLL. */
          __HAL_RCC_PLL_ENABLE();
 8001d64:	4b1a      	ldr	r3, [pc, #104]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d66:	681b      	ldr	r3, [r3, #0]
 8001d68:	4a19      	ldr	r2, [pc, #100]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d6a:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
 8001d6e:	6013      	str	r3, [r2, #0]

          /* Enable PLL System Clock output. */
          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
 8001d70:	4b17      	ldr	r3, [pc, #92]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d72:	68db      	ldr	r3, [r3, #12]
 8001d74:	4a16      	ldr	r2, [pc, #88]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d76:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
 8001d7a:	60d3      	str	r3, [r2, #12]

          /* Get Start Tick*/
          tickstart = HAL_GetTick();
 8001d7c:	f7fe ffc2 	bl	8000d04 <HAL_GetTick>
 8001d80:	6138      	str	r0, [r7, #16]

          /* Wait till PLL is ready */
          while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001d82:	e008      	b.n	8001d96 <HAL_RCC_OscConfig+0x746>
          {
            if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8001d84:	f7fe ffbe 	bl	8000d04 <HAL_GetTick>
 8001d88:	4602      	mov	r2, r0
 8001d8a:	693b      	ldr	r3, [r7, #16]
 8001d8c:	1ad3      	subs	r3, r2, r3
 8001d8e:	2b02      	cmp	r3, #2
 8001d90:	d901      	bls.n	8001d96 <HAL_RCC_OscConfig+0x746>
            {
              return HAL_TIMEOUT;
 8001d92:	2303      	movs	r3, #3
 8001d94:	e030      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
          while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001d96:	4b0e      	ldr	r3, [pc, #56]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001d98:	681b      	ldr	r3, [r3, #0]
 8001d9a:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8001d9e:	2b00      	cmp	r3, #0
 8001da0:	d0f0      	beq.n	8001d84 <HAL_RCC_OscConfig+0x734>
 8001da2:	e028      	b.n	8001df6 <HAL_RCC_OscConfig+0x7a6>
      }
    }
    else
    {
      /* Check that PLL is not used as system clock or not */
      if(sysclk_source != RCC_CFGR_SWS_PLL)
 8001da4:	69bb      	ldr	r3, [r7, #24]
 8001da6:	2b0c      	cmp	r3, #12
 8001da8:	d023      	beq.n	8001df2 <HAL_RCC_OscConfig+0x7a2>
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8001daa:	4b09      	ldr	r3, [pc, #36]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001dac:	681b      	ldr	r3, [r3, #0]
 8001dae:	4a08      	ldr	r2, [pc, #32]	; (8001dd0 <HAL_RCC_OscConfig+0x780>)
 8001db0:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
 8001db4:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001db6:	f7fe ffa5 	bl	8000d04 <HAL_GetTick>
 8001dba:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8001dbc:	e00c      	b.n	8001dd8 <HAL_RCC_OscConfig+0x788>
        {
          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8001dbe:	f7fe ffa1 	bl	8000d04 <HAL_GetTick>
 8001dc2:	4602      	mov	r2, r0
 8001dc4:	693b      	ldr	r3, [r7, #16]
 8001dc6:	1ad3      	subs	r3, r2, r3
 8001dc8:	2b02      	cmp	r3, #2
 8001dca:	d905      	bls.n	8001dd8 <HAL_RCC_OscConfig+0x788>
          {
            return HAL_TIMEOUT;
 8001dcc:	2303      	movs	r3, #3
 8001dce:	e013      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
 8001dd0:	40021000 	.word	0x40021000
 8001dd4:	f99d808c 	.word	0xf99d808c
        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8001dd8:	4b09      	ldr	r3, [pc, #36]	; (8001e00 <HAL_RCC_OscConfig+0x7b0>)
 8001dda:	681b      	ldr	r3, [r3, #0]
 8001ddc:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8001de0:	2b00      	cmp	r3, #0
 8001de2:	d1ec      	bne.n	8001dbe <HAL_RCC_OscConfig+0x76e>
          }
        }
        /* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
        RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
 8001de4:	4b06      	ldr	r3, [pc, #24]	; (8001e00 <HAL_RCC_OscConfig+0x7b0>)
 8001de6:	68da      	ldr	r2, [r3, #12]
 8001de8:	4905      	ldr	r1, [pc, #20]	; (8001e00 <HAL_RCC_OscConfig+0x7b0>)
 8001dea:	4b06      	ldr	r3, [pc, #24]	; (8001e04 <HAL_RCC_OscConfig+0x7b4>)
 8001dec:	4013      	ands	r3, r2
 8001dee:	60cb      	str	r3, [r1, #12]
 8001df0:	e001      	b.n	8001df6 <HAL_RCC_OscConfig+0x7a6>
#endif /* RCC_PLLSAI2_SUPPORT */
      }
      else
      {
        /* PLL is already used as System core clock */
        return HAL_ERROR;
 8001df2:	2301      	movs	r3, #1
 8001df4:	e000      	b.n	8001df8 <HAL_RCC_OscConfig+0x7a8>
      }
    }
  }
  return HAL_OK;
 8001df6:	2300      	movs	r3, #0
}
 8001df8:	4618      	mov	r0, r3
 8001dfa:	3720      	adds	r7, #32
 8001dfc:	46bd      	mov	sp, r7
 8001dfe:	bd80      	pop	{r7, pc}
 8001e00:	40021000 	.word	0x40021000
 8001e04:	feeefffc 	.word	0xfeeefffc

08001e08 <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 8001e08:	b580      	push	{r7, lr}
 8001e0a:	b084      	sub	sp, #16
 8001e0c:	af00      	add	r7, sp, #0
 8001e0e:	6078      	str	r0, [r7, #4]
 8001e10:	6039      	str	r1, [r7, #0]
  uint32_t hpre = RCC_SYSCLK_DIV1;
#endif
  HAL_StatusTypeDef status;

  /* Check Null pointer */
  if(RCC_ClkInitStruct == NULL)
 8001e12:	687b      	ldr	r3, [r7, #4]
 8001e14:	2b00      	cmp	r3, #0
 8001e16:	d101      	bne.n	8001e1c <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8001e18:	2301      	movs	r3, #1
 8001e1a:	e0e7      	b.n	8001fec <HAL_RCC_ClockConfig+0x1e4>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 8001e1c:	4b75      	ldr	r3, [pc, #468]	; (8001ff4 <HAL_RCC_ClockConfig+0x1ec>)
 8001e1e:	681b      	ldr	r3, [r3, #0]
 8001e20:	f003 0307 	and.w	r3, r3, #7
 8001e24:	683a      	ldr	r2, [r7, #0]
 8001e26:	429a      	cmp	r2, r3
 8001e28:	d910      	bls.n	8001e4c <HAL_RCC_ClockConfig+0x44>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8001e2a:	4b72      	ldr	r3, [pc, #456]	; (8001ff4 <HAL_RCC_ClockConfig+0x1ec>)
 8001e2c:	681b      	ldr	r3, [r3, #0]
 8001e2e:	f023 0207 	bic.w	r2, r3, #7
 8001e32:	4970      	ldr	r1, [pc, #448]	; (8001ff4 <HAL_RCC_ClockConfig+0x1ec>)
 8001e34:	683b      	ldr	r3, [r7, #0]
 8001e36:	4313      	orrs	r3, r2
 8001e38:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8001e3a:	4b6e      	ldr	r3, [pc, #440]	; (8001ff4 <HAL_RCC_ClockConfig+0x1ec>)
 8001e3c:	681b      	ldr	r3, [r3, #0]
 8001e3e:	f003 0307 	and.w	r3, r3, #7
 8001e42:	683a      	ldr	r2, [r7, #0]
 8001e44:	429a      	cmp	r2, r3
 8001e46:	d001      	beq.n	8001e4c <HAL_RCC_ClockConfig+0x44>
    {
      return HAL_ERROR;
 8001e48:	2301      	movs	r3, #1
 8001e4a:	e0cf      	b.n	8001fec <HAL_RCC_ClockConfig+0x1e4>
    }
  }

  /*----------------- HCLK Configuration prior to SYSCLK----------------------*/
  /* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8001e4c:	687b      	ldr	r3, [r7, #4]
 8001e4e:	681b      	ldr	r3, [r3, #0]
 8001e50:	f003 0302 	and.w	r3, r3, #2
 8001e54:	2b00      	cmp	r3, #0
 8001e56:	d010      	beq.n	8001e7a <HAL_RCC_ClockConfig+0x72>
  {
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));

    if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
 8001e58:	687b      	ldr	r3, [r7, #4]
 8001e5a:	689a      	ldr	r2, [r3, #8]
 8001e5c:	4b66      	ldr	r3, [pc, #408]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001e5e:	689b      	ldr	r3, [r3, #8]
 8001e60:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 8001e64:	429a      	cmp	r2, r3
 8001e66:	d908      	bls.n	8001e7a <HAL_RCC_ClockConfig+0x72>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8001e68:	4b63      	ldr	r3, [pc, #396]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001e6a:	689b      	ldr	r3, [r3, #8]
 8001e6c:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8001e70:	687b      	ldr	r3, [r7, #4]
 8001e72:	689b      	ldr	r3, [r3, #8]
 8001e74:	4960      	ldr	r1, [pc, #384]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001e76:	4313      	orrs	r3, r2
 8001e78:	608b      	str	r3, [r1, #8]
    }
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8001e7a:	687b      	ldr	r3, [r7, #4]
 8001e7c:	681b      	ldr	r3, [r3, #0]
 8001e7e:	f003 0301 	and.w	r3, r3, #1
 8001e82:	2b00      	cmp	r3, #0
 8001e84:	d04c      	beq.n	8001f20 <HAL_RCC_ClockConfig+0x118>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* PLL is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8001e86:	687b      	ldr	r3, [r7, #4]
 8001e88:	685b      	ldr	r3, [r3, #4]
 8001e8a:	2b03      	cmp	r3, #3
 8001e8c:	d107      	bne.n	8001e9e <HAL_RCC_ClockConfig+0x96>
    {
      /* Check the PLL ready flag */
      if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8001e8e:	4b5a      	ldr	r3, [pc, #360]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001e90:	681b      	ldr	r3, [r3, #0]
 8001e92:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8001e96:	2b00      	cmp	r3, #0
 8001e98:	d121      	bne.n	8001ede <HAL_RCC_ClockConfig+0xd6>
      {
        return HAL_ERROR;
 8001e9a:	2301      	movs	r3, #1
 8001e9c:	e0a6      	b.n	8001fec <HAL_RCC_ClockConfig+0x1e4>
#endif
    }
    else
    {
      /* HSE is selected as System Clock Source */
      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8001e9e:	687b      	ldr	r3, [r7, #4]
 8001ea0:	685b      	ldr	r3, [r3, #4]
 8001ea2:	2b02      	cmp	r3, #2
 8001ea4:	d107      	bne.n	8001eb6 <HAL_RCC_ClockConfig+0xae>
      {
        /* Check the HSE ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8001ea6:	4b54      	ldr	r3, [pc, #336]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001ea8:	681b      	ldr	r3, [r3, #0]
 8001eaa:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001eae:	2b00      	cmp	r3, #0
 8001eb0:	d115      	bne.n	8001ede <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8001eb2:	2301      	movs	r3, #1
 8001eb4:	e09a      	b.n	8001fec <HAL_RCC_ClockConfig+0x1e4>
        }
      }
      /* MSI is selected as System Clock Source */
      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
 8001eb6:	687b      	ldr	r3, [r7, #4]
 8001eb8:	685b      	ldr	r3, [r3, #4]
 8001eba:	2b00      	cmp	r3, #0
 8001ebc:	d107      	bne.n	8001ece <HAL_RCC_ClockConfig+0xc6>
      {
        /* Check the MSI ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 8001ebe:	4b4e      	ldr	r3, [pc, #312]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001ec0:	681b      	ldr	r3, [r3, #0]
 8001ec2:	f003 0302 	and.w	r3, r3, #2
 8001ec6:	2b00      	cmp	r3, #0
 8001ec8:	d109      	bne.n	8001ede <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8001eca:	2301      	movs	r3, #1
 8001ecc:	e08e      	b.n	8001fec <HAL_RCC_ClockConfig+0x1e4>
      }
      /* HSI is selected as System Clock Source */
      else
      {
        /* Check the HSI ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8001ece:	4b4a      	ldr	r3, [pc, #296]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001ed0:	681b      	ldr	r3, [r3, #0]
 8001ed2:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8001ed6:	2b00      	cmp	r3, #0
 8001ed8:	d101      	bne.n	8001ede <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8001eda:	2301      	movs	r3, #1
 8001edc:	e086      	b.n	8001fec <HAL_RCC_ClockConfig+0x1e4>
      }
#endif

    }

    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 8001ede:	4b46      	ldr	r3, [pc, #280]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001ee0:	689b      	ldr	r3, [r3, #8]
 8001ee2:	f023 0203 	bic.w	r2, r3, #3
 8001ee6:	687b      	ldr	r3, [r7, #4]
 8001ee8:	685b      	ldr	r3, [r3, #4]
 8001eea:	4943      	ldr	r1, [pc, #268]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001eec:	4313      	orrs	r3, r2
 8001eee:	608b      	str	r3, [r1, #8]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 8001ef0:	f7fe ff08 	bl	8000d04 <HAL_GetTick>
 8001ef4:	60f8      	str	r0, [r7, #12]

    while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8001ef6:	e00a      	b.n	8001f0e <HAL_RCC_ClockConfig+0x106>
    {
      if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001ef8:	f7fe ff04 	bl	8000d04 <HAL_GetTick>
 8001efc:	4602      	mov	r2, r0
 8001efe:	68fb      	ldr	r3, [r7, #12]
 8001f00:	1ad3      	subs	r3, r2, r3
 8001f02:	f241 3288 	movw	r2, #5000	; 0x1388
 8001f06:	4293      	cmp	r3, r2
 8001f08:	d901      	bls.n	8001f0e <HAL_RCC_ClockConfig+0x106>
      {
        return HAL_TIMEOUT;
 8001f0a:	2303      	movs	r3, #3
 8001f0c:	e06e      	b.n	8001fec <HAL_RCC_ClockConfig+0x1e4>
    while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8001f0e:	4b3a      	ldr	r3, [pc, #232]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001f10:	689b      	ldr	r3, [r3, #8]
 8001f12:	f003 020c 	and.w	r2, r3, #12
 8001f16:	687b      	ldr	r3, [r7, #4]
 8001f18:	685b      	ldr	r3, [r3, #4]
 8001f1a:	009b      	lsls	r3, r3, #2
 8001f1c:	429a      	cmp	r2, r3
 8001f1e:	d1eb      	bne.n	8001ef8 <HAL_RCC_ClockConfig+0xf0>
  }
#endif

  /*----------------- HCLK Configuration after SYSCLK-------------------------*/
  /* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8001f20:	687b      	ldr	r3, [r7, #4]
 8001f22:	681b      	ldr	r3, [r3, #0]
 8001f24:	f003 0302 	and.w	r3, r3, #2
 8001f28:	2b00      	cmp	r3, #0
 8001f2a:	d010      	beq.n	8001f4e <HAL_RCC_ClockConfig+0x146>
  {
    if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
 8001f2c:	687b      	ldr	r3, [r7, #4]
 8001f2e:	689a      	ldr	r2, [r3, #8]
 8001f30:	4b31      	ldr	r3, [pc, #196]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001f32:	689b      	ldr	r3, [r3, #8]
 8001f34:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 8001f38:	429a      	cmp	r2, r3
 8001f3a:	d208      	bcs.n	8001f4e <HAL_RCC_ClockConfig+0x146>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8001f3c:	4b2e      	ldr	r3, [pc, #184]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001f3e:	689b      	ldr	r3, [r3, #8]
 8001f40:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8001f44:	687b      	ldr	r3, [r7, #4]
 8001f46:	689b      	ldr	r3, [r3, #8]
 8001f48:	492b      	ldr	r1, [pc, #172]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001f4a:	4313      	orrs	r3, r2
 8001f4c:	608b      	str	r3, [r1, #8]
    }
  }

  /* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 8001f4e:	4b29      	ldr	r3, [pc, #164]	; (8001ff4 <HAL_RCC_ClockConfig+0x1ec>)
 8001f50:	681b      	ldr	r3, [r3, #0]
 8001f52:	f003 0307 	and.w	r3, r3, #7
 8001f56:	683a      	ldr	r2, [r7, #0]
 8001f58:	429a      	cmp	r2, r3
 8001f5a:	d210      	bcs.n	8001f7e <HAL_RCC_ClockConfig+0x176>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8001f5c:	4b25      	ldr	r3, [pc, #148]	; (8001ff4 <HAL_RCC_ClockConfig+0x1ec>)
 8001f5e:	681b      	ldr	r3, [r3, #0]
 8001f60:	f023 0207 	bic.w	r2, r3, #7
 8001f64:	4923      	ldr	r1, [pc, #140]	; (8001ff4 <HAL_RCC_ClockConfig+0x1ec>)
 8001f66:	683b      	ldr	r3, [r7, #0]
 8001f68:	4313      	orrs	r3, r2
 8001f6a:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8001f6c:	4b21      	ldr	r3, [pc, #132]	; (8001ff4 <HAL_RCC_ClockConfig+0x1ec>)
 8001f6e:	681b      	ldr	r3, [r3, #0]
 8001f70:	f003 0307 	and.w	r3, r3, #7
 8001f74:	683a      	ldr	r2, [r7, #0]
 8001f76:	429a      	cmp	r2, r3
 8001f78:	d001      	beq.n	8001f7e <HAL_RCC_ClockConfig+0x176>
    {
      return HAL_ERROR;
 8001f7a:	2301      	movs	r3, #1
 8001f7c:	e036      	b.n	8001fec <HAL_RCC_ClockConfig+0x1e4>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8001f7e:	687b      	ldr	r3, [r7, #4]
 8001f80:	681b      	ldr	r3, [r3, #0]
 8001f82:	f003 0304 	and.w	r3, r3, #4
 8001f86:	2b00      	cmp	r3, #0
 8001f88:	d008      	beq.n	8001f9c <HAL_RCC_ClockConfig+0x194>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8001f8a:	4b1b      	ldr	r3, [pc, #108]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001f8c:	689b      	ldr	r3, [r3, #8]
 8001f8e:	f423 62e0 	bic.w	r2, r3, #1792	; 0x700
 8001f92:	687b      	ldr	r3, [r7, #4]
 8001f94:	68db      	ldr	r3, [r3, #12]
 8001f96:	4918      	ldr	r1, [pc, #96]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001f98:	4313      	orrs	r3, r2
 8001f9a:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8001f9c:	687b      	ldr	r3, [r7, #4]
 8001f9e:	681b      	ldr	r3, [r3, #0]
 8001fa0:	f003 0308 	and.w	r3, r3, #8
 8001fa4:	2b00      	cmp	r3, #0
 8001fa6:	d009      	beq.n	8001fbc <HAL_RCC_ClockConfig+0x1b4>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 8001fa8:	4b13      	ldr	r3, [pc, #76]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001faa:	689b      	ldr	r3, [r3, #8]
 8001fac:	f423 5260 	bic.w	r2, r3, #14336	; 0x3800
 8001fb0:	687b      	ldr	r3, [r7, #4]
 8001fb2:	691b      	ldr	r3, [r3, #16]
 8001fb4:	00db      	lsls	r3, r3, #3
 8001fb6:	4910      	ldr	r1, [pc, #64]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001fb8:	4313      	orrs	r3, r2
 8001fba:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
 8001fbc:	f000 f824 	bl	8002008 <HAL_RCC_GetSysClockFreq>
 8001fc0:	4602      	mov	r2, r0
 8001fc2:	4b0d      	ldr	r3, [pc, #52]	; (8001ff8 <HAL_RCC_ClockConfig+0x1f0>)
 8001fc4:	689b      	ldr	r3, [r3, #8]
 8001fc6:	091b      	lsrs	r3, r3, #4
 8001fc8:	f003 030f 	and.w	r3, r3, #15
 8001fcc:	490b      	ldr	r1, [pc, #44]	; (8001ffc <HAL_RCC_ClockConfig+0x1f4>)
 8001fce:	5ccb      	ldrb	r3, [r1, r3]
 8001fd0:	f003 031f 	and.w	r3, r3, #31
 8001fd4:	fa22 f303 	lsr.w	r3, r2, r3
 8001fd8:	4a09      	ldr	r2, [pc, #36]	; (8002000 <HAL_RCC_ClockConfig+0x1f8>)
 8001fda:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings*/
  status = HAL_InitTick(uwTickPrio);
 8001fdc:	4b09      	ldr	r3, [pc, #36]	; (8002004 <HAL_RCC_ClockConfig+0x1fc>)
 8001fde:	681b      	ldr	r3, [r3, #0]
 8001fe0:	4618      	mov	r0, r3
 8001fe2:	f7fe fcab 	bl	800093c <HAL_InitTick>
 8001fe6:	4603      	mov	r3, r0
 8001fe8:	72fb      	strb	r3, [r7, #11]

  return status;
 8001fea:	7afb      	ldrb	r3, [r7, #11]
}
 8001fec:	4618      	mov	r0, r3
 8001fee:	3710      	adds	r7, #16
 8001ff0:	46bd      	mov	sp, r7
 8001ff2:	bd80      	pop	{r7, pc}
 8001ff4:	40022000 	.word	0x40022000
 8001ff8:	40021000 	.word	0x40021000
 8001ffc:	08006cd8 	.word	0x08006cd8
 8002000:	20000000 	.word	0x20000000
 8002004:	20000004 	.word	0x20000004

08002008 <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8002008:	b480      	push	{r7}
 800200a:	b089      	sub	sp, #36	; 0x24
 800200c:	af00      	add	r7, sp, #0
  uint32_t msirange = 0U, sysclockfreq = 0U;
 800200e:	2300      	movs	r3, #0
 8002010:	61fb      	str	r3, [r7, #28]
 8002012:	2300      	movs	r3, #0
 8002014:	61bb      	str	r3, [r7, #24]
  uint32_t pllvco, pllsource, pllr, pllm;    /* no init needed */
  uint32_t sysclk_source, pll_oscsource;

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 8002016:	4b3e      	ldr	r3, [pc, #248]	; (8002110 <HAL_RCC_GetSysClockFreq+0x108>)
 8002018:	689b      	ldr	r3, [r3, #8]
 800201a:	f003 030c 	and.w	r3, r3, #12
 800201e:	613b      	str	r3, [r7, #16]
  pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
 8002020:	4b3b      	ldr	r3, [pc, #236]	; (8002110 <HAL_RCC_GetSysClockFreq+0x108>)
 8002022:	68db      	ldr	r3, [r3, #12]
 8002024:	f003 0303 	and.w	r3, r3, #3
 8002028:	60fb      	str	r3, [r7, #12]

  if((sysclk_source == RCC_CFGR_SWS_MSI) ||
 800202a:	693b      	ldr	r3, [r7, #16]
 800202c:	2b00      	cmp	r3, #0
 800202e:	d005      	beq.n	800203c <HAL_RCC_GetSysClockFreq+0x34>
 8002030:	693b      	ldr	r3, [r7, #16]
 8002032:	2b0c      	cmp	r3, #12
 8002034:	d121      	bne.n	800207a <HAL_RCC_GetSysClockFreq+0x72>
     ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
 8002036:	68fb      	ldr	r3, [r7, #12]
 8002038:	2b01      	cmp	r3, #1
 800203a:	d11e      	bne.n	800207a <HAL_RCC_GetSysClockFreq+0x72>
  {
    /* MSI or PLL with MSI source used as system clock source */

    /* Get SYSCLK source */
    if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
 800203c:	4b34      	ldr	r3, [pc, #208]	; (8002110 <HAL_RCC_GetSysClockFreq+0x108>)
 800203e:	681b      	ldr	r3, [r3, #0]
 8002040:	f003 0308 	and.w	r3, r3, #8
 8002044:	2b00      	cmp	r3, #0
 8002046:	d107      	bne.n	8002058 <HAL_RCC_GetSysClockFreq+0x50>
    { /* MSISRANGE from RCC_CSR applies */
      msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
 8002048:	4b31      	ldr	r3, [pc, #196]	; (8002110 <HAL_RCC_GetSysClockFreq+0x108>)
 800204a:	f8d3 3094 	ldr.w	r3, [r3, #148]	; 0x94
 800204e:	0a1b      	lsrs	r3, r3, #8
 8002050:	f003 030f 	and.w	r3, r3, #15
 8002054:	61fb      	str	r3, [r7, #28]
 8002056:	e005      	b.n	8002064 <HAL_RCC_GetSysClockFreq+0x5c>
    }
    else
    { /* MSIRANGE from RCC_CR applies */
      msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
 8002058:	4b2d      	ldr	r3, [pc, #180]	; (8002110 <HAL_RCC_GetSysClockFreq+0x108>)
 800205a:	681b      	ldr	r3, [r3, #0]
 800205c:	091b      	lsrs	r3, r3, #4
 800205e:	f003 030f 	and.w	r3, r3, #15
 8002062:	61fb      	str	r3, [r7, #28]
    }
    /*MSI frequency range in HZ*/
    msirange = MSIRangeTable[msirange];
 8002064:	4a2b      	ldr	r2, [pc, #172]	; (8002114 <HAL_RCC_GetSysClockFreq+0x10c>)
 8002066:	69fb      	ldr	r3, [r7, #28]
 8002068:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 800206c:	61fb      	str	r3, [r7, #28]

    if(sysclk_source == RCC_CFGR_SWS_MSI)
 800206e:	693b      	ldr	r3, [r7, #16]
 8002070:	2b00      	cmp	r3, #0
 8002072:	d10d      	bne.n	8002090 <HAL_RCC_GetSysClockFreq+0x88>
    {
      /* MSI used as system clock source */
      sysclockfreq = msirange;
 8002074:	69fb      	ldr	r3, [r7, #28]
 8002076:	61bb      	str	r3, [r7, #24]
    if(sysclk_source == RCC_CFGR_SWS_MSI)
 8002078:	e00a      	b.n	8002090 <HAL_RCC_GetSysClockFreq+0x88>
    }
  }
  else if(sysclk_source == RCC_CFGR_SWS_HSI)
 800207a:	693b      	ldr	r3, [r7, #16]
 800207c:	2b04      	cmp	r3, #4
 800207e:	d102      	bne.n	8002086 <HAL_RCC_GetSysClockFreq+0x7e>
  {
    /* HSI used as system clock source */
    sysclockfreq = HSI_VALUE;
 8002080:	4b25      	ldr	r3, [pc, #148]	; (8002118 <HAL_RCC_GetSysClockFreq+0x110>)
 8002082:	61bb      	str	r3, [r7, #24]
 8002084:	e004      	b.n	8002090 <HAL_RCC_GetSysClockFreq+0x88>
  }
  else if(sysclk_source == RCC_CFGR_SWS_HSE)
 8002086:	693b      	ldr	r3, [r7, #16]
 8002088:	2b08      	cmp	r3, #8
 800208a:	d101      	bne.n	8002090 <HAL_RCC_GetSysClockFreq+0x88>
  {
    /* HSE used as system clock source */
    sysclockfreq = HSE_VALUE;
 800208c:	4b23      	ldr	r3, [pc, #140]	; (800211c <HAL_RCC_GetSysClockFreq+0x114>)
 800208e:	61bb      	str	r3, [r7, #24]
  else
  {
    /* unexpected case: sysclockfreq at 0 */
  }

  if(sysclk_source == RCC_CFGR_SWS_PLL)
 8002090:	693b      	ldr	r3, [r7, #16]
 8002092:	2b0c      	cmp	r3, #12
 8002094:	d134      	bne.n	8002100 <HAL_RCC_GetSysClockFreq+0xf8>
    /* PLL used as system clock  source */

    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
    SYSCLK = PLL_VCO / PLLR
    */
    pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
 8002096:	4b1e      	ldr	r3, [pc, #120]	; (8002110 <HAL_RCC_GetSysClockFreq+0x108>)
 8002098:	68db      	ldr	r3, [r3, #12]
 800209a:	f003 0303 	and.w	r3, r3, #3
 800209e:	60bb      	str	r3, [r7, #8]

    switch (pllsource)
 80020a0:	68bb      	ldr	r3, [r7, #8]
 80020a2:	2b02      	cmp	r3, #2
 80020a4:	d003      	beq.n	80020ae <HAL_RCC_GetSysClockFreq+0xa6>
 80020a6:	68bb      	ldr	r3, [r7, #8]
 80020a8:	2b03      	cmp	r3, #3
 80020aa:	d003      	beq.n	80020b4 <HAL_RCC_GetSysClockFreq+0xac>
 80020ac:	e005      	b.n	80020ba <HAL_RCC_GetSysClockFreq+0xb2>
    {
    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
      pllvco = HSI_VALUE;
 80020ae:	4b1a      	ldr	r3, [pc, #104]	; (8002118 <HAL_RCC_GetSysClockFreq+0x110>)
 80020b0:	617b      	str	r3, [r7, #20]
      break;
 80020b2:	e005      	b.n	80020c0 <HAL_RCC_GetSysClockFreq+0xb8>

    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
      pllvco = HSE_VALUE;
 80020b4:	4b19      	ldr	r3, [pc, #100]	; (800211c <HAL_RCC_GetSysClockFreq+0x114>)
 80020b6:	617b      	str	r3, [r7, #20]
      break;
 80020b8:	e002      	b.n	80020c0 <HAL_RCC_GetSysClockFreq+0xb8>

    case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
    default:
      pllvco = msirange;
 80020ba:	69fb      	ldr	r3, [r7, #28]
 80020bc:	617b      	str	r3, [r7, #20]
      break;
 80020be:	bf00      	nop
    }
    pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
 80020c0:	4b13      	ldr	r3, [pc, #76]	; (8002110 <HAL_RCC_GetSysClockFreq+0x108>)
 80020c2:	68db      	ldr	r3, [r3, #12]
 80020c4:	091b      	lsrs	r3, r3, #4
 80020c6:	f003 0307 	and.w	r3, r3, #7
 80020ca:	3301      	adds	r3, #1
 80020cc:	607b      	str	r3, [r7, #4]
    pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
 80020ce:	4b10      	ldr	r3, [pc, #64]	; (8002110 <HAL_RCC_GetSysClockFreq+0x108>)
 80020d0:	68db      	ldr	r3, [r3, #12]
 80020d2:	0a1b      	lsrs	r3, r3, #8
 80020d4:	f003 037f 	and.w	r3, r3, #127	; 0x7f
 80020d8:	697a      	ldr	r2, [r7, #20]
 80020da:	fb03 f202 	mul.w	r2, r3, r2
 80020de:	687b      	ldr	r3, [r7, #4]
 80020e0:	fbb2 f3f3 	udiv	r3, r2, r3
 80020e4:	617b      	str	r3, [r7, #20]
    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
 80020e6:	4b0a      	ldr	r3, [pc, #40]	; (8002110 <HAL_RCC_GetSysClockFreq+0x108>)
 80020e8:	68db      	ldr	r3, [r3, #12]
 80020ea:	0e5b      	lsrs	r3, r3, #25
 80020ec:	f003 0303 	and.w	r3, r3, #3
 80020f0:	3301      	adds	r3, #1
 80020f2:	005b      	lsls	r3, r3, #1
 80020f4:	603b      	str	r3, [r7, #0]
    sysclockfreq = pllvco / pllr;
 80020f6:	697a      	ldr	r2, [r7, #20]
 80020f8:	683b      	ldr	r3, [r7, #0]
 80020fa:	fbb2 f3f3 	udiv	r3, r2, r3
 80020fe:	61bb      	str	r3, [r7, #24]
  }

  return sysclockfreq;
 8002100:	69bb      	ldr	r3, [r7, #24]
}
 8002102:	4618      	mov	r0, r3
 8002104:	3724      	adds	r7, #36	; 0x24
 8002106:	46bd      	mov	sp, r7
 8002108:	f85d 7b04 	ldr.w	r7, [sp], #4
 800210c:	4770      	bx	lr
 800210e:	bf00      	nop
 8002110:	40021000 	.word	0x40021000
 8002114:	08006cf0 	.word	0x08006cf0
 8002118:	00f42400 	.word	0x00f42400
 800211c:	007a1200 	.word	0x007a1200

08002120 <HAL_RCC_GetHCLKFreq>:
  *
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
  * @retval HCLK frequency in Hz
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 8002120:	b480      	push	{r7}
 8002122:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 8002124:	4b03      	ldr	r3, [pc, #12]	; (8002134 <HAL_RCC_GetHCLKFreq+0x14>)
 8002126:	681b      	ldr	r3, [r3, #0]
}
 8002128:	4618      	mov	r0, r3
 800212a:	46bd      	mov	sp, r7
 800212c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002130:	4770      	bx	lr
 8002132:	bf00      	nop
 8002134:	20000000 	.word	0x20000000

08002138 <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency in Hz
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 8002138:	b580      	push	{r7, lr}
 800213a:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
 800213c:	f7ff fff0 	bl	8002120 <HAL_RCC_GetHCLKFreq>
 8002140:	4602      	mov	r2, r0
 8002142:	4b06      	ldr	r3, [pc, #24]	; (800215c <HAL_RCC_GetPCLK1Freq+0x24>)
 8002144:	689b      	ldr	r3, [r3, #8]
 8002146:	0a1b      	lsrs	r3, r3, #8
 8002148:	f003 0307 	and.w	r3, r3, #7
 800214c:	4904      	ldr	r1, [pc, #16]	; (8002160 <HAL_RCC_GetPCLK1Freq+0x28>)
 800214e:	5ccb      	ldrb	r3, [r1, r3]
 8002150:	f003 031f 	and.w	r3, r3, #31
 8002154:	fa22 f303 	lsr.w	r3, r2, r3
}
 8002158:	4618      	mov	r0, r3
 800215a:	bd80      	pop	{r7, pc}
 800215c:	40021000 	.word	0x40021000
 8002160:	08006ce8 	.word	0x08006ce8

08002164 <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency in Hz
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 8002164:	b580      	push	{r7, lr}
 8002166:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
 8002168:	f7ff ffda 	bl	8002120 <HAL_RCC_GetHCLKFreq>
 800216c:	4602      	mov	r2, r0
 800216e:	4b06      	ldr	r3, [pc, #24]	; (8002188 <HAL_RCC_GetPCLK2Freq+0x24>)
 8002170:	689b      	ldr	r3, [r3, #8]
 8002172:	0adb      	lsrs	r3, r3, #11
 8002174:	f003 0307 	and.w	r3, r3, #7
 8002178:	4904      	ldr	r1, [pc, #16]	; (800218c <HAL_RCC_GetPCLK2Freq+0x28>)
 800217a:	5ccb      	ldrb	r3, [r1, r3]
 800217c:	f003 031f 	and.w	r3, r3, #31
 8002180:	fa22 f303 	lsr.w	r3, r2, r3
}
 8002184:	4618      	mov	r0, r3
 8002186:	bd80      	pop	{r7, pc}
 8002188:	40021000 	.word	0x40021000
 800218c:	08006ce8 	.word	0x08006ce8

08002190 <HAL_RCC_GetClockConfig>:
  *         will be configured.
  * @param  pFLatency  Pointer on the Flash Latency.
  * @retval None
  */
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
{
 8002190:	b480      	push	{r7}
 8002192:	b083      	sub	sp, #12
 8002194:	af00      	add	r7, sp, #0
 8002196:	6078      	str	r0, [r7, #4]
 8002198:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(RCC_ClkInitStruct != (void  *)NULL);
  assert_param(pFLatency != (void *)NULL);

  /* Set all possible values for the Clock type parameter --------------------*/
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
 800219a:	687b      	ldr	r3, [r7, #4]
 800219c:	220f      	movs	r2, #15
 800219e:	601a      	str	r2, [r3, #0]

  /* Get the SYSCLK configuration --------------------------------------------*/
  RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);
 80021a0:	4b12      	ldr	r3, [pc, #72]	; (80021ec <HAL_RCC_GetClockConfig+0x5c>)
 80021a2:	689b      	ldr	r3, [r3, #8]
 80021a4:	f003 0203 	and.w	r2, r3, #3
 80021a8:	687b      	ldr	r3, [r7, #4]
 80021aa:	605a      	str	r2, [r3, #4]

  /* Get the HCLK configuration ----------------------------------------------*/
  RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);
 80021ac:	4b0f      	ldr	r3, [pc, #60]	; (80021ec <HAL_RCC_GetClockConfig+0x5c>)
 80021ae:	689b      	ldr	r3, [r3, #8]
 80021b0:	f003 02f0 	and.w	r2, r3, #240	; 0xf0
 80021b4:	687b      	ldr	r3, [r7, #4]
 80021b6:	609a      	str	r2, [r3, #8]

  /* Get the APB1 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);
 80021b8:	4b0c      	ldr	r3, [pc, #48]	; (80021ec <HAL_RCC_GetClockConfig+0x5c>)
 80021ba:	689b      	ldr	r3, [r3, #8]
 80021bc:	f403 62e0 	and.w	r2, r3, #1792	; 0x700
 80021c0:	687b      	ldr	r3, [r7, #4]
 80021c2:	60da      	str	r2, [r3, #12]

  /* Get the APB2 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);
 80021c4:	4b09      	ldr	r3, [pc, #36]	; (80021ec <HAL_RCC_GetClockConfig+0x5c>)
 80021c6:	689b      	ldr	r3, [r3, #8]
 80021c8:	08db      	lsrs	r3, r3, #3
 80021ca:	f403 62e0 	and.w	r2, r3, #1792	; 0x700
 80021ce:	687b      	ldr	r3, [r7, #4]
 80021d0:	611a      	str	r2, [r3, #16]

  /* Get the Flash Wait State (Latency) configuration ------------------------*/
  *pFLatency = __HAL_FLASH_GET_LATENCY();
 80021d2:	4b07      	ldr	r3, [pc, #28]	; (80021f0 <HAL_RCC_GetClockConfig+0x60>)
 80021d4:	681b      	ldr	r3, [r3, #0]
 80021d6:	f003 0207 	and.w	r2, r3, #7
 80021da:	683b      	ldr	r3, [r7, #0]
 80021dc:	601a      	str	r2, [r3, #0]
}
 80021de:	bf00      	nop
 80021e0:	370c      	adds	r7, #12
 80021e2:	46bd      	mov	sp, r7
 80021e4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80021e8:	4770      	bx	lr
 80021ea:	bf00      	nop
 80021ec:	40021000 	.word	0x40021000
 80021f0:	40022000 	.word	0x40022000

080021f4 <RCC_SetFlashLatencyFromMSIRange>:
            voltage range.
  * @param  msirange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
  * @retval HAL status
  */
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
{
 80021f4:	b580      	push	{r7, lr}
 80021f6:	b086      	sub	sp, #24
 80021f8:	af00      	add	r7, sp, #0
 80021fa:	6078      	str	r0, [r7, #4]
  uint32_t vos;
  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
 80021fc:	2300      	movs	r3, #0
 80021fe:	613b      	str	r3, [r7, #16]

  if(__HAL_RCC_PWR_IS_CLK_ENABLED())
 8002200:	4b2a      	ldr	r3, [pc, #168]	; (80022ac <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8002202:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8002204:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8002208:	2b00      	cmp	r3, #0
 800220a:	d003      	beq.n	8002214 <RCC_SetFlashLatencyFromMSIRange+0x20>
  {
    vos = HAL_PWREx_GetVoltageRange();
 800220c:	f7ff f9bc 	bl	8001588 <HAL_PWREx_GetVoltageRange>
 8002210:	6178      	str	r0, [r7, #20]
 8002212:	e014      	b.n	800223e <RCC_SetFlashLatencyFromMSIRange+0x4a>
  }
  else
  {
    __HAL_RCC_PWR_CLK_ENABLE();
 8002214:	4b25      	ldr	r3, [pc, #148]	; (80022ac <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8002216:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8002218:	4a24      	ldr	r2, [pc, #144]	; (80022ac <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800221a:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 800221e:	6593      	str	r3, [r2, #88]	; 0x58
 8002220:	4b22      	ldr	r3, [pc, #136]	; (80022ac <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8002222:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8002224:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8002228:	60fb      	str	r3, [r7, #12]
 800222a:	68fb      	ldr	r3, [r7, #12]
    vos = HAL_PWREx_GetVoltageRange();
 800222c:	f7ff f9ac 	bl	8001588 <HAL_PWREx_GetVoltageRange>
 8002230:	6178      	str	r0, [r7, #20]
    __HAL_RCC_PWR_CLK_DISABLE();
 8002232:	4b1e      	ldr	r3, [pc, #120]	; (80022ac <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8002234:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8002236:	4a1d      	ldr	r2, [pc, #116]	; (80022ac <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8002238:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 800223c:	6593      	str	r3, [r2, #88]	; 0x58
  }

  if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
 800223e:	697b      	ldr	r3, [r7, #20]
 8002240:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 8002244:	d10b      	bne.n	800225e <RCC_SetFlashLatencyFromMSIRange+0x6a>
  {
    if(msirange > RCC_MSIRANGE_8)
 8002246:	687b      	ldr	r3, [r7, #4]
 8002248:	2b80      	cmp	r3, #128	; 0x80
 800224a:	d919      	bls.n	8002280 <RCC_SetFlashLatencyFromMSIRange+0x8c>
    {
      /* MSI > 16Mhz */
      if(msirange > RCC_MSIRANGE_10)
 800224c:	687b      	ldr	r3, [r7, #4]
 800224e:	2ba0      	cmp	r3, #160	; 0xa0
 8002250:	d902      	bls.n	8002258 <RCC_SetFlashLatencyFromMSIRange+0x64>
      {
        /* MSI 48Mhz */
        latency = FLASH_LATENCY_2; /* 2WS */
 8002252:	2302      	movs	r3, #2
 8002254:	613b      	str	r3, [r7, #16]
 8002256:	e013      	b.n	8002280 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      }
      else
      {
        /* MSI 24Mhz or 32Mhz */
        latency = FLASH_LATENCY_1; /* 1WS */
 8002258:	2301      	movs	r3, #1
 800225a:	613b      	str	r3, [r7, #16]
 800225c:	e010      	b.n	8002280 <RCC_SetFlashLatencyFromMSIRange+0x8c>
        latency = FLASH_LATENCY_1; /* 1WS */
      }
      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
    }
#else
    if(msirange > RCC_MSIRANGE_8)
 800225e:	687b      	ldr	r3, [r7, #4]
 8002260:	2b80      	cmp	r3, #128	; 0x80
 8002262:	d902      	bls.n	800226a <RCC_SetFlashLatencyFromMSIRange+0x76>
    {
      /* MSI > 16Mhz */
      latency = FLASH_LATENCY_3; /* 3WS */
 8002264:	2303      	movs	r3, #3
 8002266:	613b      	str	r3, [r7, #16]
 8002268:	e00a      	b.n	8002280 <RCC_SetFlashLatencyFromMSIRange+0x8c>
    }
    else
    {
      if(msirange == RCC_MSIRANGE_8)
 800226a:	687b      	ldr	r3, [r7, #4]
 800226c:	2b80      	cmp	r3, #128	; 0x80
 800226e:	d102      	bne.n	8002276 <RCC_SetFlashLatencyFromMSIRange+0x82>
      {
        /* MSI 16Mhz */
        latency = FLASH_LATENCY_2; /* 2WS */
 8002270:	2302      	movs	r3, #2
 8002272:	613b      	str	r3, [r7, #16]
 8002274:	e004      	b.n	8002280 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      }
      else if(msirange == RCC_MSIRANGE_7)
 8002276:	687b      	ldr	r3, [r7, #4]
 8002278:	2b70      	cmp	r3, #112	; 0x70
 800227a:	d101      	bne.n	8002280 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      {
        /* MSI 8Mhz */
        latency = FLASH_LATENCY_1; /* 1WS */
 800227c:	2301      	movs	r3, #1
 800227e:	613b      	str	r3, [r7, #16]
      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
    }
#endif
  }

  __HAL_FLASH_SET_LATENCY(latency);
 8002280:	4b0b      	ldr	r3, [pc, #44]	; (80022b0 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 8002282:	681b      	ldr	r3, [r3, #0]
 8002284:	f023 0207 	bic.w	r2, r3, #7
 8002288:	4909      	ldr	r1, [pc, #36]	; (80022b0 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 800228a:	693b      	ldr	r3, [r7, #16]
 800228c:	4313      	orrs	r3, r2
 800228e:	600b      	str	r3, [r1, #0]

  /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
  if(__HAL_FLASH_GET_LATENCY() != latency)
 8002290:	4b07      	ldr	r3, [pc, #28]	; (80022b0 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 8002292:	681b      	ldr	r3, [r3, #0]
 8002294:	f003 0307 	and.w	r3, r3, #7
 8002298:	693a      	ldr	r2, [r7, #16]
 800229a:	429a      	cmp	r2, r3
 800229c:	d001      	beq.n	80022a2 <RCC_SetFlashLatencyFromMSIRange+0xae>
  {
    return HAL_ERROR;
 800229e:	2301      	movs	r3, #1
 80022a0:	e000      	b.n	80022a4 <RCC_SetFlashLatencyFromMSIRange+0xb0>
  }

  return HAL_OK;
 80022a2:	2300      	movs	r3, #0
}
 80022a4:	4618      	mov	r0, r3
 80022a6:	3718      	adds	r7, #24
 80022a8:	46bd      	mov	sp, r7
 80022aa:	bd80      	pop	{r7, pc}
 80022ac:	40021000 	.word	0x40021000
 80022b0:	40022000 	.word	0x40022000

080022b4 <HAL_RCCEx_PeriphCLKConfig>:
  *         the RTC clock source: in this case the access to Backup domain is enabled.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 80022b4:	b580      	push	{r7, lr}
 80022b6:	b086      	sub	sp, #24
 80022b8:	af00      	add	r7, sp, #0
 80022ba:	6078      	str	r0, [r7, #4]
  uint32_t tmpregister, tickstart;     /* no init needed */
  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
 80022bc:	2300      	movs	r3, #0
 80022be:	74fb      	strb	r3, [r7, #19]
  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
 80022c0:	2300      	movs	r3, #0
 80022c2:	74bb      	strb	r3, [r7, #18]
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

#if defined(SAI1)

  /*-------------------------- SAI1 clock source configuration ---------------------*/
  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
 80022c4:	687b      	ldr	r3, [r7, #4]
 80022c6:	681b      	ldr	r3, [r3, #0]
 80022c8:	f403 6300 	and.w	r3, r3, #2048	; 0x800
 80022cc:	2b00      	cmp	r3, #0
 80022ce:	d041      	beq.n	8002354 <HAL_RCCEx_PeriphCLKConfig+0xa0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));

    switch(PeriphClkInit->Sai1ClockSelection)
 80022d0:	687b      	ldr	r3, [r7, #4]
 80022d2:	6e5b      	ldr	r3, [r3, #100]	; 0x64
 80022d4:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
 80022d8:	d02a      	beq.n	8002330 <HAL_RCCEx_PeriphCLKConfig+0x7c>
 80022da:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
 80022de:	d824      	bhi.n	800232a <HAL_RCCEx_PeriphCLKConfig+0x76>
 80022e0:	f5b3 0f00 	cmp.w	r3, #8388608	; 0x800000
 80022e4:	d008      	beq.n	80022f8 <HAL_RCCEx_PeriphCLKConfig+0x44>
 80022e6:	f5b3 0f00 	cmp.w	r3, #8388608	; 0x800000
 80022ea:	d81e      	bhi.n	800232a <HAL_RCCEx_PeriphCLKConfig+0x76>
 80022ec:	2b00      	cmp	r3, #0
 80022ee:	d00a      	beq.n	8002306 <HAL_RCCEx_PeriphCLKConfig+0x52>
 80022f0:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
 80022f4:	d010      	beq.n	8002318 <HAL_RCCEx_PeriphCLKConfig+0x64>
 80022f6:	e018      	b.n	800232a <HAL_RCCEx_PeriphCLKConfig+0x76>
    {
    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
      /* Enable SAI Clock output generated from System PLL . */
#if defined(RCC_PLLSAI2_SUPPORT)
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
 80022f8:	4b86      	ldr	r3, [pc, #536]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80022fa:	68db      	ldr	r3, [r3, #12]
 80022fc:	4a85      	ldr	r2, [pc, #532]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80022fe:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8002302:	60d3      	str	r3, [r2, #12]
#else
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
#endif /* RCC_PLLSAI2_SUPPORT */
      /* SAI1 clock source config set later after clock selection check */
      break;
 8002304:	e015      	b.n	8002332 <HAL_RCCEx_PeriphCLKConfig+0x7e>

    case RCC_SAI1CLKSOURCE_PLLSAI1:  /* PLLSAI1 is used as clock source for SAI1*/
      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
 8002306:	687b      	ldr	r3, [r7, #4]
 8002308:	3304      	adds	r3, #4
 800230a:	2100      	movs	r1, #0
 800230c:	4618      	mov	r0, r3
 800230e:	f000 facb 	bl	80028a8 <RCCEx_PLLSAI1_Config>
 8002312:	4603      	mov	r3, r0
 8002314:	74fb      	strb	r3, [r7, #19]
      /* SAI1 clock source config set later after clock selection check */
      break;
 8002316:	e00c      	b.n	8002332 <HAL_RCCEx_PeriphCLKConfig+0x7e>

#if defined(RCC_PLLSAI2_SUPPORT)

    case RCC_SAI1CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI1*/
      /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
 8002318:	687b      	ldr	r3, [r7, #4]
 800231a:	3320      	adds	r3, #32
 800231c:	2100      	movs	r1, #0
 800231e:	4618      	mov	r0, r3
 8002320:	f000 fbb6 	bl	8002a90 <RCCEx_PLLSAI2_Config>
 8002324:	4603      	mov	r3, r0
 8002326:	74fb      	strb	r3, [r7, #19]
      /* SAI1 clock source config set later after clock selection check */
      break;
 8002328:	e003      	b.n	8002332 <HAL_RCCEx_PeriphCLKConfig+0x7e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
      /* SAI1 clock source config set later after clock selection check */
      break;

    default:
      ret = HAL_ERROR;
 800232a:	2301      	movs	r3, #1
 800232c:	74fb      	strb	r3, [r7, #19]
      break;
 800232e:	e000      	b.n	8002332 <HAL_RCCEx_PeriphCLKConfig+0x7e>
      break;
 8002330:	bf00      	nop
    }

    if(ret == HAL_OK)
 8002332:	7cfb      	ldrb	r3, [r7, #19]
 8002334:	2b00      	cmp	r3, #0
 8002336:	d10b      	bne.n	8002350 <HAL_RCCEx_PeriphCLKConfig+0x9c>
    {
      /* Set the source of SAI1 clock*/
      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
 8002338:	4b76      	ldr	r3, [pc, #472]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800233a:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 800233e:	f423 0240 	bic.w	r2, r3, #12582912	; 0xc00000
 8002342:	687b      	ldr	r3, [r7, #4]
 8002344:	6e5b      	ldr	r3, [r3, #100]	; 0x64
 8002346:	4973      	ldr	r1, [pc, #460]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8002348:	4313      	orrs	r3, r2
 800234a:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
 800234e:	e001      	b.n	8002354 <HAL_RCCEx_PeriphCLKConfig+0xa0>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8002350:	7cfb      	ldrb	r3, [r7, #19]
 8002352:	74bb      	strb	r3, [r7, #18]
#endif /* SAI1 */

#if defined(SAI2)

  /*-------------------------- SAI2 clock source configuration ---------------------*/
  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
 8002354:	687b      	ldr	r3, [r7, #4]
 8002356:	681b      	ldr	r3, [r3, #0]
 8002358:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
 800235c:	2b00      	cmp	r3, #0
 800235e:	d041      	beq.n	80023e4 <HAL_RCCEx_PeriphCLKConfig+0x130>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));

    switch(PeriphClkInit->Sai2ClockSelection)
 8002360:	687b      	ldr	r3, [r7, #4]
 8002362:	6e9b      	ldr	r3, [r3, #104]	; 0x68
 8002364:	f1b3 7f40 	cmp.w	r3, #50331648	; 0x3000000
 8002368:	d02a      	beq.n	80023c0 <HAL_RCCEx_PeriphCLKConfig+0x10c>
 800236a:	f1b3 7f40 	cmp.w	r3, #50331648	; 0x3000000
 800236e:	d824      	bhi.n	80023ba <HAL_RCCEx_PeriphCLKConfig+0x106>
 8002370:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
 8002374:	d008      	beq.n	8002388 <HAL_RCCEx_PeriphCLKConfig+0xd4>
 8002376:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
 800237a:	d81e      	bhi.n	80023ba <HAL_RCCEx_PeriphCLKConfig+0x106>
 800237c:	2b00      	cmp	r3, #0
 800237e:	d00a      	beq.n	8002396 <HAL_RCCEx_PeriphCLKConfig+0xe2>
 8002380:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
 8002384:	d010      	beq.n	80023a8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
 8002386:	e018      	b.n	80023ba <HAL_RCCEx_PeriphCLKConfig+0x106>
    {
    case RCC_SAI2CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
      /* Enable SAI Clock output generated from System PLL . */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
 8002388:	4b62      	ldr	r3, [pc, #392]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800238a:	68db      	ldr	r3, [r3, #12]
 800238c:	4a61      	ldr	r2, [pc, #388]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800238e:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8002392:	60d3      	str	r3, [r2, #12]
      /* SAI2 clock source config set later after clock selection check */
      break;
 8002394:	e015      	b.n	80023c2 <HAL_RCCEx_PeriphCLKConfig+0x10e>

    case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
 8002396:	687b      	ldr	r3, [r7, #4]
 8002398:	3304      	adds	r3, #4
 800239a:	2100      	movs	r1, #0
 800239c:	4618      	mov	r0, r3
 800239e:	f000 fa83 	bl	80028a8 <RCCEx_PLLSAI1_Config>
 80023a2:	4603      	mov	r3, r0
 80023a4:	74fb      	strb	r3, [r7, #19]
      /* SAI2 clock source config set later after clock selection check */
      break;
 80023a6:	e00c      	b.n	80023c2 <HAL_RCCEx_PeriphCLKConfig+0x10e>

    case RCC_SAI2CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI2*/
      /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
 80023a8:	687b      	ldr	r3, [r7, #4]
 80023aa:	3320      	adds	r3, #32
 80023ac:	2100      	movs	r1, #0
 80023ae:	4618      	mov	r0, r3
 80023b0:	f000 fb6e 	bl	8002a90 <RCCEx_PLLSAI2_Config>
 80023b4:	4603      	mov	r3, r0
 80023b6:	74fb      	strb	r3, [r7, #19]
      /* SAI2 clock source config set later after clock selection check */
      break;
 80023b8:	e003      	b.n	80023c2 <HAL_RCCEx_PeriphCLKConfig+0x10e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
      /* SAI2 clock source config set later after clock selection check */
      break;

    default:
      ret = HAL_ERROR;
 80023ba:	2301      	movs	r3, #1
 80023bc:	74fb      	strb	r3, [r7, #19]
      break;
 80023be:	e000      	b.n	80023c2 <HAL_RCCEx_PeriphCLKConfig+0x10e>
      break;
 80023c0:	bf00      	nop
    }

    if(ret == HAL_OK)
 80023c2:	7cfb      	ldrb	r3, [r7, #19]
 80023c4:	2b00      	cmp	r3, #0
 80023c6:	d10b      	bne.n	80023e0 <HAL_RCCEx_PeriphCLKConfig+0x12c>
    {
      /* Set the source of SAI2 clock*/
      __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
 80023c8:	4b52      	ldr	r3, [pc, #328]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80023ca:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 80023ce:	f023 7240 	bic.w	r2, r3, #50331648	; 0x3000000
 80023d2:	687b      	ldr	r3, [r7, #4]
 80023d4:	6e9b      	ldr	r3, [r3, #104]	; 0x68
 80023d6:	494f      	ldr	r1, [pc, #316]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80023d8:	4313      	orrs	r3, r2
 80023da:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
 80023de:	e001      	b.n	80023e4 <HAL_RCCEx_PeriphCLKConfig+0x130>
    }
    else
    {
      /* set overall return value */
      status = ret;
 80023e0:	7cfb      	ldrb	r3, [r7, #19]
 80023e2:	74bb      	strb	r3, [r7, #18]
    }
  }
#endif /* SAI2 */

  /*-------------------------- RTC clock source configuration ----------------------*/
  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 80023e4:	687b      	ldr	r3, [r7, #4]
 80023e6:	681b      	ldr	r3, [r3, #0]
 80023e8:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80023ec:	2b00      	cmp	r3, #0
 80023ee:	f000 80a0 	beq.w	8002532 <HAL_RCCEx_PeriphCLKConfig+0x27e>
  {
    FlagStatus       pwrclkchanged = RESET;
 80023f2:	2300      	movs	r3, #0
 80023f4:	747b      	strb	r3, [r7, #17]

    /* Check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));

    /* Enable Power Clock */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
 80023f6:	4b47      	ldr	r3, [pc, #284]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80023f8:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 80023fa:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80023fe:	2b00      	cmp	r3, #0
 8002400:	d101      	bne.n	8002406 <HAL_RCCEx_PeriphCLKConfig+0x152>
 8002402:	2301      	movs	r3, #1
 8002404:	e000      	b.n	8002408 <HAL_RCCEx_PeriphCLKConfig+0x154>
 8002406:	2300      	movs	r3, #0
 8002408:	2b00      	cmp	r3, #0
 800240a:	d00d      	beq.n	8002428 <HAL_RCCEx_PeriphCLKConfig+0x174>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 800240c:	4b41      	ldr	r3, [pc, #260]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800240e:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 8002410:	4a40      	ldr	r2, [pc, #256]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8002412:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8002416:	6593      	str	r3, [r2, #88]	; 0x58
 8002418:	4b3e      	ldr	r3, [pc, #248]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800241a:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 800241c:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8002420:	60bb      	str	r3, [r7, #8]
 8002422:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8002424:	2301      	movs	r3, #1
 8002426:	747b      	strb	r3, [r7, #17]
    }

    /* Enable write access to Backup domain */
    SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8002428:	4b3b      	ldr	r3, [pc, #236]	; (8002518 <HAL_RCCEx_PeriphCLKConfig+0x264>)
 800242a:	681b      	ldr	r3, [r3, #0]
 800242c:	4a3a      	ldr	r2, [pc, #232]	; (8002518 <HAL_RCCEx_PeriphCLKConfig+0x264>)
 800242e:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8002432:	6013      	str	r3, [r2, #0]

    /* Wait for Backup domain Write protection disable */
    tickstart = HAL_GetTick();
 8002434:	f7fe fc66 	bl	8000d04 <HAL_GetTick>
 8002438:	60f8      	str	r0, [r7, #12]

    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
 800243a:	e009      	b.n	8002450 <HAL_RCCEx_PeriphCLKConfig+0x19c>
    {
      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 800243c:	f7fe fc62 	bl	8000d04 <HAL_GetTick>
 8002440:	4602      	mov	r2, r0
 8002442:	68fb      	ldr	r3, [r7, #12]
 8002444:	1ad3      	subs	r3, r2, r3
 8002446:	2b02      	cmp	r3, #2
 8002448:	d902      	bls.n	8002450 <HAL_RCCEx_PeriphCLKConfig+0x19c>
      {
        ret = HAL_TIMEOUT;
 800244a:	2303      	movs	r3, #3
 800244c:	74fb      	strb	r3, [r7, #19]
        break;
 800244e:	e005      	b.n	800245c <HAL_RCCEx_PeriphCLKConfig+0x1a8>
    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
 8002450:	4b31      	ldr	r3, [pc, #196]	; (8002518 <HAL_RCCEx_PeriphCLKConfig+0x264>)
 8002452:	681b      	ldr	r3, [r3, #0]
 8002454:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8002458:	2b00      	cmp	r3, #0
 800245a:	d0ef      	beq.n	800243c <HAL_RCCEx_PeriphCLKConfig+0x188>
      }
    }

    if(ret == HAL_OK)
 800245c:	7cfb      	ldrb	r3, [r7, #19]
 800245e:	2b00      	cmp	r3, #0
 8002460:	d15c      	bne.n	800251c <HAL_RCCEx_PeriphCLKConfig+0x268>
    {
      /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
      tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
 8002462:	4b2c      	ldr	r3, [pc, #176]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8002464:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8002468:	f403 7340 	and.w	r3, r3, #768	; 0x300
 800246c:	617b      	str	r3, [r7, #20]

      if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
 800246e:	697b      	ldr	r3, [r7, #20]
 8002470:	2b00      	cmp	r3, #0
 8002472:	d01f      	beq.n	80024b4 <HAL_RCCEx_PeriphCLKConfig+0x200>
 8002474:	687b      	ldr	r3, [r7, #4]
 8002476:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
 800247a:	697a      	ldr	r2, [r7, #20]
 800247c:	429a      	cmp	r2, r3
 800247e:	d019      	beq.n	80024b4 <HAL_RCCEx_PeriphCLKConfig+0x200>
      {
        /* Store the content of BDCR register before the reset of Backup Domain */
        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
 8002480:	4b24      	ldr	r3, [pc, #144]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8002482:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8002486:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 800248a:	617b      	str	r3, [r7, #20]
        /* RTC Clock selection can be changed only if the Backup Domain is reset */
        __HAL_RCC_BACKUPRESET_FORCE();
 800248c:	4b21      	ldr	r3, [pc, #132]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800248e:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 8002492:	4a20      	ldr	r2, [pc, #128]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8002494:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8002498:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
        __HAL_RCC_BACKUPRESET_RELEASE();
 800249c:	4b1d      	ldr	r3, [pc, #116]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 800249e:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 80024a2:	4a1c      	ldr	r2, [pc, #112]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80024a4:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 80024a8:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
        /* Restore the Content of BDCR register */
        RCC->BDCR = tmpregister;
 80024ac:	4a19      	ldr	r2, [pc, #100]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80024ae:	697b      	ldr	r3, [r7, #20]
 80024b0:	f8c2 3090 	str.w	r3, [r2, #144]	; 0x90
      }

      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
 80024b4:	697b      	ldr	r3, [r7, #20]
 80024b6:	f003 0301 	and.w	r3, r3, #1
 80024ba:	2b00      	cmp	r3, #0
 80024bc:	d016      	beq.n	80024ec <HAL_RCCEx_PeriphCLKConfig+0x238>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80024be:	f7fe fc21 	bl	8000d04 <HAL_GetTick>
 80024c2:	60f8      	str	r0, [r7, #12]

        /* Wait till LSE is ready */
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 80024c4:	e00b      	b.n	80024de <HAL_RCCEx_PeriphCLKConfig+0x22a>
        {
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80024c6:	f7fe fc1d 	bl	8000d04 <HAL_GetTick>
 80024ca:	4602      	mov	r2, r0
 80024cc:	68fb      	ldr	r3, [r7, #12]
 80024ce:	1ad3      	subs	r3, r2, r3
 80024d0:	f241 3288 	movw	r2, #5000	; 0x1388
 80024d4:	4293      	cmp	r3, r2
 80024d6:	d902      	bls.n	80024de <HAL_RCCEx_PeriphCLKConfig+0x22a>
          {
            ret = HAL_TIMEOUT;
 80024d8:	2303      	movs	r3, #3
 80024da:	74fb      	strb	r3, [r7, #19]
            break;
 80024dc:	e006      	b.n	80024ec <HAL_RCCEx_PeriphCLKConfig+0x238>
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 80024de:	4b0d      	ldr	r3, [pc, #52]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80024e0:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 80024e4:	f003 0302 	and.w	r3, r3, #2
 80024e8:	2b00      	cmp	r3, #0
 80024ea:	d0ec      	beq.n	80024c6 <HAL_RCCEx_PeriphCLKConfig+0x212>
          }
        }
      }

      if(ret == HAL_OK)
 80024ec:	7cfb      	ldrb	r3, [r7, #19]
 80024ee:	2b00      	cmp	r3, #0
 80024f0:	d10c      	bne.n	800250c <HAL_RCCEx_PeriphCLKConfig+0x258>
      {
        /* Apply new RTC clock source selection */
        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 80024f2:	4b08      	ldr	r3, [pc, #32]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 80024f4:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
 80024f8:	f423 7240 	bic.w	r2, r3, #768	; 0x300
 80024fc:	687b      	ldr	r3, [r7, #4]
 80024fe:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
 8002502:	4904      	ldr	r1, [pc, #16]	; (8002514 <HAL_RCCEx_PeriphCLKConfig+0x260>)
 8002504:	4313      	orrs	r3, r2
 8002506:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
 800250a:	e009      	b.n	8002520 <HAL_RCCEx_PeriphCLKConfig+0x26c>
      }
      else
      {
        /* set overall return value */
        status = ret;
 800250c:	7cfb      	ldrb	r3, [r7, #19]
 800250e:	74bb      	strb	r3, [r7, #18]
 8002510:	e006      	b.n	8002520 <HAL_RCCEx_PeriphCLKConfig+0x26c>
 8002512:	bf00      	nop
 8002514:	40021000 	.word	0x40021000
 8002518:	40007000 	.word	0x40007000
      }
    }
    else
    {
      /* set overall return value */
      status = ret;
 800251c:	7cfb      	ldrb	r3, [r7, #19]
 800251e:	74bb      	strb	r3, [r7, #18]
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 8002520:	7c7b      	ldrb	r3, [r7, #17]
 8002522:	2b01      	cmp	r3, #1
 8002524:	d105      	bne.n	8002532 <HAL_RCCEx_PeriphCLKConfig+0x27e>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8002526:	4b9e      	ldr	r3, [pc, #632]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002528:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 800252a:	4a9d      	ldr	r2, [pc, #628]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800252c:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8002530:	6593      	str	r3, [r2, #88]	; 0x58
    }
  }

  /*-------------------------- USART1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
 8002532:	687b      	ldr	r3, [r7, #4]
 8002534:	681b      	ldr	r3, [r3, #0]
 8002536:	f003 0301 	and.w	r3, r3, #1
 800253a:	2b00      	cmp	r3, #0
 800253c:	d00a      	beq.n	8002554 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));

    /* Configure the USART1 clock source */
    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
 800253e:	4b98      	ldr	r3, [pc, #608]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002540:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002544:	f023 0203 	bic.w	r2, r3, #3
 8002548:	687b      	ldr	r3, [r7, #4]
 800254a:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 800254c:	4994      	ldr	r1, [pc, #592]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800254e:	4313      	orrs	r3, r2
 8002550:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
  }

  /*-------------------------- USART2 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
 8002554:	687b      	ldr	r3, [r7, #4]
 8002556:	681b      	ldr	r3, [r3, #0]
 8002558:	f003 0302 	and.w	r3, r3, #2
 800255c:	2b00      	cmp	r3, #0
 800255e:	d00a      	beq.n	8002576 <HAL_RCCEx_PeriphCLKConfig+0x2c2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));

    /* Configure the USART2 clock source */
    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
 8002560:	4b8f      	ldr	r3, [pc, #572]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002562:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002566:	f023 020c 	bic.w	r2, r3, #12
 800256a:	687b      	ldr	r3, [r7, #4]
 800256c:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 800256e:	498c      	ldr	r1, [pc, #560]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002570:	4313      	orrs	r3, r2
 8002572:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
  }

#if defined(USART3)

  /*-------------------------- USART3 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
 8002576:	687b      	ldr	r3, [r7, #4]
 8002578:	681b      	ldr	r3, [r3, #0]
 800257a:	f003 0304 	and.w	r3, r3, #4
 800257e:	2b00      	cmp	r3, #0
 8002580:	d00a      	beq.n	8002598 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));

    /* Configure the USART3 clock source */
    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
 8002582:	4b87      	ldr	r3, [pc, #540]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002584:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002588:	f023 0230 	bic.w	r2, r3, #48	; 0x30
 800258c:	687b      	ldr	r3, [r7, #4]
 800258e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8002590:	4983      	ldr	r1, [pc, #524]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002592:	4313      	orrs	r3, r2
 8002594:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
#endif /* USART3 */

#if defined(UART4)

  /*-------------------------- UART4 clock source configuration --------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
 8002598:	687b      	ldr	r3, [r7, #4]
 800259a:	681b      	ldr	r3, [r3, #0]
 800259c:	f003 0308 	and.w	r3, r3, #8
 80025a0:	2b00      	cmp	r3, #0
 80025a2:	d00a      	beq.n	80025ba <HAL_RCCEx_PeriphCLKConfig+0x306>
  {
    /* Check the parameters */
    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));

    /* Configure the UART4 clock source */
    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
 80025a4:	4b7e      	ldr	r3, [pc, #504]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80025a6:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 80025aa:	f023 02c0 	bic.w	r2, r3, #192	; 0xc0
 80025ae:	687b      	ldr	r3, [r7, #4]
 80025b0:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 80025b2:	497b      	ldr	r1, [pc, #492]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80025b4:	4313      	orrs	r3, r2
 80025b6:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
#endif /* UART4 */

#if defined(UART5)

  /*-------------------------- UART5 clock source configuration --------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
 80025ba:	687b      	ldr	r3, [r7, #4]
 80025bc:	681b      	ldr	r3, [r3, #0]
 80025be:	f003 0310 	and.w	r3, r3, #16
 80025c2:	2b00      	cmp	r3, #0
 80025c4:	d00a      	beq.n	80025dc <HAL_RCCEx_PeriphCLKConfig+0x328>
  {
    /* Check the parameters */
    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));

    /* Configure the UART5 clock source */
    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
 80025c6:	4b76      	ldr	r3, [pc, #472]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80025c8:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 80025cc:	f423 7240 	bic.w	r2, r3, #768	; 0x300
 80025d0:	687b      	ldr	r3, [r7, #4]
 80025d2:	6c9b      	ldr	r3, [r3, #72]	; 0x48
 80025d4:	4972      	ldr	r1, [pc, #456]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80025d6:	4313      	orrs	r3, r2
 80025d8:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
  }

#endif /* UART5 */

  /*-------------------------- LPUART1 clock source configuration ------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
 80025dc:	687b      	ldr	r3, [r7, #4]
 80025de:	681b      	ldr	r3, [r3, #0]
 80025e0:	f003 0320 	and.w	r3, r3, #32
 80025e4:	2b00      	cmp	r3, #0
 80025e6:	d00a      	beq.n	80025fe <HAL_RCCEx_PeriphCLKConfig+0x34a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));

    /* Configure the LPUART1 clock source */
    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
 80025e8:	4b6d      	ldr	r3, [pc, #436]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80025ea:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 80025ee:	f423 6240 	bic.w	r2, r3, #3072	; 0xc00
 80025f2:	687b      	ldr	r3, [r7, #4]
 80025f4:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80025f6:	496a      	ldr	r1, [pc, #424]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80025f8:	4313      	orrs	r3, r2
 80025fa:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
  }

  /*-------------------------- LPTIM1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
 80025fe:	687b      	ldr	r3, [r7, #4]
 8002600:	681b      	ldr	r3, [r3, #0]
 8002602:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8002606:	2b00      	cmp	r3, #0
 8002608:	d00a      	beq.n	8002620 <HAL_RCCEx_PeriphCLKConfig+0x36c>
  {
    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
 800260a:	4b65      	ldr	r3, [pc, #404]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800260c:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002610:	f423 2240 	bic.w	r2, r3, #786432	; 0xc0000
 8002614:	687b      	ldr	r3, [r7, #4]
 8002616:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
 8002618:	4961      	ldr	r1, [pc, #388]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800261a:	4313      	orrs	r3, r2
 800261c:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
  }

  /*-------------------------- LPTIM2 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
 8002620:	687b      	ldr	r3, [r7, #4]
 8002622:	681b      	ldr	r3, [r3, #0]
 8002624:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8002628:	2b00      	cmp	r3, #0
 800262a:	d00a      	beq.n	8002642 <HAL_RCCEx_PeriphCLKConfig+0x38e>
  {
    assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
    __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
 800262c:	4b5c      	ldr	r3, [pc, #368]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800262e:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002632:	f423 1240 	bic.w	r2, r3, #3145728	; 0x300000
 8002636:	687b      	ldr	r3, [r7, #4]
 8002638:	6e1b      	ldr	r3, [r3, #96]	; 0x60
 800263a:	4959      	ldr	r1, [pc, #356]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800263c:	4313      	orrs	r3, r2
 800263e:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
  }

  /*-------------------------- I2C1 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
 8002642:	687b      	ldr	r3, [r7, #4]
 8002644:	681b      	ldr	r3, [r3, #0]
 8002646:	f003 0340 	and.w	r3, r3, #64	; 0x40
 800264a:	2b00      	cmp	r3, #0
 800264c:	d00a      	beq.n	8002664 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));

    /* Configure the I2C1 clock source */
    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
 800264e:	4b54      	ldr	r3, [pc, #336]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002650:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002654:	f423 5240 	bic.w	r2, r3, #12288	; 0x3000
 8002658:	687b      	ldr	r3, [r7, #4]
 800265a:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 800265c:	4950      	ldr	r1, [pc, #320]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 800265e:	4313      	orrs	r3, r2
 8002660:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
  }

#if defined(I2C2)

  /*-------------------------- I2C2 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
 8002664:	687b      	ldr	r3, [r7, #4]
 8002666:	681b      	ldr	r3, [r3, #0]
 8002668:	f003 0380 	and.w	r3, r3, #128	; 0x80
 800266c:	2b00      	cmp	r3, #0
 800266e:	d00a      	beq.n	8002686 <HAL_RCCEx_PeriphCLKConfig+0x3d2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));

    /* Configure the I2C2 clock source */
    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
 8002670:	4b4b      	ldr	r3, [pc, #300]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002672:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002676:	f423 4240 	bic.w	r2, r3, #49152	; 0xc000
 800267a:	687b      	ldr	r3, [r7, #4]
 800267c:	6d5b      	ldr	r3, [r3, #84]	; 0x54
 800267e:	4948      	ldr	r1, [pc, #288]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002680:	4313      	orrs	r3, r2
 8002682:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
  }

#endif /* I2C2 */

  /*-------------------------- I2C3 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
 8002686:	687b      	ldr	r3, [r7, #4]
 8002688:	681b      	ldr	r3, [r3, #0]
 800268a:	f403 7380 	and.w	r3, r3, #256	; 0x100
 800268e:	2b00      	cmp	r3, #0
 8002690:	d00a      	beq.n	80026a8 <HAL_RCCEx_PeriphCLKConfig+0x3f4>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));

    /* Configure the I2C3 clock source */
    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
 8002692:	4b43      	ldr	r3, [pc, #268]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002694:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002698:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
 800269c:	687b      	ldr	r3, [r7, #4]
 800269e:	6d9b      	ldr	r3, [r3, #88]	; 0x58
 80026a0:	493f      	ldr	r1, [pc, #252]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80026a2:	4313      	orrs	r3, r2
 80026a4:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
#endif /* I2C4 */

#if defined(USB_OTG_FS) || defined(USB)

  /*-------------------------- USB clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
 80026a8:	687b      	ldr	r3, [r7, #4]
 80026aa:	681b      	ldr	r3, [r3, #0]
 80026ac:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
 80026b0:	2b00      	cmp	r3, #0
 80026b2:	d028      	beq.n	8002706 <HAL_RCCEx_PeriphCLKConfig+0x452>
  {
    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 80026b4:	4b3a      	ldr	r3, [pc, #232]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80026b6:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 80026ba:	f023 6240 	bic.w	r2, r3, #201326592	; 0xc000000
 80026be:	687b      	ldr	r3, [r7, #4]
 80026c0:	6edb      	ldr	r3, [r3, #108]	; 0x6c
 80026c2:	4937      	ldr	r1, [pc, #220]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80026c4:	4313      	orrs	r3, r2
 80026c6:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88

    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
 80026ca:	687b      	ldr	r3, [r7, #4]
 80026cc:	6edb      	ldr	r3, [r3, #108]	; 0x6c
 80026ce:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
 80026d2:	d106      	bne.n	80026e2 <HAL_RCCEx_PeriphCLKConfig+0x42e>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 80026d4:	4b32      	ldr	r3, [pc, #200]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80026d6:	68db      	ldr	r3, [r3, #12]
 80026d8:	4a31      	ldr	r2, [pc, #196]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 80026da:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
 80026de:	60d3      	str	r3, [r2, #12]
 80026e0:	e011      	b.n	8002706 <HAL_RCCEx_PeriphCLKConfig+0x452>
    }
    else
    {
#if defined(RCC_PLLSAI1_SUPPORT)
      if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
 80026e2:	687b      	ldr	r3, [r7, #4]
 80026e4:	6edb      	ldr	r3, [r3, #108]	; 0x6c
 80026e6:	f1b3 6f80 	cmp.w	r3, #67108864	; 0x4000000
 80026ea:	d10c      	bne.n	8002706 <HAL_RCCEx_PeriphCLKConfig+0x452>
      {
        /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
        ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 80026ec:	687b      	ldr	r3, [r7, #4]
 80026ee:	3304      	adds	r3, #4
 80026f0:	2101      	movs	r1, #1
 80026f2:	4618      	mov	r0, r3
 80026f4:	f000 f8d8 	bl	80028a8 <RCCEx_PLLSAI1_Config>
 80026f8:	4603      	mov	r3, r0
 80026fa:	74fb      	strb	r3, [r7, #19]

        if(ret != HAL_OK)
 80026fc:	7cfb      	ldrb	r3, [r7, #19]
 80026fe:	2b00      	cmp	r3, #0
 8002700:	d001      	beq.n	8002706 <HAL_RCCEx_PeriphCLKConfig+0x452>
        {
          /* set overall return value */
          status = ret;
 8002702:	7cfb      	ldrb	r3, [r7, #19]
 8002704:	74bb      	strb	r3, [r7, #18]
#endif /* USB_OTG_FS || USB */

#if defined(SDMMC1)

  /*-------------------------- SDMMC1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
 8002706:	687b      	ldr	r3, [r7, #4]
 8002708:	681b      	ldr	r3, [r3, #0]
 800270a:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
 800270e:	2b00      	cmp	r3, #0
 8002710:	d028      	beq.n	8002764 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
  {
    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
 8002712:	4b23      	ldr	r3, [pc, #140]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002714:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002718:	f023 6240 	bic.w	r2, r3, #201326592	; 0xc000000
 800271c:	687b      	ldr	r3, [r7, #4]
 800271e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002720:	491f      	ldr	r1, [pc, #124]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002722:	4313      	orrs	r3, r2
 8002724:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88

    if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)   /* PLL "Q" ? */
 8002728:	687b      	ldr	r3, [r7, #4]
 800272a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 800272c:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
 8002730:	d106      	bne.n	8002740 <HAL_RCCEx_PeriphCLKConfig+0x48c>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8002732:	4b1b      	ldr	r3, [pc, #108]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002734:	68db      	ldr	r3, [r3, #12]
 8002736:	4a1a      	ldr	r2, [pc, #104]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002738:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
 800273c:	60d3      	str	r3, [r2, #12]
 800273e:	e011      	b.n	8002764 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
    {
      /* Enable PLLSAI3CLK output */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
    }
#endif
    else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
 8002740:	687b      	ldr	r3, [r7, #4]
 8002742:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002744:	f1b3 6f80 	cmp.w	r3, #67108864	; 0x4000000
 8002748:	d10c      	bne.n	8002764 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
    {
      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 800274a:	687b      	ldr	r3, [r7, #4]
 800274c:	3304      	adds	r3, #4
 800274e:	2101      	movs	r1, #1
 8002750:	4618      	mov	r0, r3
 8002752:	f000 f8a9 	bl	80028a8 <RCCEx_PLLSAI1_Config>
 8002756:	4603      	mov	r3, r0
 8002758:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 800275a:	7cfb      	ldrb	r3, [r7, #19]
 800275c:	2b00      	cmp	r3, #0
 800275e:	d001      	beq.n	8002764 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
      {
        /* set overall return value */
        status = ret;
 8002760:	7cfb      	ldrb	r3, [r7, #19]
 8002762:	74bb      	strb	r3, [r7, #18]
  }

#endif /* SDMMC1 */

  /*-------------------------- RNG clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
 8002764:	687b      	ldr	r3, [r7, #4]
 8002766:	681b      	ldr	r3, [r3, #0]
 8002768:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
 800276c:	2b00      	cmp	r3, #0
 800276e:	d02b      	beq.n	80027c8 <HAL_RCCEx_PeriphCLKConfig+0x514>
  {
    assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
 8002770:	4b0b      	ldr	r3, [pc, #44]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002772:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002776:	f023 6240 	bic.w	r2, r3, #201326592	; 0xc000000
 800277a:	687b      	ldr	r3, [r7, #4]
 800277c:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 800277e:	4908      	ldr	r1, [pc, #32]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002780:	4313      	orrs	r3, r2
 8002782:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88

    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
 8002786:	687b      	ldr	r3, [r7, #4]
 8002788:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 800278a:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
 800278e:	d109      	bne.n	80027a4 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8002790:	4b03      	ldr	r3, [pc, #12]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002792:	68db      	ldr	r3, [r3, #12]
 8002794:	4a02      	ldr	r2, [pc, #8]	; (80027a0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
 8002796:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
 800279a:	60d3      	str	r3, [r2, #12]
 800279c:	e014      	b.n	80027c8 <HAL_RCCEx_PeriphCLKConfig+0x514>
 800279e:	bf00      	nop
 80027a0:	40021000 	.word	0x40021000
    }
#if defined(RCC_PLLSAI1_SUPPORT)
    else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
 80027a4:	687b      	ldr	r3, [r7, #4]
 80027a6:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 80027a8:	f1b3 6f80 	cmp.w	r3, #67108864	; 0x4000000
 80027ac:	d10c      	bne.n	80027c8 <HAL_RCCEx_PeriphCLKConfig+0x514>
    {
      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 80027ae:	687b      	ldr	r3, [r7, #4]
 80027b0:	3304      	adds	r3, #4
 80027b2:	2101      	movs	r1, #1
 80027b4:	4618      	mov	r0, r3
 80027b6:	f000 f877 	bl	80028a8 <RCCEx_PLLSAI1_Config>
 80027ba:	4603      	mov	r3, r0
 80027bc:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 80027be:	7cfb      	ldrb	r3, [r7, #19]
 80027c0:	2b00      	cmp	r3, #0
 80027c2:	d001      	beq.n	80027c8 <HAL_RCCEx_PeriphCLKConfig+0x514>
      {
        /* set overall return value */
        status = ret;
 80027c4:	7cfb      	ldrb	r3, [r7, #19]
 80027c6:	74bb      	strb	r3, [r7, #18]
    }
  }

  /*-------------------------- ADC clock source configuration ----------------------*/
#if !defined(STM32L412xx) && !defined(STM32L422xx)
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 80027c8:	687b      	ldr	r3, [r7, #4]
 80027ca:	681b      	ldr	r3, [r3, #0]
 80027cc:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 80027d0:	2b00      	cmp	r3, #0
 80027d2:	d02f      	beq.n	8002834 <HAL_RCCEx_PeriphCLKConfig+0x580>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));

    /* Configure the ADC interface clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 80027d4:	4b2b      	ldr	r3, [pc, #172]	; (8002884 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 80027d6:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 80027da:	f023 5240 	bic.w	r2, r3, #805306368	; 0x30000000
 80027de:	687b      	ldr	r3, [r7, #4]
 80027e0:	6f9b      	ldr	r3, [r3, #120]	; 0x78
 80027e2:	4928      	ldr	r1, [pc, #160]	; (8002884 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 80027e4:	4313      	orrs	r3, r2
 80027e6:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88

#if defined(RCC_PLLSAI1_SUPPORT)
    if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
 80027ea:	687b      	ldr	r3, [r7, #4]
 80027ec:	6f9b      	ldr	r3, [r3, #120]	; 0x78
 80027ee:	f1b3 5f80 	cmp.w	r3, #268435456	; 0x10000000
 80027f2:	d10d      	bne.n	8002810 <HAL_RCCEx_PeriphCLKConfig+0x55c>
    {
      /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
 80027f4:	687b      	ldr	r3, [r7, #4]
 80027f6:	3304      	adds	r3, #4
 80027f8:	2102      	movs	r1, #2
 80027fa:	4618      	mov	r0, r3
 80027fc:	f000 f854 	bl	80028a8 <RCCEx_PLLSAI1_Config>
 8002800:	4603      	mov	r3, r0
 8002802:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 8002804:	7cfb      	ldrb	r3, [r7, #19]
 8002806:	2b00      	cmp	r3, #0
 8002808:	d014      	beq.n	8002834 <HAL_RCCEx_PeriphCLKConfig+0x580>
      {
        /* set overall return value */
        status = ret;
 800280a:	7cfb      	ldrb	r3, [r7, #19]
 800280c:	74bb      	strb	r3, [r7, #18]
 800280e:	e011      	b.n	8002834 <HAL_RCCEx_PeriphCLKConfig+0x580>
    }
#endif /* RCC_PLLSAI1_SUPPORT */

#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)

    else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
 8002810:	687b      	ldr	r3, [r7, #4]
 8002812:	6f9b      	ldr	r3, [r3, #120]	; 0x78
 8002814:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
 8002818:	d10c      	bne.n	8002834 <HAL_RCCEx_PeriphCLKConfig+0x580>
    {
      /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
      ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
 800281a:	687b      	ldr	r3, [r7, #4]
 800281c:	3320      	adds	r3, #32
 800281e:	2102      	movs	r1, #2
 8002820:	4618      	mov	r0, r3
 8002822:	f000 f935 	bl	8002a90 <RCCEx_PLLSAI2_Config>
 8002826:	4603      	mov	r3, r0
 8002828:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 800282a:	7cfb      	ldrb	r3, [r7, #19]
 800282c:	2b00      	cmp	r3, #0
 800282e:	d001      	beq.n	8002834 <HAL_RCCEx_PeriphCLKConfig+0x580>
      {
        /* set overall return value */
        status = ret;
 8002830:	7cfb      	ldrb	r3, [r7, #19]
 8002832:	74bb      	strb	r3, [r7, #18]
#endif /* !STM32L412xx && !STM32L422xx */

#if defined(SWPMI1)

  /*-------------------------- SWPMI1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
 8002834:	687b      	ldr	r3, [r7, #4]
 8002836:	681b      	ldr	r3, [r3, #0]
 8002838:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
 800283c:	2b00      	cmp	r3, #0
 800283e:	d00a      	beq.n	8002856 <HAL_RCCEx_PeriphCLKConfig+0x5a2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));

    /* Configure the SWPMI1 clock source */
    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
 8002840:	4b10      	ldr	r3, [pc, #64]	; (8002884 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 8002842:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002846:	f023 4280 	bic.w	r2, r3, #1073741824	; 0x40000000
 800284a:	687b      	ldr	r3, [r7, #4]
 800284c:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
 800284e:	490d      	ldr	r1, [pc, #52]	; (8002884 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 8002850:	4313      	orrs	r3, r2
 8002852:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
#endif /* SWPMI1 */

#if defined(DFSDM1_Filter0)

  /*-------------------------- DFSDM1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
 8002856:	687b      	ldr	r3, [r7, #4]
 8002858:	681b      	ldr	r3, [r3, #0]
 800285a:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 800285e:	2b00      	cmp	r3, #0
 8002860:	d00b      	beq.n	800287a <HAL_RCCEx_PeriphCLKConfig+0x5c6>
  {
    /* Check the parameters */
    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));

    /* Configure the DFSDM1 interface clock source */
    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
 8002862:	4b08      	ldr	r3, [pc, #32]	; (8002884 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 8002864:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8002868:	f023 4200 	bic.w	r2, r3, #2147483648	; 0x80000000
 800286c:	687b      	ldr	r3, [r7, #4]
 800286e:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
 8002872:	4904      	ldr	r1, [pc, #16]	; (8002884 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
 8002874:	4313      	orrs	r3, r2
 8002876:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
    }
  }

#endif /* OCTOSPI1 || OCTOSPI2 */

  return status;
 800287a:	7cbb      	ldrb	r3, [r7, #18]
}
 800287c:	4618      	mov	r0, r3
 800287e:	3718      	adds	r7, #24
 8002880:	46bd      	mov	sp, r7
 8002882:	bd80      	pop	{r7, pc}
 8002884:	40021000 	.word	0x40021000

08002888 <HAL_RCCEx_EnableMSIPLLMode>:
  * @note   Prior to enable the PLL-mode of the MSI for automatic hardware
  *         calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
  * @retval None
  */
void HAL_RCCEx_EnableMSIPLLMode(void)
{
 8002888:	b480      	push	{r7}
 800288a:	af00      	add	r7, sp, #0
  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
 800288c:	4b05      	ldr	r3, [pc, #20]	; (80028a4 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
 800288e:	681b      	ldr	r3, [r3, #0]
 8002890:	4a04      	ldr	r2, [pc, #16]	; (80028a4 <HAL_RCCEx_EnableMSIPLLMode+0x1c>)
 8002892:	f043 0304 	orr.w	r3, r3, #4
 8002896:	6013      	str	r3, [r2, #0]
}
 8002898:	bf00      	nop
 800289a:	46bd      	mov	sp, r7
 800289c:	f85d 7b04 	ldr.w	r7, [sp], #4
 80028a0:	4770      	bx	lr
 80028a2:	bf00      	nop
 80028a4:	40021000 	.word	0x40021000

080028a8 <RCCEx_PLLSAI1_Config>:
  * @note   PLLSAI1 is temporary disable to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
{
 80028a8:	b580      	push	{r7, lr}
 80028aa:	b084      	sub	sp, #16
 80028ac:	af00      	add	r7, sp, #0
 80028ae:	6078      	str	r0, [r7, #4]
 80028b0:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 80028b2:	2300      	movs	r3, #0
 80028b4:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));

  /* Check that PLLSAI1 clock source and divider M can be applied */
  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
 80028b6:	4b75      	ldr	r3, [pc, #468]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 80028b8:	68db      	ldr	r3, [r3, #12]
 80028ba:	f003 0303 	and.w	r3, r3, #3
 80028be:	2b00      	cmp	r3, #0
 80028c0:	d018      	beq.n	80028f4 <RCCEx_PLLSAI1_Config+0x4c>
  {
    /* PLL clock source and divider M already set, check that no request for change  */
    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
 80028c2:	4b72      	ldr	r3, [pc, #456]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 80028c4:	68db      	ldr	r3, [r3, #12]
 80028c6:	f003 0203 	and.w	r2, r3, #3
 80028ca:	687b      	ldr	r3, [r7, #4]
 80028cc:	681b      	ldr	r3, [r3, #0]
 80028ce:	429a      	cmp	r2, r3
 80028d0:	d10d      	bne.n	80028ee <RCCEx_PLLSAI1_Config+0x46>
       ||
       (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
 80028d2:	687b      	ldr	r3, [r7, #4]
 80028d4:	681b      	ldr	r3, [r3, #0]
       ||
 80028d6:	2b00      	cmp	r3, #0
 80028d8:	d009      	beq.n	80028ee <RCCEx_PLLSAI1_Config+0x46>
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
       ||
       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
 80028da:	4b6c      	ldr	r3, [pc, #432]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 80028dc:	68db      	ldr	r3, [r3, #12]
 80028de:	091b      	lsrs	r3, r3, #4
 80028e0:	f003 0307 	and.w	r3, r3, #7
 80028e4:	1c5a      	adds	r2, r3, #1
 80028e6:	687b      	ldr	r3, [r7, #4]
 80028e8:	685b      	ldr	r3, [r3, #4]
       ||
 80028ea:	429a      	cmp	r2, r3
 80028ec:	d047      	beq.n	800297e <RCCEx_PLLSAI1_Config+0xd6>
#endif
      )
    {
      status = HAL_ERROR;
 80028ee:	2301      	movs	r3, #1
 80028f0:	73fb      	strb	r3, [r7, #15]
 80028f2:	e044      	b.n	800297e <RCCEx_PLLSAI1_Config+0xd6>
    }
  }
  else
  {
    /* Check PLLSAI1 clock source availability */
    switch(PllSai1->PLLSAI1Source)
 80028f4:	687b      	ldr	r3, [r7, #4]
 80028f6:	681b      	ldr	r3, [r3, #0]
 80028f8:	2b03      	cmp	r3, #3
 80028fa:	d018      	beq.n	800292e <RCCEx_PLLSAI1_Config+0x86>
 80028fc:	2b03      	cmp	r3, #3
 80028fe:	d825      	bhi.n	800294c <RCCEx_PLLSAI1_Config+0xa4>
 8002900:	2b01      	cmp	r3, #1
 8002902:	d002      	beq.n	800290a <RCCEx_PLLSAI1_Config+0x62>
 8002904:	2b02      	cmp	r3, #2
 8002906:	d009      	beq.n	800291c <RCCEx_PLLSAI1_Config+0x74>
 8002908:	e020      	b.n	800294c <RCCEx_PLLSAI1_Config+0xa4>
    {
    case RCC_PLLSOURCE_MSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
 800290a:	4b60      	ldr	r3, [pc, #384]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 800290c:	681b      	ldr	r3, [r3, #0]
 800290e:	f003 0302 	and.w	r3, r3, #2
 8002912:	2b00      	cmp	r3, #0
 8002914:	d11d      	bne.n	8002952 <RCCEx_PLLSAI1_Config+0xaa>
      {
        status = HAL_ERROR;
 8002916:	2301      	movs	r3, #1
 8002918:	73fb      	strb	r3, [r7, #15]
      }
      break;
 800291a:	e01a      	b.n	8002952 <RCCEx_PLLSAI1_Config+0xaa>
    case RCC_PLLSOURCE_HSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
 800291c:	4b5b      	ldr	r3, [pc, #364]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 800291e:	681b      	ldr	r3, [r3, #0]
 8002920:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8002924:	2b00      	cmp	r3, #0
 8002926:	d116      	bne.n	8002956 <RCCEx_PLLSAI1_Config+0xae>
      {
        status = HAL_ERROR;
 8002928:	2301      	movs	r3, #1
 800292a:	73fb      	strb	r3, [r7, #15]
      }
      break;
 800292c:	e013      	b.n	8002956 <RCCEx_PLLSAI1_Config+0xae>
    case RCC_PLLSOURCE_HSE:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
 800292e:	4b57      	ldr	r3, [pc, #348]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002930:	681b      	ldr	r3, [r3, #0]
 8002932:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8002936:	2b00      	cmp	r3, #0
 8002938:	d10f      	bne.n	800295a <RCCEx_PLLSAI1_Config+0xb2>
      {
        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
 800293a:	4b54      	ldr	r3, [pc, #336]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 800293c:	681b      	ldr	r3, [r3, #0]
 800293e:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
 8002942:	2b00      	cmp	r3, #0
 8002944:	d109      	bne.n	800295a <RCCEx_PLLSAI1_Config+0xb2>
        {
          status = HAL_ERROR;
 8002946:	2301      	movs	r3, #1
 8002948:	73fb      	strb	r3, [r7, #15]
        }
      }
      break;
 800294a:	e006      	b.n	800295a <RCCEx_PLLSAI1_Config+0xb2>
    default:
      status = HAL_ERROR;
 800294c:	2301      	movs	r3, #1
 800294e:	73fb      	strb	r3, [r7, #15]
      break;
 8002950:	e004      	b.n	800295c <RCCEx_PLLSAI1_Config+0xb4>
      break;
 8002952:	bf00      	nop
 8002954:	e002      	b.n	800295c <RCCEx_PLLSAI1_Config+0xb4>
      break;
 8002956:	bf00      	nop
 8002958:	e000      	b.n	800295c <RCCEx_PLLSAI1_Config+0xb4>
      break;
 800295a:	bf00      	nop
    }

    if(status == HAL_OK)
 800295c:	7bfb      	ldrb	r3, [r7, #15]
 800295e:	2b00      	cmp	r3, #0
 8002960:	d10d      	bne.n	800297e <RCCEx_PLLSAI1_Config+0xd6>
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
      /* Set PLLSAI1 clock source */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
#else
      /* Set PLLSAI1 clock source and divider M */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
 8002962:	4b4a      	ldr	r3, [pc, #296]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002964:	68db      	ldr	r3, [r3, #12]
 8002966:	f023 0273 	bic.w	r2, r3, #115	; 0x73
 800296a:	687b      	ldr	r3, [r7, #4]
 800296c:	6819      	ldr	r1, [r3, #0]
 800296e:	687b      	ldr	r3, [r7, #4]
 8002970:	685b      	ldr	r3, [r3, #4]
 8002972:	3b01      	subs	r3, #1
 8002974:	011b      	lsls	r3, r3, #4
 8002976:	430b      	orrs	r3, r1
 8002978:	4944      	ldr	r1, [pc, #272]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 800297a:	4313      	orrs	r3, r2
 800297c:	60cb      	str	r3, [r1, #12]
#endif
    }
  }

  if(status == HAL_OK)
 800297e:	7bfb      	ldrb	r3, [r7, #15]
 8002980:	2b00      	cmp	r3, #0
 8002982:	d17d      	bne.n	8002a80 <RCCEx_PLLSAI1_Config+0x1d8>
  {
    /* Disable the PLLSAI1 */
    __HAL_RCC_PLLSAI1_DISABLE();
 8002984:	4b41      	ldr	r3, [pc, #260]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002986:	681b      	ldr	r3, [r3, #0]
 8002988:	4a40      	ldr	r2, [pc, #256]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 800298a:	f023 6380 	bic.w	r3, r3, #67108864	; 0x4000000
 800298e:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 8002990:	f7fe f9b8 	bl	8000d04 <HAL_GetTick>
 8002994:	60b8      	str	r0, [r7, #8]

    /* Wait till PLLSAI1 is ready to be updated */
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
 8002996:	e009      	b.n	80029ac <RCCEx_PLLSAI1_Config+0x104>
    {
      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
 8002998:	f7fe f9b4 	bl	8000d04 <HAL_GetTick>
 800299c:	4602      	mov	r2, r0
 800299e:	68bb      	ldr	r3, [r7, #8]
 80029a0:	1ad3      	subs	r3, r2, r3
 80029a2:	2b02      	cmp	r3, #2
 80029a4:	d902      	bls.n	80029ac <RCCEx_PLLSAI1_Config+0x104>
      {
        status = HAL_TIMEOUT;
 80029a6:	2303      	movs	r3, #3
 80029a8:	73fb      	strb	r3, [r7, #15]
        break;
 80029aa:	e005      	b.n	80029b8 <RCCEx_PLLSAI1_Config+0x110>
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
 80029ac:	4b37      	ldr	r3, [pc, #220]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 80029ae:	681b      	ldr	r3, [r3, #0]
 80029b0:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
 80029b4:	2b00      	cmp	r3, #0
 80029b6:	d1ef      	bne.n	8002998 <RCCEx_PLLSAI1_Config+0xf0>
      }
    }

    if(status == HAL_OK)
 80029b8:	7bfb      	ldrb	r3, [r7, #15]
 80029ba:	2b00      	cmp	r3, #0
 80029bc:	d160      	bne.n	8002a80 <RCCEx_PLLSAI1_Config+0x1d8>
    {
      if(Divider == DIVIDER_P_UPDATE)
 80029be:	683b      	ldr	r3, [r7, #0]
 80029c0:	2b00      	cmp	r3, #0
 80029c2:	d111      	bne.n	80029e8 <RCCEx_PLLSAI1_Config+0x140>
        MODIFY_REG(RCC->PLLSAI1CFGR,
                   RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
#else
        MODIFY_REG(RCC->PLLSAI1CFGR,
 80029c4:	4b31      	ldr	r3, [pc, #196]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 80029c6:	691b      	ldr	r3, [r3, #16]
 80029c8:	f423 331f 	bic.w	r3, r3, #162816	; 0x27c00
 80029cc:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 80029d0:	687a      	ldr	r2, [r7, #4]
 80029d2:	6892      	ldr	r2, [r2, #8]
 80029d4:	0211      	lsls	r1, r2, #8
 80029d6:	687a      	ldr	r2, [r7, #4]
 80029d8:	68d2      	ldr	r2, [r2, #12]
 80029da:	0912      	lsrs	r2, r2, #4
 80029dc:	0452      	lsls	r2, r2, #17
 80029de:	430a      	orrs	r2, r1
 80029e0:	492a      	ldr	r1, [pc, #168]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 80029e2:	4313      	orrs	r3, r2
 80029e4:	610b      	str	r3, [r1, #16]
 80029e6:	e027      	b.n	8002a38 <RCCEx_PLLSAI1_Config+0x190>
                   ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */

#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
      }
      else if(Divider == DIVIDER_Q_UPDATE)
 80029e8:	683b      	ldr	r3, [r7, #0]
 80029ea:	2b01      	cmp	r3, #1
 80029ec:	d112      	bne.n	8002a14 <RCCEx_PLLSAI1_Config+0x16c>
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
        /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI1CFGR,
 80029ee:	4b27      	ldr	r3, [pc, #156]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 80029f0:	691b      	ldr	r3, [r3, #16]
 80029f2:	f423 03c0 	bic.w	r3, r3, #6291456	; 0x600000
 80029f6:	f423 43fe 	bic.w	r3, r3, #32512	; 0x7f00
 80029fa:	687a      	ldr	r2, [r7, #4]
 80029fc:	6892      	ldr	r2, [r2, #8]
 80029fe:	0211      	lsls	r1, r2, #8
 8002a00:	687a      	ldr	r2, [r7, #4]
 8002a02:	6912      	ldr	r2, [r2, #16]
 8002a04:	0852      	lsrs	r2, r2, #1
 8002a06:	3a01      	subs	r2, #1
 8002a08:	0552      	lsls	r2, r2, #21
 8002a0a:	430a      	orrs	r2, r1
 8002a0c:	491f      	ldr	r1, [pc, #124]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002a0e:	4313      	orrs	r3, r2
 8002a10:	610b      	str	r3, [r1, #16]
 8002a12:	e011      	b.n	8002a38 <RCCEx_PLLSAI1_Config+0x190>
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
        /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI1CFGR,
 8002a14:	4b1d      	ldr	r3, [pc, #116]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002a16:	691b      	ldr	r3, [r3, #16]
 8002a18:	f023 63c0 	bic.w	r3, r3, #100663296	; 0x6000000
 8002a1c:	f423 43fe 	bic.w	r3, r3, #32512	; 0x7f00
 8002a20:	687a      	ldr	r2, [r7, #4]
 8002a22:	6892      	ldr	r2, [r2, #8]
 8002a24:	0211      	lsls	r1, r2, #8
 8002a26:	687a      	ldr	r2, [r7, #4]
 8002a28:	6952      	ldr	r2, [r2, #20]
 8002a2a:	0852      	lsrs	r2, r2, #1
 8002a2c:	3a01      	subs	r2, #1
 8002a2e:	0652      	lsls	r2, r2, #25
 8002a30:	430a      	orrs	r2, r1
 8002a32:	4916      	ldr	r1, [pc, #88]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002a34:	4313      	orrs	r3, r2
 8002a36:	610b      	str	r3, [r1, #16]
                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
      }

      /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
      __HAL_RCC_PLLSAI1_ENABLE();
 8002a38:	4b14      	ldr	r3, [pc, #80]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002a3a:	681b      	ldr	r3, [r3, #0]
 8002a3c:	4a13      	ldr	r2, [pc, #76]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002a3e:	f043 6380 	orr.w	r3, r3, #67108864	; 0x4000000
 8002a42:	6013      	str	r3, [r2, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002a44:	f7fe f95e 	bl	8000d04 <HAL_GetTick>
 8002a48:	60b8      	str	r0, [r7, #8]

      /* Wait till PLLSAI1 is ready */
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
 8002a4a:	e009      	b.n	8002a60 <RCCEx_PLLSAI1_Config+0x1b8>
      {
        if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
 8002a4c:	f7fe f95a 	bl	8000d04 <HAL_GetTick>
 8002a50:	4602      	mov	r2, r0
 8002a52:	68bb      	ldr	r3, [r7, #8]
 8002a54:	1ad3      	subs	r3, r2, r3
 8002a56:	2b02      	cmp	r3, #2
 8002a58:	d902      	bls.n	8002a60 <RCCEx_PLLSAI1_Config+0x1b8>
        {
          status = HAL_TIMEOUT;
 8002a5a:	2303      	movs	r3, #3
 8002a5c:	73fb      	strb	r3, [r7, #15]
          break;
 8002a5e:	e005      	b.n	8002a6c <RCCEx_PLLSAI1_Config+0x1c4>
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
 8002a60:	4b0a      	ldr	r3, [pc, #40]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002a62:	681b      	ldr	r3, [r3, #0]
 8002a64:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
 8002a68:	2b00      	cmp	r3, #0
 8002a6a:	d0ef      	beq.n	8002a4c <RCCEx_PLLSAI1_Config+0x1a4>
        }
      }

      if(status == HAL_OK)
 8002a6c:	7bfb      	ldrb	r3, [r7, #15]
 8002a6e:	2b00      	cmp	r3, #0
 8002a70:	d106      	bne.n	8002a80 <RCCEx_PLLSAI1_Config+0x1d8>
      {
        /* Configure the PLLSAI1 Clock output(s) */
        __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
 8002a72:	4b06      	ldr	r3, [pc, #24]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002a74:	691a      	ldr	r2, [r3, #16]
 8002a76:	687b      	ldr	r3, [r7, #4]
 8002a78:	699b      	ldr	r3, [r3, #24]
 8002a7a:	4904      	ldr	r1, [pc, #16]	; (8002a8c <RCCEx_PLLSAI1_Config+0x1e4>)
 8002a7c:	4313      	orrs	r3, r2
 8002a7e:	610b      	str	r3, [r1, #16]
      }
    }
  }

  return status;
 8002a80:	7bfb      	ldrb	r3, [r7, #15]
}
 8002a82:	4618      	mov	r0, r3
 8002a84:	3710      	adds	r7, #16
 8002a86:	46bd      	mov	sp, r7
 8002a88:	bd80      	pop	{r7, pc}
 8002a8a:	bf00      	nop
 8002a8c:	40021000 	.word	0x40021000

08002a90 <RCCEx_PLLSAI2_Config>:
  * @note   PLLSAI2 is temporary disable to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
{
 8002a90:	b580      	push	{r7, lr}
 8002a92:	b084      	sub	sp, #16
 8002a94:	af00      	add	r7, sp, #0
 8002a96:	6078      	str	r0, [r7, #4]
 8002a98:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 8002a9a:	2300      	movs	r3, #0
 8002a9c:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
  assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));

  /* Check that PLLSAI2 clock source and divider M can be applied */
  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
 8002a9e:	4b6a      	ldr	r3, [pc, #424]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002aa0:	68db      	ldr	r3, [r3, #12]
 8002aa2:	f003 0303 	and.w	r3, r3, #3
 8002aa6:	2b00      	cmp	r3, #0
 8002aa8:	d018      	beq.n	8002adc <RCCEx_PLLSAI2_Config+0x4c>
  {
    /* PLL clock source and divider M already set, check that no request for change  */
    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
 8002aaa:	4b67      	ldr	r3, [pc, #412]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002aac:	68db      	ldr	r3, [r3, #12]
 8002aae:	f003 0203 	and.w	r2, r3, #3
 8002ab2:	687b      	ldr	r3, [r7, #4]
 8002ab4:	681b      	ldr	r3, [r3, #0]
 8002ab6:	429a      	cmp	r2, r3
 8002ab8:	d10d      	bne.n	8002ad6 <RCCEx_PLLSAI2_Config+0x46>
       ||
       (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
 8002aba:	687b      	ldr	r3, [r7, #4]
 8002abc:	681b      	ldr	r3, [r3, #0]
       ||
 8002abe:	2b00      	cmp	r3, #0
 8002ac0:	d009      	beq.n	8002ad6 <RCCEx_PLLSAI2_Config+0x46>
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
       ||
       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
 8002ac2:	4b61      	ldr	r3, [pc, #388]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002ac4:	68db      	ldr	r3, [r3, #12]
 8002ac6:	091b      	lsrs	r3, r3, #4
 8002ac8:	f003 0307 	and.w	r3, r3, #7
 8002acc:	1c5a      	adds	r2, r3, #1
 8002ace:	687b      	ldr	r3, [r7, #4]
 8002ad0:	685b      	ldr	r3, [r3, #4]
       ||
 8002ad2:	429a      	cmp	r2, r3
 8002ad4:	d047      	beq.n	8002b66 <RCCEx_PLLSAI2_Config+0xd6>
#endif
      )
    {
      status = HAL_ERROR;
 8002ad6:	2301      	movs	r3, #1
 8002ad8:	73fb      	strb	r3, [r7, #15]
 8002ada:	e044      	b.n	8002b66 <RCCEx_PLLSAI2_Config+0xd6>
    }
  }
  else
  {
    /* Check PLLSAI2 clock source availability */
    switch(PllSai2->PLLSAI2Source)
 8002adc:	687b      	ldr	r3, [r7, #4]
 8002ade:	681b      	ldr	r3, [r3, #0]
 8002ae0:	2b03      	cmp	r3, #3
 8002ae2:	d018      	beq.n	8002b16 <RCCEx_PLLSAI2_Config+0x86>
 8002ae4:	2b03      	cmp	r3, #3
 8002ae6:	d825      	bhi.n	8002b34 <RCCEx_PLLSAI2_Config+0xa4>
 8002ae8:	2b01      	cmp	r3, #1
 8002aea:	d002      	beq.n	8002af2 <RCCEx_PLLSAI2_Config+0x62>
 8002aec:	2b02      	cmp	r3, #2
 8002aee:	d009      	beq.n	8002b04 <RCCEx_PLLSAI2_Config+0x74>
 8002af0:	e020      	b.n	8002b34 <RCCEx_PLLSAI2_Config+0xa4>
    {
    case RCC_PLLSOURCE_MSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
 8002af2:	4b55      	ldr	r3, [pc, #340]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002af4:	681b      	ldr	r3, [r3, #0]
 8002af6:	f003 0302 	and.w	r3, r3, #2
 8002afa:	2b00      	cmp	r3, #0
 8002afc:	d11d      	bne.n	8002b3a <RCCEx_PLLSAI2_Config+0xaa>
      {
        status = HAL_ERROR;
 8002afe:	2301      	movs	r3, #1
 8002b00:	73fb      	strb	r3, [r7, #15]
      }
      break;
 8002b02:	e01a      	b.n	8002b3a <RCCEx_PLLSAI2_Config+0xaa>
    case RCC_PLLSOURCE_HSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
 8002b04:	4b50      	ldr	r3, [pc, #320]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002b06:	681b      	ldr	r3, [r3, #0]
 8002b08:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8002b0c:	2b00      	cmp	r3, #0
 8002b0e:	d116      	bne.n	8002b3e <RCCEx_PLLSAI2_Config+0xae>
      {
        status = HAL_ERROR;
 8002b10:	2301      	movs	r3, #1
 8002b12:	73fb      	strb	r3, [r7, #15]
      }
      break;
 8002b14:	e013      	b.n	8002b3e <RCCEx_PLLSAI2_Config+0xae>
    case RCC_PLLSOURCE_HSE:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
 8002b16:	4b4c      	ldr	r3, [pc, #304]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002b18:	681b      	ldr	r3, [r3, #0]
 8002b1a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8002b1e:	2b00      	cmp	r3, #0
 8002b20:	d10f      	bne.n	8002b42 <RCCEx_PLLSAI2_Config+0xb2>
      {
        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
 8002b22:	4b49      	ldr	r3, [pc, #292]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002b24:	681b      	ldr	r3, [r3, #0]
 8002b26:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
 8002b2a:	2b00      	cmp	r3, #0
 8002b2c:	d109      	bne.n	8002b42 <RCCEx_PLLSAI2_Config+0xb2>
        {
          status = HAL_ERROR;
 8002b2e:	2301      	movs	r3, #1
 8002b30:	73fb      	strb	r3, [r7, #15]
        }
      }
      break;
 8002b32:	e006      	b.n	8002b42 <RCCEx_PLLSAI2_Config+0xb2>
    default:
      status = HAL_ERROR;
 8002b34:	2301      	movs	r3, #1
 8002b36:	73fb      	strb	r3, [r7, #15]
      break;
 8002b38:	e004      	b.n	8002b44 <RCCEx_PLLSAI2_Config+0xb4>
      break;
 8002b3a:	bf00      	nop
 8002b3c:	e002      	b.n	8002b44 <RCCEx_PLLSAI2_Config+0xb4>
      break;
 8002b3e:	bf00      	nop
 8002b40:	e000      	b.n	8002b44 <RCCEx_PLLSAI2_Config+0xb4>
      break;
 8002b42:	bf00      	nop
    }

    if(status == HAL_OK)
 8002b44:	7bfb      	ldrb	r3, [r7, #15]
 8002b46:	2b00      	cmp	r3, #0
 8002b48:	d10d      	bne.n	8002b66 <RCCEx_PLLSAI2_Config+0xd6>
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
      /* Set PLLSAI2 clock source */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
#else
      /* Set PLLSAI2 clock source and divider M */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
 8002b4a:	4b3f      	ldr	r3, [pc, #252]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002b4c:	68db      	ldr	r3, [r3, #12]
 8002b4e:	f023 0273 	bic.w	r2, r3, #115	; 0x73
 8002b52:	687b      	ldr	r3, [r7, #4]
 8002b54:	6819      	ldr	r1, [r3, #0]
 8002b56:	687b      	ldr	r3, [r7, #4]
 8002b58:	685b      	ldr	r3, [r3, #4]
 8002b5a:	3b01      	subs	r3, #1
 8002b5c:	011b      	lsls	r3, r3, #4
 8002b5e:	430b      	orrs	r3, r1
 8002b60:	4939      	ldr	r1, [pc, #228]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002b62:	4313      	orrs	r3, r2
 8002b64:	60cb      	str	r3, [r1, #12]
#endif
    }
  }

  if(status == HAL_OK)
 8002b66:	7bfb      	ldrb	r3, [r7, #15]
 8002b68:	2b00      	cmp	r3, #0
 8002b6a:	d167      	bne.n	8002c3c <RCCEx_PLLSAI2_Config+0x1ac>
  {
    /* Disable the PLLSAI2 */
    __HAL_RCC_PLLSAI2_DISABLE();
 8002b6c:	4b36      	ldr	r3, [pc, #216]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002b6e:	681b      	ldr	r3, [r3, #0]
 8002b70:	4a35      	ldr	r2, [pc, #212]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002b72:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8002b76:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 8002b78:	f7fe f8c4 	bl	8000d04 <HAL_GetTick>
 8002b7c:	60b8      	str	r0, [r7, #8]

    /* Wait till PLLSAI2 is ready to be updated */
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
 8002b7e:	e009      	b.n	8002b94 <RCCEx_PLLSAI2_Config+0x104>
    {
      if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
 8002b80:	f7fe f8c0 	bl	8000d04 <HAL_GetTick>
 8002b84:	4602      	mov	r2, r0
 8002b86:	68bb      	ldr	r3, [r7, #8]
 8002b88:	1ad3      	subs	r3, r2, r3
 8002b8a:	2b02      	cmp	r3, #2
 8002b8c:	d902      	bls.n	8002b94 <RCCEx_PLLSAI2_Config+0x104>
      {
        status = HAL_TIMEOUT;
 8002b8e:	2303      	movs	r3, #3
 8002b90:	73fb      	strb	r3, [r7, #15]
        break;
 8002b92:	e005      	b.n	8002ba0 <RCCEx_PLLSAI2_Config+0x110>
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
 8002b94:	4b2c      	ldr	r3, [pc, #176]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002b96:	681b      	ldr	r3, [r3, #0]
 8002b98:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
 8002b9c:	2b00      	cmp	r3, #0
 8002b9e:	d1ef      	bne.n	8002b80 <RCCEx_PLLSAI2_Config+0xf0>
      }
    }

    if(status == HAL_OK)
 8002ba0:	7bfb      	ldrb	r3, [r7, #15]
 8002ba2:	2b00      	cmp	r3, #0
 8002ba4:	d14a      	bne.n	8002c3c <RCCEx_PLLSAI2_Config+0x1ac>
    {
      if(Divider == DIVIDER_P_UPDATE)
 8002ba6:	683b      	ldr	r3, [r7, #0]
 8002ba8:	2b00      	cmp	r3, #0
 8002baa:	d111      	bne.n	8002bd0 <RCCEx_PLLSAI2_Config+0x140>
        MODIFY_REG(RCC->PLLSAI2CFGR,
                   RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
                   (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
#else
        MODIFY_REG(RCC->PLLSAI2CFGR,
 8002bac:	4b26      	ldr	r3, [pc, #152]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002bae:	695b      	ldr	r3, [r3, #20]
 8002bb0:	f423 331f 	bic.w	r3, r3, #162816	; 0x27c00
 8002bb4:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8002bb8:	687a      	ldr	r2, [r7, #4]
 8002bba:	6892      	ldr	r2, [r2, #8]
 8002bbc:	0211      	lsls	r1, r2, #8
 8002bbe:	687a      	ldr	r2, [r7, #4]
 8002bc0:	68d2      	ldr	r2, [r2, #12]
 8002bc2:	0912      	lsrs	r2, r2, #4
 8002bc4:	0452      	lsls	r2, r2, #17
 8002bc6:	430a      	orrs	r2, r1
 8002bc8:	491f      	ldr	r1, [pc, #124]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002bca:	4313      	orrs	r3, r2
 8002bcc:	614b      	str	r3, [r1, #20]
 8002bce:	e011      	b.n	8002bf4 <RCCEx_PLLSAI2_Config+0x164>
                   (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
                   ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
#else
        /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI2CFGR,
 8002bd0:	4b1d      	ldr	r3, [pc, #116]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002bd2:	695b      	ldr	r3, [r3, #20]
 8002bd4:	f023 63c0 	bic.w	r3, r3, #100663296	; 0x6000000
 8002bd8:	f423 43fe 	bic.w	r3, r3, #32512	; 0x7f00
 8002bdc:	687a      	ldr	r2, [r7, #4]
 8002bde:	6892      	ldr	r2, [r2, #8]
 8002be0:	0211      	lsls	r1, r2, #8
 8002be2:	687a      	ldr	r2, [r7, #4]
 8002be4:	6912      	ldr	r2, [r2, #16]
 8002be6:	0852      	lsrs	r2, r2, #1
 8002be8:	3a01      	subs	r2, #1
 8002bea:	0652      	lsls	r2, r2, #25
 8002bec:	430a      	orrs	r2, r1
 8002bee:	4916      	ldr	r1, [pc, #88]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002bf0:	4313      	orrs	r3, r2
 8002bf2:	614b      	str	r3, [r1, #20]
                   (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
      }

      /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
      __HAL_RCC_PLLSAI2_ENABLE();
 8002bf4:	4b14      	ldr	r3, [pc, #80]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002bf6:	681b      	ldr	r3, [r3, #0]
 8002bf8:	4a13      	ldr	r2, [pc, #76]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002bfa:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8002bfe:	6013      	str	r3, [r2, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002c00:	f7fe f880 	bl	8000d04 <HAL_GetTick>
 8002c04:	60b8      	str	r0, [r7, #8]

      /* Wait till PLLSAI2 is ready */
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
 8002c06:	e009      	b.n	8002c1c <RCCEx_PLLSAI2_Config+0x18c>
      {
        if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
 8002c08:	f7fe f87c 	bl	8000d04 <HAL_GetTick>
 8002c0c:	4602      	mov	r2, r0
 8002c0e:	68bb      	ldr	r3, [r7, #8]
 8002c10:	1ad3      	subs	r3, r2, r3
 8002c12:	2b02      	cmp	r3, #2
 8002c14:	d902      	bls.n	8002c1c <RCCEx_PLLSAI2_Config+0x18c>
        {
          status = HAL_TIMEOUT;
 8002c16:	2303      	movs	r3, #3
 8002c18:	73fb      	strb	r3, [r7, #15]
          break;
 8002c1a:	e005      	b.n	8002c28 <RCCEx_PLLSAI2_Config+0x198>
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
 8002c1c:	4b0a      	ldr	r3, [pc, #40]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002c1e:	681b      	ldr	r3, [r3, #0]
 8002c20:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
 8002c24:	2b00      	cmp	r3, #0
 8002c26:	d0ef      	beq.n	8002c08 <RCCEx_PLLSAI2_Config+0x178>
        }
      }

      if(status == HAL_OK)
 8002c28:	7bfb      	ldrb	r3, [r7, #15]
 8002c2a:	2b00      	cmp	r3, #0
 8002c2c:	d106      	bne.n	8002c3c <RCCEx_PLLSAI2_Config+0x1ac>
      {
        /* Configure the PLLSAI2 Clock output(s) */
        __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
 8002c2e:	4b06      	ldr	r3, [pc, #24]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002c30:	695a      	ldr	r2, [r3, #20]
 8002c32:	687b      	ldr	r3, [r7, #4]
 8002c34:	695b      	ldr	r3, [r3, #20]
 8002c36:	4904      	ldr	r1, [pc, #16]	; (8002c48 <RCCEx_PLLSAI2_Config+0x1b8>)
 8002c38:	4313      	orrs	r3, r2
 8002c3a:	614b      	str	r3, [r1, #20]
      }
    }
  }

  return status;
 8002c3c:	7bfb      	ldrb	r3, [r7, #15]
}
 8002c3e:	4618      	mov	r0, r3
 8002c40:	3710      	adds	r7, #16
 8002c42:	46bd      	mov	sp, r7
 8002c44:	bd80      	pop	{r7, pc}
 8002c46:	bf00      	nop
 8002c48:	40021000 	.word	0x40021000

08002c4c <HAL_RNG_Init>:
  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
  *                the configuration information for RNG.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
 8002c4c:	b580      	push	{r7, lr}
 8002c4e:	b084      	sub	sp, #16
 8002c50:	af00      	add	r7, sp, #0
 8002c52:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
#if defined(RNG_CR_CONDRST)
  uint32_t cr_value;
#endif  /* RNG_CR_CONDRST */
  /* Check the RNG handle allocation */
  if (hrng == NULL)
 8002c54:	687b      	ldr	r3, [r7, #4]
 8002c56:	2b00      	cmp	r3, #0
 8002c58:	d101      	bne.n	8002c5e <HAL_RNG_Init+0x12>
  {
    return HAL_ERROR;
 8002c5a:	2301      	movs	r3, #1
 8002c5c:	e049      	b.n	8002cf2 <HAL_RNG_Init+0xa6>

    /* Init the low level hardware */
    hrng->MspInitCallback(hrng);
  }
#else
  if (hrng->State == HAL_RNG_STATE_RESET)
 8002c5e:	687b      	ldr	r3, [r7, #4]
 8002c60:	795b      	ldrb	r3, [r3, #5]
 8002c62:	b2db      	uxtb	r3, r3
 8002c64:	2b00      	cmp	r3, #0
 8002c66:	d105      	bne.n	8002c74 <HAL_RNG_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    hrng->Lock = HAL_UNLOCKED;
 8002c68:	687b      	ldr	r3, [r7, #4]
 8002c6a:	2200      	movs	r2, #0
 8002c6c:	711a      	strb	r2, [r3, #4]

    /* Init the low level hardware */
    HAL_RNG_MspInit(hrng);
 8002c6e:	6878      	ldr	r0, [r7, #4]
 8002c70:	f7fd fdac 	bl	80007cc <HAL_RNG_MspInit>
  }
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */

  /* Change RNG peripheral state */
  hrng->State = HAL_RNG_STATE_BUSY;
 8002c74:	687b      	ldr	r3, [r7, #4]
 8002c76:	2202      	movs	r2, #2
 8002c78:	715a      	strb	r2, [r3, #5]
  MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
#endif /* defined(RNG_CR_CED) */
#endif /* end of RNG_CR_CONDRST */

  /* Enable the RNG Peripheral */
  __HAL_RNG_ENABLE(hrng);
 8002c7a:	687b      	ldr	r3, [r7, #4]
 8002c7c:	681b      	ldr	r3, [r3, #0]
 8002c7e:	681a      	ldr	r2, [r3, #0]
 8002c80:	687b      	ldr	r3, [r7, #4]
 8002c82:	681b      	ldr	r3, [r3, #0]
 8002c84:	f042 0204 	orr.w	r2, r2, #4
 8002c88:	601a      	str	r2, [r3, #0]

  /* verify that no seed error */
  if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
 8002c8a:	687b      	ldr	r3, [r7, #4]
 8002c8c:	681b      	ldr	r3, [r3, #0]
 8002c8e:	685b      	ldr	r3, [r3, #4]
 8002c90:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002c94:	2b40      	cmp	r3, #64	; 0x40
 8002c96:	d104      	bne.n	8002ca2 <HAL_RNG_Init+0x56>
  {
    hrng->State = HAL_RNG_STATE_ERROR;
 8002c98:	687b      	ldr	r3, [r7, #4]
 8002c9a:	2204      	movs	r2, #4
 8002c9c:	715a      	strb	r2, [r3, #5]
    return HAL_ERROR;
 8002c9e:	2301      	movs	r3, #1
 8002ca0:	e027      	b.n	8002cf2 <HAL_RNG_Init+0xa6>
  }
  /* Get tick */
  tickstart = HAL_GetTick();
 8002ca2:	f7fe f82f 	bl	8000d04 <HAL_GetTick>
 8002ca6:	60f8      	str	r0, [r7, #12]
  /* Check if data register contains valid random data */
  while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
 8002ca8:	e015      	b.n	8002cd6 <HAL_RNG_Init+0x8a>
  {
    if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
 8002caa:	f7fe f82b 	bl	8000d04 <HAL_GetTick>
 8002cae:	4602      	mov	r2, r0
 8002cb0:	68fb      	ldr	r3, [r7, #12]
 8002cb2:	1ad3      	subs	r3, r2, r3
 8002cb4:	2b02      	cmp	r3, #2
 8002cb6:	d90e      	bls.n	8002cd6 <HAL_RNG_Init+0x8a>
    {
      /* New check to avoid false timeout detection in case of preemption */
      if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
 8002cb8:	687b      	ldr	r3, [r7, #4]
 8002cba:	681b      	ldr	r3, [r3, #0]
 8002cbc:	685b      	ldr	r3, [r3, #4]
 8002cbe:	f003 0304 	and.w	r3, r3, #4
 8002cc2:	2b04      	cmp	r3, #4
 8002cc4:	d107      	bne.n	8002cd6 <HAL_RNG_Init+0x8a>
      {
        hrng->State = HAL_RNG_STATE_ERROR;
 8002cc6:	687b      	ldr	r3, [r7, #4]
 8002cc8:	2204      	movs	r2, #4
 8002cca:	715a      	strb	r2, [r3, #5]
        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
 8002ccc:	687b      	ldr	r3, [r7, #4]
 8002cce:	2202      	movs	r2, #2
 8002cd0:	609a      	str	r2, [r3, #8]
        return HAL_ERROR;
 8002cd2:	2301      	movs	r3, #1
 8002cd4:	e00d      	b.n	8002cf2 <HAL_RNG_Init+0xa6>
  while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
 8002cd6:	687b      	ldr	r3, [r7, #4]
 8002cd8:	681b      	ldr	r3, [r3, #0]
 8002cda:	685b      	ldr	r3, [r3, #4]
 8002cdc:	f003 0304 	and.w	r3, r3, #4
 8002ce0:	2b04      	cmp	r3, #4
 8002ce2:	d0e2      	beq.n	8002caa <HAL_RNG_Init+0x5e>
      }
    }
  }

  /* Initialize the RNG state */
  hrng->State = HAL_RNG_STATE_READY;
 8002ce4:	687b      	ldr	r3, [r7, #4]
 8002ce6:	2201      	movs	r2, #1
 8002ce8:	715a      	strb	r2, [r3, #5]

  /* Initialise the error code */
  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
 8002cea:	687b      	ldr	r3, [r7, #4]
 8002cec:	2200      	movs	r2, #0
 8002cee:	609a      	str	r2, [r3, #8]

  /* Return function status */
  return HAL_OK;
 8002cf0:	2300      	movs	r3, #0
}
 8002cf2:	4618      	mov	r0, r3
 8002cf4:	3710      	adds	r7, #16
 8002cf6:	46bd      	mov	sp, r7
 8002cf8:	bd80      	pop	{r7, pc}

08002cfa <HAL_RTC_Init>:
  * @brief  Initialize the RTC peripheral
  * @param  hrtc RTC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
 8002cfa:	b580      	push	{r7, lr}
 8002cfc:	b084      	sub	sp, #16
 8002cfe:	af00      	add	r7, sp, #0
 8002d00:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_ERROR;
 8002d02:	2301      	movs	r3, #1
 8002d04:	73fb      	strb	r3, [r7, #15]

  /* Check the RTC peripheral state */
  if (hrtc != NULL)
 8002d06:	687b      	ldr	r3, [r7, #4]
 8002d08:	2b00      	cmp	r3, #0
 8002d0a:	d06c      	beq.n	8002de6 <HAL_RTC_Init+0xec>
      {
        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
      }
    }
#else /* #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
    if (hrtc->State == HAL_RTC_STATE_RESET)
 8002d0c:	687b      	ldr	r3, [r7, #4]
 8002d0e:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 8002d12:	b2db      	uxtb	r3, r3
 8002d14:	2b00      	cmp	r3, #0
 8002d16:	d106      	bne.n	8002d26 <HAL_RTC_Init+0x2c>
    {
      /* Allocate lock resource and initialize it */
      hrtc->Lock = HAL_UNLOCKED;
 8002d18:	687b      	ldr	r3, [r7, #4]
 8002d1a:	2200      	movs	r2, #0
 8002d1c:	f883 2020 	strb.w	r2, [r3, #32]

      /* Initialize RTC MSP */
      HAL_RTC_MspInit(hrtc);
 8002d20:	6878      	ldr	r0, [r7, #4]
 8002d22:	f7fd fdb1 	bl	8000888 <HAL_RTC_MspInit>
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
    /* Process TAMP ip offset from RTC one */
    hrtc->TampOffset = (TAMP_BASE - RTC_BASE);
#endif
    /* Set RTC state */
    hrtc->State = HAL_RTC_STATE_BUSY;
 8002d26:	687b      	ldr	r3, [r7, #4]
 8002d28:	2202      	movs	r2, #2
 8002d2a:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21

    /* Disable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 8002d2e:	687b      	ldr	r3, [r7, #4]
 8002d30:	681b      	ldr	r3, [r3, #0]
 8002d32:	22ca      	movs	r2, #202	; 0xca
 8002d34:	625a      	str	r2, [r3, #36]	; 0x24
 8002d36:	687b      	ldr	r3, [r7, #4]
 8002d38:	681b      	ldr	r3, [r3, #0]
 8002d3a:	2253      	movs	r2, #83	; 0x53
 8002d3c:	625a      	str	r2, [r3, #36]	; 0x24

    /* Enter Initialization mode */
    status = RTC_EnterInitMode(hrtc);
 8002d3e:	6878      	ldr	r0, [r7, #4]
 8002d40:	f000 f87c 	bl	8002e3c <RTC_EnterInitMode>
 8002d44:	4603      	mov	r3, r0
 8002d46:	73fb      	strb	r3, [r7, #15]

    if (status == HAL_OK)
 8002d48:	7bfb      	ldrb	r3, [r7, #15]
 8002d4a:	2b00      	cmp	r3, #0
 8002d4c:	d14b      	bne.n	8002de6 <HAL_RTC_Init+0xec>
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
      /* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */
      hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE);
#else
      /* Clear RTC_CR FMT, OSEL and POL Bits */
      hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL);
 8002d4e:	687b      	ldr	r3, [r7, #4]
 8002d50:	681b      	ldr	r3, [r3, #0]
 8002d52:	689b      	ldr	r3, [r3, #8]
 8002d54:	687a      	ldr	r2, [r7, #4]
 8002d56:	6812      	ldr	r2, [r2, #0]
 8002d58:	f423 03e0 	bic.w	r3, r3, #7340032	; 0x700000
 8002d5c:	f023 0340 	bic.w	r3, r3, #64	; 0x40
 8002d60:	6093      	str	r3, [r2, #8]
#endif
      /* Set RTC_CR register */
      hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
 8002d62:	687b      	ldr	r3, [r7, #4]
 8002d64:	681b      	ldr	r3, [r3, #0]
 8002d66:	6899      	ldr	r1, [r3, #8]
 8002d68:	687b      	ldr	r3, [r7, #4]
 8002d6a:	685a      	ldr	r2, [r3, #4]
 8002d6c:	687b      	ldr	r3, [r7, #4]
 8002d6e:	691b      	ldr	r3, [r3, #16]
 8002d70:	431a      	orrs	r2, r3
 8002d72:	687b      	ldr	r3, [r7, #4]
 8002d74:	699b      	ldr	r3, [r3, #24]
 8002d76:	431a      	orrs	r2, r3
 8002d78:	687b      	ldr	r3, [r7, #4]
 8002d7a:	681b      	ldr	r3, [r3, #0]
 8002d7c:	430a      	orrs	r2, r1
 8002d7e:	609a      	str	r2, [r3, #8]

      /* Configure the RTC PRER */
      hrtc->Instance->PRER = (hrtc->Init.SynchPrediv);
 8002d80:	687b      	ldr	r3, [r7, #4]
 8002d82:	681b      	ldr	r3, [r3, #0]
 8002d84:	687a      	ldr	r2, [r7, #4]
 8002d86:	68d2      	ldr	r2, [r2, #12]
 8002d88:	611a      	str	r2, [r3, #16]
      hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
 8002d8a:	687b      	ldr	r3, [r7, #4]
 8002d8c:	681b      	ldr	r3, [r3, #0]
 8002d8e:	6919      	ldr	r1, [r3, #16]
 8002d90:	687b      	ldr	r3, [r7, #4]
 8002d92:	689b      	ldr	r3, [r3, #8]
 8002d94:	041a      	lsls	r2, r3, #16
 8002d96:	687b      	ldr	r3, [r7, #4]
 8002d98:	681b      	ldr	r3, [r3, #0]
 8002d9a:	430a      	orrs	r2, r1
 8002d9c:	611a      	str	r2, [r3, #16]
      /* Configure the Binary mode */
      MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
#endif

      /* Exit Initialization mode */
      status = RTC_ExitInitMode(hrtc);
 8002d9e:	6878      	ldr	r0, [r7, #4]
 8002da0:	f000 f880 	bl	8002ea4 <RTC_ExitInitMode>
 8002da4:	4603      	mov	r3, r0
 8002da6:	73fb      	strb	r3, [r7, #15]

      if (status == HAL_OK)
 8002da8:	7bfb      	ldrb	r3, [r7, #15]
 8002daa:	2b00      	cmp	r3, #0
 8002dac:	d11b      	bne.n	8002de6 <HAL_RTC_Init+0xec>
      {
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
        hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN);
        hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
#else
        hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
 8002dae:	687b      	ldr	r3, [r7, #4]
 8002db0:	681b      	ldr	r3, [r3, #0]
 8002db2:	6cda      	ldr	r2, [r3, #76]	; 0x4c
 8002db4:	687b      	ldr	r3, [r7, #4]
 8002db6:	681b      	ldr	r3, [r3, #0]
 8002db8:	f022 0203 	bic.w	r2, r2, #3
 8002dbc:	64da      	str	r2, [r3, #76]	; 0x4c
        hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
 8002dbe:	687b      	ldr	r3, [r7, #4]
 8002dc0:	681b      	ldr	r3, [r3, #0]
 8002dc2:	6cd9      	ldr	r1, [r3, #76]	; 0x4c
 8002dc4:	687b      	ldr	r3, [r7, #4]
 8002dc6:	69da      	ldr	r2, [r3, #28]
 8002dc8:	687b      	ldr	r3, [r7, #4]
 8002dca:	695b      	ldr	r3, [r3, #20]
 8002dcc:	431a      	orrs	r2, r3
 8002dce:	687b      	ldr	r3, [r7, #4]
 8002dd0:	681b      	ldr	r3, [r3, #0]
 8002dd2:	430a      	orrs	r2, r1
 8002dd4:	64da      	str	r2, [r3, #76]	; 0x4c
#endif

        /* Enable the write protection for RTC registers */
        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8002dd6:	687b      	ldr	r3, [r7, #4]
 8002dd8:	681b      	ldr	r3, [r3, #0]
 8002dda:	22ff      	movs	r2, #255	; 0xff
 8002ddc:	625a      	str	r2, [r3, #36]	; 0x24

        hrtc->State = HAL_RTC_STATE_READY;
 8002dde:	687b      	ldr	r3, [r7, #4]
 8002de0:	2201      	movs	r2, #1
 8002de2:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
      }
    }
  }

  return status;
 8002de6:	7bfb      	ldrb	r3, [r7, #15]
}
 8002de8:	4618      	mov	r0, r3
 8002dea:	3710      	adds	r7, #16
 8002dec:	46bd      	mov	sp, r7
 8002dee:	bd80      	pop	{r7, pc}

08002df0 <HAL_RTC_WaitForSynchro>:
  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
  * @param  hrtc RTC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
{
 8002df0:	b580      	push	{r7, lr}
 8002df2:	b084      	sub	sp, #16
 8002df4:	af00      	add	r7, sp, #0
 8002df6:	6078      	str	r0, [r7, #4]

  /* Clear RSF flag */
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
  hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK;
#else
  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
 8002df8:	687b      	ldr	r3, [r7, #4]
 8002dfa:	681b      	ldr	r3, [r3, #0]
 8002dfc:	68da      	ldr	r2, [r3, #12]
 8002dfe:	687b      	ldr	r3, [r7, #4]
 8002e00:	681b      	ldr	r3, [r3, #0]
 8002e02:	f022 02a0 	bic.w	r2, r2, #160	; 0xa0
 8002e06:	60da      	str	r2, [r3, #12]
#endif

  tickstart = HAL_GetTick();
 8002e08:	f7fd ff7c 	bl	8000d04 <HAL_GetTick>
 8002e0c:	60f8      	str	r0, [r7, #12]

  /* Wait the registers to be synchronised */
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
  while ((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U)
#else
  while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
 8002e0e:	e009      	b.n	8002e24 <HAL_RTC_WaitForSynchro+0x34>
#endif
  {
    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
 8002e10:	f7fd ff78 	bl	8000d04 <HAL_GetTick>
 8002e14:	4602      	mov	r2, r0
 8002e16:	68fb      	ldr	r3, [r7, #12]
 8002e18:	1ad3      	subs	r3, r2, r3
 8002e1a:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
 8002e1e:	d901      	bls.n	8002e24 <HAL_RTC_WaitForSynchro+0x34>
    {
      return HAL_TIMEOUT;
 8002e20:	2303      	movs	r3, #3
 8002e22:	e007      	b.n	8002e34 <HAL_RTC_WaitForSynchro+0x44>
  while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
 8002e24:	687b      	ldr	r3, [r7, #4]
 8002e26:	681b      	ldr	r3, [r3, #0]
 8002e28:	68db      	ldr	r3, [r3, #12]
 8002e2a:	f003 0320 	and.w	r3, r3, #32
 8002e2e:	2b00      	cmp	r3, #0
 8002e30:	d0ee      	beq.n	8002e10 <HAL_RTC_WaitForSynchro+0x20>
    }
  }

  return HAL_OK;
 8002e32:	2300      	movs	r3, #0
}
 8002e34:	4618      	mov	r0, r3
 8002e36:	3710      	adds	r7, #16
 8002e38:	46bd      	mov	sp, r7
 8002e3a:	bd80      	pop	{r7, pc}

08002e3c <RTC_EnterInitMode>:
  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
  * @param  hrtc RTC handle
  * @retval HAL status
  */
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
{
 8002e3c:	b580      	push	{r7, lr}
 8002e3e:	b084      	sub	sp, #16
 8002e40:	af00      	add	r7, sp, #0
 8002e42:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 8002e44:	2300      	movs	r3, #0
 8002e46:	73fb      	strb	r3, [r7, #15]
        hrtc->State = HAL_RTC_STATE_TIMEOUT;
      }
    }
  }
#else /* #if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) */
  if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
 8002e48:	687b      	ldr	r3, [r7, #4]
 8002e4a:	681b      	ldr	r3, [r3, #0]
 8002e4c:	68db      	ldr	r3, [r3, #12]
 8002e4e:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002e52:	2b00      	cmp	r3, #0
 8002e54:	d120      	bne.n	8002e98 <RTC_EnterInitMode+0x5c>
  {
    /* Set the Initialization mode */
    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
 8002e56:	687b      	ldr	r3, [r7, #4]
 8002e58:	681b      	ldr	r3, [r3, #0]
 8002e5a:	f04f 32ff 	mov.w	r2, #4294967295
 8002e5e:	60da      	str	r2, [r3, #12]

    tickstart = HAL_GetTick();
 8002e60:	f7fd ff50 	bl	8000d04 <HAL_GetTick>
 8002e64:	60b8      	str	r0, [r7, #8]
    /* Wait till RTC is in INIT state and if Time out is reached exit */
    while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT))
 8002e66:	e00d      	b.n	8002e84 <RTC_EnterInitMode+0x48>
    {
      if ((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
 8002e68:	f7fd ff4c 	bl	8000d04 <HAL_GetTick>
 8002e6c:	4602      	mov	r2, r0
 8002e6e:	68bb      	ldr	r3, [r7, #8]
 8002e70:	1ad3      	subs	r3, r2, r3
 8002e72:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
 8002e76:	d905      	bls.n	8002e84 <RTC_EnterInitMode+0x48>
      {
        status = HAL_TIMEOUT;
 8002e78:	2303      	movs	r3, #3
 8002e7a:	73fb      	strb	r3, [r7, #15]
        hrtc->State = HAL_RTC_STATE_TIMEOUT;
 8002e7c:	687b      	ldr	r3, [r7, #4]
 8002e7e:	2203      	movs	r2, #3
 8002e80:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
    while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT))
 8002e84:	687b      	ldr	r3, [r7, #4]
 8002e86:	681b      	ldr	r3, [r3, #0]
 8002e88:	68db      	ldr	r3, [r3, #12]
 8002e8a:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002e8e:	2b00      	cmp	r3, #0
 8002e90:	d102      	bne.n	8002e98 <RTC_EnterInitMode+0x5c>
 8002e92:	7bfb      	ldrb	r3, [r7, #15]
 8002e94:	2b03      	cmp	r3, #3
 8002e96:	d1e7      	bne.n	8002e68 <RTC_EnterInitMode+0x2c>
      }
    }
  }
#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) */

  return status;
 8002e98:	7bfb      	ldrb	r3, [r7, #15]
}
 8002e9a:	4618      	mov	r0, r3
 8002e9c:	3710      	adds	r7, #16
 8002e9e:	46bd      	mov	sp, r7
 8002ea0:	bd80      	pop	{r7, pc}
	...

08002ea4 <RTC_ExitInitMode>:
  * @brief  Exit the RTC Initialization mode.
  * @param  hrtc RTC handle
  * @retval HAL status
  */
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
{
 8002ea4:	b580      	push	{r7, lr}
 8002ea6:	b084      	sub	sp, #16
 8002ea8:	af00      	add	r7, sp, #0
 8002eaa:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 8002eac:	2300      	movs	r3, #0
 8002eae:	73fb      	strb	r3, [r7, #15]
  /* Exit Initialization mode */
#if defined(STM32L412xx) || defined(STM32L422xx) || defined(STM32L4P5xx) || defined(STM32L4Q5xx)
  CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
#else
  /* Exit Initialization mode */
  CLEAR_BIT(RTC->ISR, RTC_ISR_INIT);
 8002eb0:	4b1a      	ldr	r3, [pc, #104]	; (8002f1c <RTC_ExitInitMode+0x78>)
 8002eb2:	68db      	ldr	r3, [r3, #12]
 8002eb4:	4a19      	ldr	r2, [pc, #100]	; (8002f1c <RTC_ExitInitMode+0x78>)
 8002eb6:	f023 0380 	bic.w	r3, r3, #128	; 0x80
 8002eba:	60d3      	str	r3, [r2, #12]
#endif

  /* If CR_BYPSHAD bit = 0, wait for synchro */
  if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
 8002ebc:	4b17      	ldr	r3, [pc, #92]	; (8002f1c <RTC_ExitInitMode+0x78>)
 8002ebe:	689b      	ldr	r3, [r3, #8]
 8002ec0:	f003 0320 	and.w	r3, r3, #32
 8002ec4:	2b00      	cmp	r3, #0
 8002ec6:	d10c      	bne.n	8002ee2 <RTC_ExitInitMode+0x3e>
  {
    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
 8002ec8:	6878      	ldr	r0, [r7, #4]
 8002eca:	f7ff ff91 	bl	8002df0 <HAL_RTC_WaitForSynchro>
 8002ece:	4603      	mov	r3, r0
 8002ed0:	2b00      	cmp	r3, #0
 8002ed2:	d01e      	beq.n	8002f12 <RTC_ExitInitMode+0x6e>
    {
      hrtc->State = HAL_RTC_STATE_TIMEOUT;
 8002ed4:	687b      	ldr	r3, [r7, #4]
 8002ed6:	2203      	movs	r2, #3
 8002ed8:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
      status = HAL_TIMEOUT;
 8002edc:	2303      	movs	r3, #3
 8002ede:	73fb      	strb	r3, [r7, #15]
 8002ee0:	e017      	b.n	8002f12 <RTC_ExitInitMode+0x6e>
    }
  }
  else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry */
  {
    /* Clear BYPSHAD bit */
    CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
 8002ee2:	4b0e      	ldr	r3, [pc, #56]	; (8002f1c <RTC_ExitInitMode+0x78>)
 8002ee4:	689b      	ldr	r3, [r3, #8]
 8002ee6:	4a0d      	ldr	r2, [pc, #52]	; (8002f1c <RTC_ExitInitMode+0x78>)
 8002ee8:	f023 0320 	bic.w	r3, r3, #32
 8002eec:	6093      	str	r3, [r2, #8]
    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
 8002eee:	6878      	ldr	r0, [r7, #4]
 8002ef0:	f7ff ff7e 	bl	8002df0 <HAL_RTC_WaitForSynchro>
 8002ef4:	4603      	mov	r3, r0
 8002ef6:	2b00      	cmp	r3, #0
 8002ef8:	d005      	beq.n	8002f06 <RTC_ExitInitMode+0x62>
    {
      hrtc->State = HAL_RTC_STATE_TIMEOUT;
 8002efa:	687b      	ldr	r3, [r7, #4]
 8002efc:	2203      	movs	r2, #3
 8002efe:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
      status = HAL_TIMEOUT;
 8002f02:	2303      	movs	r3, #3
 8002f04:	73fb      	strb	r3, [r7, #15]
    }
    /* Restore BYPSHAD bit */
    SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
 8002f06:	4b05      	ldr	r3, [pc, #20]	; (8002f1c <RTC_ExitInitMode+0x78>)
 8002f08:	689b      	ldr	r3, [r3, #8]
 8002f0a:	4a04      	ldr	r2, [pc, #16]	; (8002f1c <RTC_ExitInitMode+0x78>)
 8002f0c:	f043 0320 	orr.w	r3, r3, #32
 8002f10:	6093      	str	r3, [r2, #8]
  }

  return status;
 8002f12:	7bfb      	ldrb	r3, [r7, #15]
}
 8002f14:	4618      	mov	r0, r3
 8002f16:	3710      	adds	r7, #16
 8002f18:	46bd      	mov	sp, r7
 8002f1a:	bd80      	pop	{r7, pc}
 8002f1c:	40002800 	.word	0x40002800

08002f20 <HAL_TIM_Base_Init>:
  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
 8002f20:	b580      	push	{r7, lr}
 8002f22:	b082      	sub	sp, #8
 8002f24:	af00      	add	r7, sp, #0
 8002f26:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 8002f28:	687b      	ldr	r3, [r7, #4]
 8002f2a:	2b00      	cmp	r3, #0
 8002f2c:	d101      	bne.n	8002f32 <HAL_TIM_Base_Init+0x12>
  {
    return HAL_ERROR;
 8002f2e:	2301      	movs	r3, #1
 8002f30:	e049      	b.n	8002fc6 <HAL_TIM_Base_Init+0xa6>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 8002f32:	687b      	ldr	r3, [r7, #4]
 8002f34:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 8002f38:	b2db      	uxtb	r3, r3
 8002f3a:	2b00      	cmp	r3, #0
 8002f3c:	d106      	bne.n	8002f4c <HAL_TIM_Base_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 8002f3e:	687b      	ldr	r3, [r7, #4]
 8002f40:	2200      	movs	r2, #0
 8002f42:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
 8002f46:	6878      	ldr	r0, [r7, #4]
 8002f48:	f000 f841 	bl	8002fce <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8002f4c:	687b      	ldr	r3, [r7, #4]
 8002f4e:	2202      	movs	r2, #2
 8002f50:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8002f54:	687b      	ldr	r3, [r7, #4]
 8002f56:	681a      	ldr	r2, [r3, #0]
 8002f58:	687b      	ldr	r3, [r7, #4]
 8002f5a:	3304      	adds	r3, #4
 8002f5c:	4619      	mov	r1, r3
 8002f5e:	4610      	mov	r0, r2
 8002f60:	f000 f9f8 	bl	8003354 <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 8002f64:	687b      	ldr	r3, [r7, #4]
 8002f66:	2201      	movs	r2, #1
 8002f68:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8002f6c:	687b      	ldr	r3, [r7, #4]
 8002f6e:	2201      	movs	r2, #1
 8002f70:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
 8002f74:	687b      	ldr	r3, [r7, #4]
 8002f76:	2201      	movs	r2, #1
 8002f78:	f883 203f 	strb.w	r2, [r3, #63]	; 0x3f
 8002f7c:	687b      	ldr	r3, [r7, #4]
 8002f7e:	2201      	movs	r2, #1
 8002f80:	f883 2040 	strb.w	r2, [r3, #64]	; 0x40
 8002f84:	687b      	ldr	r3, [r7, #4]
 8002f86:	2201      	movs	r2, #1
 8002f88:	f883 2041 	strb.w	r2, [r3, #65]	; 0x41
 8002f8c:	687b      	ldr	r3, [r7, #4]
 8002f8e:	2201      	movs	r2, #1
 8002f90:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
 8002f94:	687b      	ldr	r3, [r7, #4]
 8002f96:	2201      	movs	r2, #1
 8002f98:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8002f9c:	687b      	ldr	r3, [r7, #4]
 8002f9e:	2201      	movs	r2, #1
 8002fa0:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
 8002fa4:	687b      	ldr	r3, [r7, #4]
 8002fa6:	2201      	movs	r2, #1
 8002fa8:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
 8002fac:	687b      	ldr	r3, [r7, #4]
 8002fae:	2201      	movs	r2, #1
 8002fb0:	f883 2046 	strb.w	r2, [r3, #70]	; 0x46
 8002fb4:	687b      	ldr	r3, [r7, #4]
 8002fb6:	2201      	movs	r2, #1
 8002fb8:	f883 2047 	strb.w	r2, [r3, #71]	; 0x47

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 8002fbc:	687b      	ldr	r3, [r7, #4]
 8002fbe:	2201      	movs	r2, #1
 8002fc0:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  return HAL_OK;
 8002fc4:	2300      	movs	r3, #0
}
 8002fc6:	4618      	mov	r0, r3
 8002fc8:	3708      	adds	r7, #8
 8002fca:	46bd      	mov	sp, r7
 8002fcc:	bd80      	pop	{r7, pc}

08002fce <HAL_TIM_Base_MspInit>:
  * @brief  Initializes the TIM Base MSP.
  * @param  htim TIM Base handle
  * @retval None
  */
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
 8002fce:	b480      	push	{r7}
 8002fd0:	b083      	sub	sp, #12
 8002fd2:	af00      	add	r7, sp, #0
 8002fd4:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_Base_MspInit could be implemented in the user file
   */
}
 8002fd6:	bf00      	nop
 8002fd8:	370c      	adds	r7, #12
 8002fda:	46bd      	mov	sp, r7
 8002fdc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002fe0:	4770      	bx	lr
	...

08002fe4 <HAL_TIM_Base_Start_IT>:
  * @brief  Starts the TIM Base generation in interrupt mode.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
 8002fe4:	b480      	push	{r7}
 8002fe6:	b085      	sub	sp, #20
 8002fe8:	af00      	add	r7, sp, #0
 8002fea:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 8002fec:	687b      	ldr	r3, [r7, #4]
 8002fee:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 8002ff2:	b2db      	uxtb	r3, r3
 8002ff4:	2b01      	cmp	r3, #1
 8002ff6:	d001      	beq.n	8002ffc <HAL_TIM_Base_Start_IT+0x18>
  {
    return HAL_ERROR;
 8002ff8:	2301      	movs	r3, #1
 8002ffa:	e04f      	b.n	800309c <HAL_TIM_Base_Start_IT+0xb8>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8002ffc:	687b      	ldr	r3, [r7, #4]
 8002ffe:	2202      	movs	r2, #2
 8003000:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 8003004:	687b      	ldr	r3, [r7, #4]
 8003006:	681b      	ldr	r3, [r3, #0]
 8003008:	68da      	ldr	r2, [r3, #12]
 800300a:	687b      	ldr	r3, [r7, #4]
 800300c:	681b      	ldr	r3, [r3, #0]
 800300e:	f042 0201 	orr.w	r2, r2, #1
 8003012:	60da      	str	r2, [r3, #12]

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8003014:	687b      	ldr	r3, [r7, #4]
 8003016:	681b      	ldr	r3, [r3, #0]
 8003018:	4a23      	ldr	r2, [pc, #140]	; (80030a8 <HAL_TIM_Base_Start_IT+0xc4>)
 800301a:	4293      	cmp	r3, r2
 800301c:	d01d      	beq.n	800305a <HAL_TIM_Base_Start_IT+0x76>
 800301e:	687b      	ldr	r3, [r7, #4]
 8003020:	681b      	ldr	r3, [r3, #0]
 8003022:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8003026:	d018      	beq.n	800305a <HAL_TIM_Base_Start_IT+0x76>
 8003028:	687b      	ldr	r3, [r7, #4]
 800302a:	681b      	ldr	r3, [r3, #0]
 800302c:	4a1f      	ldr	r2, [pc, #124]	; (80030ac <HAL_TIM_Base_Start_IT+0xc8>)
 800302e:	4293      	cmp	r3, r2
 8003030:	d013      	beq.n	800305a <HAL_TIM_Base_Start_IT+0x76>
 8003032:	687b      	ldr	r3, [r7, #4]
 8003034:	681b      	ldr	r3, [r3, #0]
 8003036:	4a1e      	ldr	r2, [pc, #120]	; (80030b0 <HAL_TIM_Base_Start_IT+0xcc>)
 8003038:	4293      	cmp	r3, r2
 800303a:	d00e      	beq.n	800305a <HAL_TIM_Base_Start_IT+0x76>
 800303c:	687b      	ldr	r3, [r7, #4]
 800303e:	681b      	ldr	r3, [r3, #0]
 8003040:	4a1c      	ldr	r2, [pc, #112]	; (80030b4 <HAL_TIM_Base_Start_IT+0xd0>)
 8003042:	4293      	cmp	r3, r2
 8003044:	d009      	beq.n	800305a <HAL_TIM_Base_Start_IT+0x76>
 8003046:	687b      	ldr	r3, [r7, #4]
 8003048:	681b      	ldr	r3, [r3, #0]
 800304a:	4a1b      	ldr	r2, [pc, #108]	; (80030b8 <HAL_TIM_Base_Start_IT+0xd4>)
 800304c:	4293      	cmp	r3, r2
 800304e:	d004      	beq.n	800305a <HAL_TIM_Base_Start_IT+0x76>
 8003050:	687b      	ldr	r3, [r7, #4]
 8003052:	681b      	ldr	r3, [r3, #0]
 8003054:	4a19      	ldr	r2, [pc, #100]	; (80030bc <HAL_TIM_Base_Start_IT+0xd8>)
 8003056:	4293      	cmp	r3, r2
 8003058:	d115      	bne.n	8003086 <HAL_TIM_Base_Start_IT+0xa2>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 800305a:	687b      	ldr	r3, [r7, #4]
 800305c:	681b      	ldr	r3, [r3, #0]
 800305e:	689a      	ldr	r2, [r3, #8]
 8003060:	4b17      	ldr	r3, [pc, #92]	; (80030c0 <HAL_TIM_Base_Start_IT+0xdc>)
 8003062:	4013      	ands	r3, r2
 8003064:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8003066:	68fb      	ldr	r3, [r7, #12]
 8003068:	2b06      	cmp	r3, #6
 800306a:	d015      	beq.n	8003098 <HAL_TIM_Base_Start_IT+0xb4>
 800306c:	68fb      	ldr	r3, [r7, #12]
 800306e:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8003072:	d011      	beq.n	8003098 <HAL_TIM_Base_Start_IT+0xb4>
    {
      __HAL_TIM_ENABLE(htim);
 8003074:	687b      	ldr	r3, [r7, #4]
 8003076:	681b      	ldr	r3, [r3, #0]
 8003078:	681a      	ldr	r2, [r3, #0]
 800307a:	687b      	ldr	r3, [r7, #4]
 800307c:	681b      	ldr	r3, [r3, #0]
 800307e:	f042 0201 	orr.w	r2, r2, #1
 8003082:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8003084:	e008      	b.n	8003098 <HAL_TIM_Base_Start_IT+0xb4>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 8003086:	687b      	ldr	r3, [r7, #4]
 8003088:	681b      	ldr	r3, [r3, #0]
 800308a:	681a      	ldr	r2, [r3, #0]
 800308c:	687b      	ldr	r3, [r7, #4]
 800308e:	681b      	ldr	r3, [r3, #0]
 8003090:	f042 0201 	orr.w	r2, r2, #1
 8003094:	601a      	str	r2, [r3, #0]
 8003096:	e000      	b.n	800309a <HAL_TIM_Base_Start_IT+0xb6>
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8003098:	bf00      	nop
  }

  /* Return function status */
  return HAL_OK;
 800309a:	2300      	movs	r3, #0
}
 800309c:	4618      	mov	r0, r3
 800309e:	3714      	adds	r7, #20
 80030a0:	46bd      	mov	sp, r7
 80030a2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80030a6:	4770      	bx	lr
 80030a8:	40012c00 	.word	0x40012c00
 80030ac:	40000400 	.word	0x40000400
 80030b0:	40000800 	.word	0x40000800
 80030b4:	40000c00 	.word	0x40000c00
 80030b8:	40013400 	.word	0x40013400
 80030bc:	40014000 	.word	0x40014000
 80030c0:	00010007 	.word	0x00010007

080030c4 <HAL_TIM_IRQHandler>:
  * @brief  This function handles TIM interrupts requests.
  * @param  htim TIM  handle
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
 80030c4:	b580      	push	{r7, lr}
 80030c6:	b082      	sub	sp, #8
 80030c8:	af00      	add	r7, sp, #0
 80030ca:	6078      	str	r0, [r7, #4]
  /* Capture compare 1 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80030cc:	687b      	ldr	r3, [r7, #4]
 80030ce:	681b      	ldr	r3, [r3, #0]
 80030d0:	691b      	ldr	r3, [r3, #16]
 80030d2:	f003 0302 	and.w	r3, r3, #2
 80030d6:	2b02      	cmp	r3, #2
 80030d8:	d122      	bne.n	8003120 <HAL_TIM_IRQHandler+0x5c>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
 80030da:	687b      	ldr	r3, [r7, #4]
 80030dc:	681b      	ldr	r3, [r3, #0]
 80030de:	68db      	ldr	r3, [r3, #12]
 80030e0:	f003 0302 	and.w	r3, r3, #2
 80030e4:	2b02      	cmp	r3, #2
 80030e6:	d11b      	bne.n	8003120 <HAL_TIM_IRQHandler+0x5c>
    {
      {
        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
 80030e8:	687b      	ldr	r3, [r7, #4]
 80030ea:	681b      	ldr	r3, [r3, #0]
 80030ec:	f06f 0202 	mvn.w	r2, #2
 80030f0:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80030f2:	687b      	ldr	r3, [r7, #4]
 80030f4:	2201      	movs	r2, #1
 80030f6:	771a      	strb	r2, [r3, #28]

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80030f8:	687b      	ldr	r3, [r7, #4]
 80030fa:	681b      	ldr	r3, [r3, #0]
 80030fc:	699b      	ldr	r3, [r3, #24]
 80030fe:	f003 0303 	and.w	r3, r3, #3
 8003102:	2b00      	cmp	r3, #0
 8003104:	d003      	beq.n	800310e <HAL_TIM_IRQHandler+0x4a>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 8003106:	6878      	ldr	r0, [r7, #4]
 8003108:	f000 f905 	bl	8003316 <HAL_TIM_IC_CaptureCallback>
 800310c:	e005      	b.n	800311a <HAL_TIM_IRQHandler+0x56>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->OC_DelayElapsedCallback(htim);
          htim->PWM_PulseFinishedCallback(htim);
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
 800310e:	6878      	ldr	r0, [r7, #4]
 8003110:	f000 f8f7 	bl	8003302 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 8003114:	6878      	ldr	r0, [r7, #4]
 8003116:	f000 f908 	bl	800332a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800311a:	687b      	ldr	r3, [r7, #4]
 800311c:	2200      	movs	r2, #0
 800311e:	771a      	strb	r2, [r3, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
 8003120:	687b      	ldr	r3, [r7, #4]
 8003122:	681b      	ldr	r3, [r3, #0]
 8003124:	691b      	ldr	r3, [r3, #16]
 8003126:	f003 0304 	and.w	r3, r3, #4
 800312a:	2b04      	cmp	r3, #4
 800312c:	d122      	bne.n	8003174 <HAL_TIM_IRQHandler+0xb0>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
 800312e:	687b      	ldr	r3, [r7, #4]
 8003130:	681b      	ldr	r3, [r3, #0]
 8003132:	68db      	ldr	r3, [r3, #12]
 8003134:	f003 0304 	and.w	r3, r3, #4
 8003138:	2b04      	cmp	r3, #4
 800313a:	d11b      	bne.n	8003174 <HAL_TIM_IRQHandler+0xb0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
 800313c:	687b      	ldr	r3, [r7, #4]
 800313e:	681b      	ldr	r3, [r3, #0]
 8003140:	f06f 0204 	mvn.w	r2, #4
 8003144:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8003146:	687b      	ldr	r3, [r7, #4]
 8003148:	2202      	movs	r2, #2
 800314a:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800314c:	687b      	ldr	r3, [r7, #4]
 800314e:	681b      	ldr	r3, [r3, #0]
 8003150:	699b      	ldr	r3, [r3, #24]
 8003152:	f403 7340 	and.w	r3, r3, #768	; 0x300
 8003156:	2b00      	cmp	r3, #0
 8003158:	d003      	beq.n	8003162 <HAL_TIM_IRQHandler+0x9e>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800315a:	6878      	ldr	r0, [r7, #4]
 800315c:	f000 f8db 	bl	8003316 <HAL_TIM_IC_CaptureCallback>
 8003160:	e005      	b.n	800316e <HAL_TIM_IRQHandler+0xaa>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8003162:	6878      	ldr	r0, [r7, #4]
 8003164:	f000 f8cd 	bl	8003302 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8003168:	6878      	ldr	r0, [r7, #4]
 800316a:	f000 f8de 	bl	800332a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800316e:	687b      	ldr	r3, [r7, #4]
 8003170:	2200      	movs	r2, #0
 8003172:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 3 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
 8003174:	687b      	ldr	r3, [r7, #4]
 8003176:	681b      	ldr	r3, [r3, #0]
 8003178:	691b      	ldr	r3, [r3, #16]
 800317a:	f003 0308 	and.w	r3, r3, #8
 800317e:	2b08      	cmp	r3, #8
 8003180:	d122      	bne.n	80031c8 <HAL_TIM_IRQHandler+0x104>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
 8003182:	687b      	ldr	r3, [r7, #4]
 8003184:	681b      	ldr	r3, [r3, #0]
 8003186:	68db      	ldr	r3, [r3, #12]
 8003188:	f003 0308 	and.w	r3, r3, #8
 800318c:	2b08      	cmp	r3, #8
 800318e:	d11b      	bne.n	80031c8 <HAL_TIM_IRQHandler+0x104>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
 8003190:	687b      	ldr	r3, [r7, #4]
 8003192:	681b      	ldr	r3, [r3, #0]
 8003194:	f06f 0208 	mvn.w	r2, #8
 8003198:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 800319a:	687b      	ldr	r3, [r7, #4]
 800319c:	2204      	movs	r2, #4
 800319e:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 80031a0:	687b      	ldr	r3, [r7, #4]
 80031a2:	681b      	ldr	r3, [r3, #0]
 80031a4:	69db      	ldr	r3, [r3, #28]
 80031a6:	f003 0303 	and.w	r3, r3, #3
 80031aa:	2b00      	cmp	r3, #0
 80031ac:	d003      	beq.n	80031b6 <HAL_TIM_IRQHandler+0xf2>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 80031ae:	6878      	ldr	r0, [r7, #4]
 80031b0:	f000 f8b1 	bl	8003316 <HAL_TIM_IC_CaptureCallback>
 80031b4:	e005      	b.n	80031c2 <HAL_TIM_IRQHandler+0xfe>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80031b6:	6878      	ldr	r0, [r7, #4]
 80031b8:	f000 f8a3 	bl	8003302 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80031bc:	6878      	ldr	r0, [r7, #4]
 80031be:	f000 f8b4 	bl	800332a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80031c2:	687b      	ldr	r3, [r7, #4]
 80031c4:	2200      	movs	r2, #0
 80031c6:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 4 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
 80031c8:	687b      	ldr	r3, [r7, #4]
 80031ca:	681b      	ldr	r3, [r3, #0]
 80031cc:	691b      	ldr	r3, [r3, #16]
 80031ce:	f003 0310 	and.w	r3, r3, #16
 80031d2:	2b10      	cmp	r3, #16
 80031d4:	d122      	bne.n	800321c <HAL_TIM_IRQHandler+0x158>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
 80031d6:	687b      	ldr	r3, [r7, #4]
 80031d8:	681b      	ldr	r3, [r3, #0]
 80031da:	68db      	ldr	r3, [r3, #12]
 80031dc:	f003 0310 	and.w	r3, r3, #16
 80031e0:	2b10      	cmp	r3, #16
 80031e2:	d11b      	bne.n	800321c <HAL_TIM_IRQHandler+0x158>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
 80031e4:	687b      	ldr	r3, [r7, #4]
 80031e6:	681b      	ldr	r3, [r3, #0]
 80031e8:	f06f 0210 	mvn.w	r2, #16
 80031ec:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 80031ee:	687b      	ldr	r3, [r7, #4]
 80031f0:	2208      	movs	r2, #8
 80031f2:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 80031f4:	687b      	ldr	r3, [r7, #4]
 80031f6:	681b      	ldr	r3, [r3, #0]
 80031f8:	69db      	ldr	r3, [r3, #28]
 80031fa:	f403 7340 	and.w	r3, r3, #768	; 0x300
 80031fe:	2b00      	cmp	r3, #0
 8003200:	d003      	beq.n	800320a <HAL_TIM_IRQHandler+0x146>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8003202:	6878      	ldr	r0, [r7, #4]
 8003204:	f000 f887 	bl	8003316 <HAL_TIM_IC_CaptureCallback>
 8003208:	e005      	b.n	8003216 <HAL_TIM_IRQHandler+0x152>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800320a:	6878      	ldr	r0, [r7, #4]
 800320c:	f000 f879 	bl	8003302 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8003210:	6878      	ldr	r0, [r7, #4]
 8003212:	f000 f88a 	bl	800332a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8003216:	687b      	ldr	r3, [r7, #4]
 8003218:	2200      	movs	r2, #0
 800321a:	771a      	strb	r2, [r3, #28]
    }
  }
  /* TIM Update event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
 800321c:	687b      	ldr	r3, [r7, #4]
 800321e:	681b      	ldr	r3, [r3, #0]
 8003220:	691b      	ldr	r3, [r3, #16]
 8003222:	f003 0301 	and.w	r3, r3, #1
 8003226:	2b01      	cmp	r3, #1
 8003228:	d10e      	bne.n	8003248 <HAL_TIM_IRQHandler+0x184>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
 800322a:	687b      	ldr	r3, [r7, #4]
 800322c:	681b      	ldr	r3, [r3, #0]
 800322e:	68db      	ldr	r3, [r3, #12]
 8003230:	f003 0301 	and.w	r3, r3, #1
 8003234:	2b01      	cmp	r3, #1
 8003236:	d107      	bne.n	8003248 <HAL_TIM_IRQHandler+0x184>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 8003238:	687b      	ldr	r3, [r7, #4]
 800323a:	681b      	ldr	r3, [r3, #0]
 800323c:	f06f 0201 	mvn.w	r2, #1
 8003240:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 8003242:	6878      	ldr	r0, [r7, #4]
 8003244:	f7fd fa96 	bl	8000774 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break input event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
 8003248:	687b      	ldr	r3, [r7, #4]
 800324a:	681b      	ldr	r3, [r3, #0]
 800324c:	691b      	ldr	r3, [r3, #16]
 800324e:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8003252:	2b80      	cmp	r3, #128	; 0x80
 8003254:	d10e      	bne.n	8003274 <HAL_TIM_IRQHandler+0x1b0>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
 8003256:	687b      	ldr	r3, [r7, #4]
 8003258:	681b      	ldr	r3, [r3, #0]
 800325a:	68db      	ldr	r3, [r3, #12]
 800325c:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8003260:	2b80      	cmp	r3, #128	; 0x80
 8003262:	d107      	bne.n	8003274 <HAL_TIM_IRQHandler+0x1b0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 8003264:	687b      	ldr	r3, [r7, #4]
 8003266:	681b      	ldr	r3, [r3, #0]
 8003268:	f06f 0280 	mvn.w	r2, #128	; 0x80
 800326c:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->BreakCallback(htim);
#else
      HAL_TIMEx_BreakCallback(htim);
 800326e:	6878      	ldr	r0, [r7, #4]
 8003270:	f000 f914 	bl	800349c <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break2 input event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
 8003274:	687b      	ldr	r3, [r7, #4]
 8003276:	681b      	ldr	r3, [r3, #0]
 8003278:	691b      	ldr	r3, [r3, #16]
 800327a:	f403 7380 	and.w	r3, r3, #256	; 0x100
 800327e:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
 8003282:	d10e      	bne.n	80032a2 <HAL_TIM_IRQHandler+0x1de>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
 8003284:	687b      	ldr	r3, [r7, #4]
 8003286:	681b      	ldr	r3, [r3, #0]
 8003288:	68db      	ldr	r3, [r3, #12]
 800328a:	f003 0380 	and.w	r3, r3, #128	; 0x80
 800328e:	2b80      	cmp	r3, #128	; 0x80
 8003290:	d107      	bne.n	80032a2 <HAL_TIM_IRQHandler+0x1de>
    {
      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
 8003292:	687b      	ldr	r3, [r7, #4]
 8003294:	681b      	ldr	r3, [r3, #0]
 8003296:	f46f 7280 	mvn.w	r2, #256	; 0x100
 800329a:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->Break2Callback(htim);
#else
      HAL_TIMEx_Break2Callback(htim);
 800329c:	6878      	ldr	r0, [r7, #4]
 800329e:	f000 f907 	bl	80034b0 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
 80032a2:	687b      	ldr	r3, [r7, #4]
 80032a4:	681b      	ldr	r3, [r3, #0]
 80032a6:	691b      	ldr	r3, [r3, #16]
 80032a8:	f003 0340 	and.w	r3, r3, #64	; 0x40
 80032ac:	2b40      	cmp	r3, #64	; 0x40
 80032ae:	d10e      	bne.n	80032ce <HAL_TIM_IRQHandler+0x20a>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
 80032b0:	687b      	ldr	r3, [r7, #4]
 80032b2:	681b      	ldr	r3, [r3, #0]
 80032b4:	68db      	ldr	r3, [r3, #12]
 80032b6:	f003 0340 	and.w	r3, r3, #64	; 0x40
 80032ba:	2b40      	cmp	r3, #64	; 0x40
 80032bc:	d107      	bne.n	80032ce <HAL_TIM_IRQHandler+0x20a>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 80032be:	687b      	ldr	r3, [r7, #4]
 80032c0:	681b      	ldr	r3, [r3, #0]
 80032c2:	f06f 0240 	mvn.w	r2, #64	; 0x40
 80032c6:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 80032c8:	6878      	ldr	r0, [r7, #4]
 80032ca:	f000 f838 	bl	800333e <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM commutation event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
 80032ce:	687b      	ldr	r3, [r7, #4]
 80032d0:	681b      	ldr	r3, [r3, #0]
 80032d2:	691b      	ldr	r3, [r3, #16]
 80032d4:	f003 0320 	and.w	r3, r3, #32
 80032d8:	2b20      	cmp	r3, #32
 80032da:	d10e      	bne.n	80032fa <HAL_TIM_IRQHandler+0x236>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
 80032dc:	687b      	ldr	r3, [r7, #4]
 80032de:	681b      	ldr	r3, [r3, #0]
 80032e0:	68db      	ldr	r3, [r3, #12]
 80032e2:	f003 0320 	and.w	r3, r3, #32
 80032e6:	2b20      	cmp	r3, #32
 80032e8:	d107      	bne.n	80032fa <HAL_TIM_IRQHandler+0x236>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 80032ea:	687b      	ldr	r3, [r7, #4]
 80032ec:	681b      	ldr	r3, [r3, #0]
 80032ee:	f06f 0220 	mvn.w	r2, #32
 80032f2:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->CommutationCallback(htim);
#else
      HAL_TIMEx_CommutCallback(htim);
 80032f4:	6878      	ldr	r0, [r7, #4]
 80032f6:	f000 f8c7 	bl	8003488 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 80032fa:	bf00      	nop
 80032fc:	3708      	adds	r7, #8
 80032fe:	46bd      	mov	sp, r7
 8003300:	bd80      	pop	{r7, pc}

08003302 <HAL_TIM_OC_DelayElapsedCallback>:
  * @brief  Output Compare callback in non-blocking mode
  * @param  htim TIM OC handle
  * @retval None
  */
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
 8003302:	b480      	push	{r7}
 8003304:	b083      	sub	sp, #12
 8003306:	af00      	add	r7, sp, #0
 8003308:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
   */
}
 800330a:	bf00      	nop
 800330c:	370c      	adds	r7, #12
 800330e:	46bd      	mov	sp, r7
 8003310:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003314:	4770      	bx	lr

08003316 <HAL_TIM_IC_CaptureCallback>:
  * @brief  Input Capture callback in non-blocking mode
  * @param  htim TIM IC handle
  * @retval None
  */
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
 8003316:	b480      	push	{r7}
 8003318:	b083      	sub	sp, #12
 800331a:	af00      	add	r7, sp, #0
 800331c:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
   */
}
 800331e:	bf00      	nop
 8003320:	370c      	adds	r7, #12
 8003322:	46bd      	mov	sp, r7
 8003324:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003328:	4770      	bx	lr

0800332a <HAL_TIM_PWM_PulseFinishedCallback>:
  * @brief  PWM Pulse finished callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
 800332a:	b480      	push	{r7}
 800332c:	b083      	sub	sp, #12
 800332e:	af00      	add	r7, sp, #0
 8003330:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
   */
}
 8003332:	bf00      	nop
 8003334:	370c      	adds	r7, #12
 8003336:	46bd      	mov	sp, r7
 8003338:	f85d 7b04 	ldr.w	r7, [sp], #4
 800333c:	4770      	bx	lr

0800333e <HAL_TIM_TriggerCallback>:
  * @brief  Hall Trigger detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
 800333e:	b480      	push	{r7}
 8003340:	b083      	sub	sp, #12
 8003342:	af00      	add	r7, sp, #0
 8003344:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerCallback could be implemented in the user file
   */
}
 8003346:	bf00      	nop
 8003348:	370c      	adds	r7, #12
 800334a:	46bd      	mov	sp, r7
 800334c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003350:	4770      	bx	lr
	...

08003354 <TIM_Base_SetConfig>:
  * @param  TIMx TIM peripheral
  * @param  Structure TIM Base configuration structure
  * @retval None
  */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
 8003354:	b480      	push	{r7}
 8003356:	b085      	sub	sp, #20
 8003358:	af00      	add	r7, sp, #0
 800335a:	6078      	str	r0, [r7, #4]
 800335c:	6039      	str	r1, [r7, #0]
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;
 800335e:	687b      	ldr	r3, [r7, #4]
 8003360:	681b      	ldr	r3, [r3, #0]
 8003362:	60fb      	str	r3, [r7, #12]

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8003364:	687b      	ldr	r3, [r7, #4]
 8003366:	4a40      	ldr	r2, [pc, #256]	; (8003468 <TIM_Base_SetConfig+0x114>)
 8003368:	4293      	cmp	r3, r2
 800336a:	d013      	beq.n	8003394 <TIM_Base_SetConfig+0x40>
 800336c:	687b      	ldr	r3, [r7, #4]
 800336e:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8003372:	d00f      	beq.n	8003394 <TIM_Base_SetConfig+0x40>
 8003374:	687b      	ldr	r3, [r7, #4]
 8003376:	4a3d      	ldr	r2, [pc, #244]	; (800346c <TIM_Base_SetConfig+0x118>)
 8003378:	4293      	cmp	r3, r2
 800337a:	d00b      	beq.n	8003394 <TIM_Base_SetConfig+0x40>
 800337c:	687b      	ldr	r3, [r7, #4]
 800337e:	4a3c      	ldr	r2, [pc, #240]	; (8003470 <TIM_Base_SetConfig+0x11c>)
 8003380:	4293      	cmp	r3, r2
 8003382:	d007      	beq.n	8003394 <TIM_Base_SetConfig+0x40>
 8003384:	687b      	ldr	r3, [r7, #4]
 8003386:	4a3b      	ldr	r2, [pc, #236]	; (8003474 <TIM_Base_SetConfig+0x120>)
 8003388:	4293      	cmp	r3, r2
 800338a:	d003      	beq.n	8003394 <TIM_Base_SetConfig+0x40>
 800338c:	687b      	ldr	r3, [r7, #4]
 800338e:	4a3a      	ldr	r2, [pc, #232]	; (8003478 <TIM_Base_SetConfig+0x124>)
 8003390:	4293      	cmp	r3, r2
 8003392:	d108      	bne.n	80033a6 <TIM_Base_SetConfig+0x52>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8003394:	68fb      	ldr	r3, [r7, #12]
 8003396:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 800339a:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= Structure->CounterMode;
 800339c:	683b      	ldr	r3, [r7, #0]
 800339e:	685b      	ldr	r3, [r3, #4]
 80033a0:	68fa      	ldr	r2, [r7, #12]
 80033a2:	4313      	orrs	r3, r2
 80033a4:	60fb      	str	r3, [r7, #12]
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 80033a6:	687b      	ldr	r3, [r7, #4]
 80033a8:	4a2f      	ldr	r2, [pc, #188]	; (8003468 <TIM_Base_SetConfig+0x114>)
 80033aa:	4293      	cmp	r3, r2
 80033ac:	d01f      	beq.n	80033ee <TIM_Base_SetConfig+0x9a>
 80033ae:	687b      	ldr	r3, [r7, #4]
 80033b0:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 80033b4:	d01b      	beq.n	80033ee <TIM_Base_SetConfig+0x9a>
 80033b6:	687b      	ldr	r3, [r7, #4]
 80033b8:	4a2c      	ldr	r2, [pc, #176]	; (800346c <TIM_Base_SetConfig+0x118>)
 80033ba:	4293      	cmp	r3, r2
 80033bc:	d017      	beq.n	80033ee <TIM_Base_SetConfig+0x9a>
 80033be:	687b      	ldr	r3, [r7, #4]
 80033c0:	4a2b      	ldr	r2, [pc, #172]	; (8003470 <TIM_Base_SetConfig+0x11c>)
 80033c2:	4293      	cmp	r3, r2
 80033c4:	d013      	beq.n	80033ee <TIM_Base_SetConfig+0x9a>
 80033c6:	687b      	ldr	r3, [r7, #4]
 80033c8:	4a2a      	ldr	r2, [pc, #168]	; (8003474 <TIM_Base_SetConfig+0x120>)
 80033ca:	4293      	cmp	r3, r2
 80033cc:	d00f      	beq.n	80033ee <TIM_Base_SetConfig+0x9a>
 80033ce:	687b      	ldr	r3, [r7, #4]
 80033d0:	4a29      	ldr	r2, [pc, #164]	; (8003478 <TIM_Base_SetConfig+0x124>)
 80033d2:	4293      	cmp	r3, r2
 80033d4:	d00b      	beq.n	80033ee <TIM_Base_SetConfig+0x9a>
 80033d6:	687b      	ldr	r3, [r7, #4]
 80033d8:	4a28      	ldr	r2, [pc, #160]	; (800347c <TIM_Base_SetConfig+0x128>)
 80033da:	4293      	cmp	r3, r2
 80033dc:	d007      	beq.n	80033ee <TIM_Base_SetConfig+0x9a>
 80033de:	687b      	ldr	r3, [r7, #4]
 80033e0:	4a27      	ldr	r2, [pc, #156]	; (8003480 <TIM_Base_SetConfig+0x12c>)
 80033e2:	4293      	cmp	r3, r2
 80033e4:	d003      	beq.n	80033ee <TIM_Base_SetConfig+0x9a>
 80033e6:	687b      	ldr	r3, [r7, #4]
 80033e8:	4a26      	ldr	r2, [pc, #152]	; (8003484 <TIM_Base_SetConfig+0x130>)
 80033ea:	4293      	cmp	r3, r2
 80033ec:	d108      	bne.n	8003400 <TIM_Base_SetConfig+0xac>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
 80033ee:	68fb      	ldr	r3, [r7, #12]
 80033f0:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 80033f4:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 80033f6:	683b      	ldr	r3, [r7, #0]
 80033f8:	68db      	ldr	r3, [r3, #12]
 80033fa:	68fa      	ldr	r2, [r7, #12]
 80033fc:	4313      	orrs	r3, r2
 80033fe:	60fb      	str	r3, [r7, #12]
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8003400:	68fb      	ldr	r3, [r7, #12]
 8003402:	f023 0280 	bic.w	r2, r3, #128	; 0x80
 8003406:	683b      	ldr	r3, [r7, #0]
 8003408:	695b      	ldr	r3, [r3, #20]
 800340a:	4313      	orrs	r3, r2
 800340c:	60fb      	str	r3, [r7, #12]

  TIMx->CR1 = tmpcr1;
 800340e:	687b      	ldr	r3, [r7, #4]
 8003410:	68fa      	ldr	r2, [r7, #12]
 8003412:	601a      	str	r2, [r3, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8003414:	683b      	ldr	r3, [r7, #0]
 8003416:	689a      	ldr	r2, [r3, #8]
 8003418:	687b      	ldr	r3, [r7, #4]
 800341a:	62da      	str	r2, [r3, #44]	; 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 800341c:	683b      	ldr	r3, [r7, #0]
 800341e:	681a      	ldr	r2, [r3, #0]
 8003420:	687b      	ldr	r3, [r7, #4]
 8003422:	629a      	str	r2, [r3, #40]	; 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 8003424:	687b      	ldr	r3, [r7, #4]
 8003426:	4a10      	ldr	r2, [pc, #64]	; (8003468 <TIM_Base_SetConfig+0x114>)
 8003428:	4293      	cmp	r3, r2
 800342a:	d00f      	beq.n	800344c <TIM_Base_SetConfig+0xf8>
 800342c:	687b      	ldr	r3, [r7, #4]
 800342e:	4a12      	ldr	r2, [pc, #72]	; (8003478 <TIM_Base_SetConfig+0x124>)
 8003430:	4293      	cmp	r3, r2
 8003432:	d00b      	beq.n	800344c <TIM_Base_SetConfig+0xf8>
 8003434:	687b      	ldr	r3, [r7, #4]
 8003436:	4a11      	ldr	r2, [pc, #68]	; (800347c <TIM_Base_SetConfig+0x128>)
 8003438:	4293      	cmp	r3, r2
 800343a:	d007      	beq.n	800344c <TIM_Base_SetConfig+0xf8>
 800343c:	687b      	ldr	r3, [r7, #4]
 800343e:	4a10      	ldr	r2, [pc, #64]	; (8003480 <TIM_Base_SetConfig+0x12c>)
 8003440:	4293      	cmp	r3, r2
 8003442:	d003      	beq.n	800344c <TIM_Base_SetConfig+0xf8>
 8003444:	687b      	ldr	r3, [r7, #4]
 8003446:	4a0f      	ldr	r2, [pc, #60]	; (8003484 <TIM_Base_SetConfig+0x130>)
 8003448:	4293      	cmp	r3, r2
 800344a:	d103      	bne.n	8003454 <TIM_Base_SetConfig+0x100>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 800344c:	683b      	ldr	r3, [r7, #0]
 800344e:	691a      	ldr	r2, [r3, #16]
 8003450:	687b      	ldr	r3, [r7, #4]
 8003452:	631a      	str	r2, [r3, #48]	; 0x30
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 8003454:	687b      	ldr	r3, [r7, #4]
 8003456:	2201      	movs	r2, #1
 8003458:	615a      	str	r2, [r3, #20]
}
 800345a:	bf00      	nop
 800345c:	3714      	adds	r7, #20
 800345e:	46bd      	mov	sp, r7
 8003460:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003464:	4770      	bx	lr
 8003466:	bf00      	nop
 8003468:	40012c00 	.word	0x40012c00
 800346c:	40000400 	.word	0x40000400
 8003470:	40000800 	.word	0x40000800
 8003474:	40000c00 	.word	0x40000c00
 8003478:	40013400 	.word	0x40013400
 800347c:	40014000 	.word	0x40014000
 8003480:	40014400 	.word	0x40014400
 8003484:	40014800 	.word	0x40014800

08003488 <HAL_TIMEx_CommutCallback>:
  * @brief  Hall commutation changed callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
 8003488:	b480      	push	{r7}
 800348a:	b083      	sub	sp, #12
 800348c:	af00      	add	r7, sp, #0
 800348e:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_CommutCallback could be implemented in the user file
   */
}
 8003490:	bf00      	nop
 8003492:	370c      	adds	r7, #12
 8003494:	46bd      	mov	sp, r7
 8003496:	f85d 7b04 	ldr.w	r7, [sp], #4
 800349a:	4770      	bx	lr

0800349c <HAL_TIMEx_BreakCallback>:
  * @brief  Hall Break detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 800349c:	b480      	push	{r7}
 800349e:	b083      	sub	sp, #12
 80034a0:	af00      	add	r7, sp, #0
 80034a2:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_BreakCallback could be implemented in the user file
   */
}
 80034a4:	bf00      	nop
 80034a6:	370c      	adds	r7, #12
 80034a8:	46bd      	mov	sp, r7
 80034aa:	f85d 7b04 	ldr.w	r7, [sp], #4
 80034ae:	4770      	bx	lr

080034b0 <HAL_TIMEx_Break2Callback>:
  * @brief  Hall Break2 detection callback in non blocking mode
  * @param  htim: TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
 80034b0:	b480      	push	{r7}
 80034b2:	b083      	sub	sp, #12
 80034b4:	af00      	add	r7, sp, #0
 80034b6:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_TIMEx_Break2Callback could be implemented in the user file
   */
}
 80034b8:	bf00      	nop
 80034ba:	370c      	adds	r7, #12
 80034bc:	46bd      	mov	sp, r7
 80034be:	f85d 7b04 	ldr.w	r7, [sp], #4
 80034c2:	4770      	bx	lr

080034c4 <HAL_UART_Init>:
  *        parameters in the UART_InitTypeDef and initialize the associated handle.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 80034c4:	b580      	push	{r7, lr}
 80034c6:	b082      	sub	sp, #8
 80034c8:	af00      	add	r7, sp, #0
 80034ca:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 80034cc:	687b      	ldr	r3, [r7, #4]
 80034ce:	2b00      	cmp	r3, #0
 80034d0:	d101      	bne.n	80034d6 <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 80034d2:	2301      	movs	r3, #1
 80034d4:	e040      	b.n	8003558 <HAL_UART_Init+0x94>
  {
    /* Check the parameters */
    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
  }

  if (huart->gState == HAL_UART_STATE_RESET)
 80034d6:	687b      	ldr	r3, [r7, #4]
 80034d8:	6f9b      	ldr	r3, [r3, #120]	; 0x78
 80034da:	2b00      	cmp	r3, #0
 80034dc:	d106      	bne.n	80034ec <HAL_UART_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 80034de:	687b      	ldr	r3, [r7, #4]
 80034e0:	2200      	movs	r2, #0
 80034e2:	f883 2074 	strb.w	r2, [r3, #116]	; 0x74

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 80034e6:	6878      	ldr	r0, [r7, #4]
 80034e8:	f7fd faf4 	bl	8000ad4 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 80034ec:	687b      	ldr	r3, [r7, #4]
 80034ee:	2224      	movs	r2, #36	; 0x24
 80034f0:	679a      	str	r2, [r3, #120]	; 0x78

  __HAL_UART_DISABLE(huart);
 80034f2:	687b      	ldr	r3, [r7, #4]
 80034f4:	681b      	ldr	r3, [r3, #0]
 80034f6:	681a      	ldr	r2, [r3, #0]
 80034f8:	687b      	ldr	r3, [r7, #4]
 80034fa:	681b      	ldr	r3, [r3, #0]
 80034fc:	f022 0201 	bic.w	r2, r2, #1
 8003500:	601a      	str	r2, [r3, #0]

  /* Set the UART Communication parameters */
  if (UART_SetConfig(huart) == HAL_ERROR)
 8003502:	6878      	ldr	r0, [r7, #4]
 8003504:	f000 f82c 	bl	8003560 <UART_SetConfig>
 8003508:	4603      	mov	r3, r0
 800350a:	2b01      	cmp	r3, #1
 800350c:	d101      	bne.n	8003512 <HAL_UART_Init+0x4e>
  {
    return HAL_ERROR;
 800350e:	2301      	movs	r3, #1
 8003510:	e022      	b.n	8003558 <HAL_UART_Init+0x94>
  }

  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
 8003512:	687b      	ldr	r3, [r7, #4]
 8003514:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003516:	2b00      	cmp	r3, #0
 8003518:	d002      	beq.n	8003520 <HAL_UART_Init+0x5c>
  {
    UART_AdvFeatureConfig(huart);
 800351a:	6878      	ldr	r0, [r7, #4]
 800351c:	f000 fad8 	bl	8003ad0 <UART_AdvFeatureConfig>
  }

  /* In asynchronous mode, the following bits must be kept cleared:
  - LINEN and CLKEN bits in the USART_CR2 register,
  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8003520:	687b      	ldr	r3, [r7, #4]
 8003522:	681b      	ldr	r3, [r3, #0]
 8003524:	685a      	ldr	r2, [r3, #4]
 8003526:	687b      	ldr	r3, [r7, #4]
 8003528:	681b      	ldr	r3, [r3, #0]
 800352a:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 800352e:	605a      	str	r2, [r3, #4]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8003530:	687b      	ldr	r3, [r7, #4]
 8003532:	681b      	ldr	r3, [r3, #0]
 8003534:	689a      	ldr	r2, [r3, #8]
 8003536:	687b      	ldr	r3, [r7, #4]
 8003538:	681b      	ldr	r3, [r3, #0]
 800353a:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 800353e:	609a      	str	r2, [r3, #8]

  __HAL_UART_ENABLE(huart);
 8003540:	687b      	ldr	r3, [r7, #4]
 8003542:	681b      	ldr	r3, [r3, #0]
 8003544:	681a      	ldr	r2, [r3, #0]
 8003546:	687b      	ldr	r3, [r7, #4]
 8003548:	681b      	ldr	r3, [r3, #0]
 800354a:	f042 0201 	orr.w	r2, r2, #1
 800354e:	601a      	str	r2, [r3, #0]

  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
  return (UART_CheckIdleState(huart));
 8003550:	6878      	ldr	r0, [r7, #4]
 8003552:	f000 fb5f 	bl	8003c14 <UART_CheckIdleState>
 8003556:	4603      	mov	r3, r0
}
 8003558:	4618      	mov	r0, r3
 800355a:	3708      	adds	r7, #8
 800355c:	46bd      	mov	sp, r7
 800355e:	bd80      	pop	{r7, pc}

08003560 <UART_SetConfig>:
  * @brief Configure the UART peripheral.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
 8003560:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 8003564:	b08a      	sub	sp, #40	; 0x28
 8003566:	af00      	add	r7, sp, #0
 8003568:	60f8      	str	r0, [r7, #12]
  uint32_t tmpreg;
  uint16_t brrtemp;
  UART_ClockSourceTypeDef clocksource;
  uint32_t usartdiv;
  HAL_StatusTypeDef ret               = HAL_OK;
 800356a:	2300      	movs	r3, #0
 800356c:	f887 3022 	strb.w	r3, [r7, #34]	; 0x22
  *  the UART Word Length, Parity, Mode and oversampling:
  *  set the M bits according to huart->Init.WordLength value
  *  set PCE and PS bits according to huart->Init.Parity value
  *  set TE and RE bits according to huart->Init.Mode value
  *  set OVER8 bit according to huart->Init.OverSampling value */
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
 8003570:	68fb      	ldr	r3, [r7, #12]
 8003572:	689a      	ldr	r2, [r3, #8]
 8003574:	68fb      	ldr	r3, [r7, #12]
 8003576:	691b      	ldr	r3, [r3, #16]
 8003578:	431a      	orrs	r2, r3
 800357a:	68fb      	ldr	r3, [r7, #12]
 800357c:	695b      	ldr	r3, [r3, #20]
 800357e:	431a      	orrs	r2, r3
 8003580:	68fb      	ldr	r3, [r7, #12]
 8003582:	69db      	ldr	r3, [r3, #28]
 8003584:	4313      	orrs	r3, r2
 8003586:	627b      	str	r3, [r7, #36]	; 0x24
  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
 8003588:	68fb      	ldr	r3, [r7, #12]
 800358a:	681b      	ldr	r3, [r3, #0]
 800358c:	681a      	ldr	r2, [r3, #0]
 800358e:	4ba4      	ldr	r3, [pc, #656]	; (8003820 <UART_SetConfig+0x2c0>)
 8003590:	4013      	ands	r3, r2
 8003592:	68fa      	ldr	r2, [r7, #12]
 8003594:	6812      	ldr	r2, [r2, #0]
 8003596:	6a79      	ldr	r1, [r7, #36]	; 0x24
 8003598:	430b      	orrs	r3, r1
 800359a:	6013      	str	r3, [r2, #0]

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
  * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 800359c:	68fb      	ldr	r3, [r7, #12]
 800359e:	681b      	ldr	r3, [r3, #0]
 80035a0:	685b      	ldr	r3, [r3, #4]
 80035a2:	f423 5140 	bic.w	r1, r3, #12288	; 0x3000
 80035a6:	68fb      	ldr	r3, [r7, #12]
 80035a8:	68da      	ldr	r2, [r3, #12]
 80035aa:	68fb      	ldr	r3, [r7, #12]
 80035ac:	681b      	ldr	r3, [r3, #0]
 80035ae:	430a      	orrs	r2, r1
 80035b0:	605a      	str	r2, [r3, #4]
  /* Configure
  * - UART HardWare Flow Control: set CTSE and RTSE bits according
  *   to huart->Init.HwFlowCtl value
  * - one-bit sampling method versus three samples' majority rule according
  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
 80035b2:	68fb      	ldr	r3, [r7, #12]
 80035b4:	699b      	ldr	r3, [r3, #24]
 80035b6:	627b      	str	r3, [r7, #36]	; 0x24

  if (!(UART_INSTANCE_LOWPOWER(huart)))
 80035b8:	68fb      	ldr	r3, [r7, #12]
 80035ba:	681b      	ldr	r3, [r3, #0]
 80035bc:	4a99      	ldr	r2, [pc, #612]	; (8003824 <UART_SetConfig+0x2c4>)
 80035be:	4293      	cmp	r3, r2
 80035c0:	d004      	beq.n	80035cc <UART_SetConfig+0x6c>
  {
    tmpreg |= huart->Init.OneBitSampling;
 80035c2:	68fb      	ldr	r3, [r7, #12]
 80035c4:	6a1b      	ldr	r3, [r3, #32]
 80035c6:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 80035c8:	4313      	orrs	r3, r2
 80035ca:	627b      	str	r3, [r7, #36]	; 0x24
  }
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 80035cc:	68fb      	ldr	r3, [r7, #12]
 80035ce:	681b      	ldr	r3, [r3, #0]
 80035d0:	689b      	ldr	r3, [r3, #8]
 80035d2:	f423 6130 	bic.w	r1, r3, #2816	; 0xb00
 80035d6:	68fb      	ldr	r3, [r7, #12]
 80035d8:	681b      	ldr	r3, [r3, #0]
 80035da:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 80035dc:	430a      	orrs	r2, r1
 80035de:	609a      	str	r2, [r3, #8]
  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
#endif /* USART_PRESC_PRESCALER */

  /*-------------------------- USART BRR Configuration -----------------------*/
  UART_GETCLOCKSOURCE(huart, clocksource);
 80035e0:	68fb      	ldr	r3, [r7, #12]
 80035e2:	681b      	ldr	r3, [r3, #0]
 80035e4:	4a90      	ldr	r2, [pc, #576]	; (8003828 <UART_SetConfig+0x2c8>)
 80035e6:	4293      	cmp	r3, r2
 80035e8:	d126      	bne.n	8003638 <UART_SetConfig+0xd8>
 80035ea:	4b90      	ldr	r3, [pc, #576]	; (800382c <UART_SetConfig+0x2cc>)
 80035ec:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 80035f0:	f003 0303 	and.w	r3, r3, #3
 80035f4:	2b03      	cmp	r3, #3
 80035f6:	d81b      	bhi.n	8003630 <UART_SetConfig+0xd0>
 80035f8:	a201      	add	r2, pc, #4	; (adr r2, 8003600 <UART_SetConfig+0xa0>)
 80035fa:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80035fe:	bf00      	nop
 8003600:	08003611 	.word	0x08003611
 8003604:	08003621 	.word	0x08003621
 8003608:	08003619 	.word	0x08003619
 800360c:	08003629 	.word	0x08003629
 8003610:	2301      	movs	r3, #1
 8003612:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 8003616:	e116      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003618:	2302      	movs	r3, #2
 800361a:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 800361e:	e112      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003620:	2304      	movs	r3, #4
 8003622:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 8003626:	e10e      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003628:	2308      	movs	r3, #8
 800362a:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 800362e:	e10a      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003630:	2310      	movs	r3, #16
 8003632:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 8003636:	e106      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003638:	68fb      	ldr	r3, [r7, #12]
 800363a:	681b      	ldr	r3, [r3, #0]
 800363c:	4a7c      	ldr	r2, [pc, #496]	; (8003830 <UART_SetConfig+0x2d0>)
 800363e:	4293      	cmp	r3, r2
 8003640:	d138      	bne.n	80036b4 <UART_SetConfig+0x154>
 8003642:	4b7a      	ldr	r3, [pc, #488]	; (800382c <UART_SetConfig+0x2cc>)
 8003644:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8003648:	f003 030c 	and.w	r3, r3, #12
 800364c:	2b0c      	cmp	r3, #12
 800364e:	d82d      	bhi.n	80036ac <UART_SetConfig+0x14c>
 8003650:	a201      	add	r2, pc, #4	; (adr r2, 8003658 <UART_SetConfig+0xf8>)
 8003652:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8003656:	bf00      	nop
 8003658:	0800368d 	.word	0x0800368d
 800365c:	080036ad 	.word	0x080036ad
 8003660:	080036ad 	.word	0x080036ad
 8003664:	080036ad 	.word	0x080036ad
 8003668:	0800369d 	.word	0x0800369d
 800366c:	080036ad 	.word	0x080036ad
 8003670:	080036ad 	.word	0x080036ad
 8003674:	080036ad 	.word	0x080036ad
 8003678:	08003695 	.word	0x08003695
 800367c:	080036ad 	.word	0x080036ad
 8003680:	080036ad 	.word	0x080036ad
 8003684:	080036ad 	.word	0x080036ad
 8003688:	080036a5 	.word	0x080036a5
 800368c:	2300      	movs	r3, #0
 800368e:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 8003692:	e0d8      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003694:	2302      	movs	r3, #2
 8003696:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 800369a:	e0d4      	b.n	8003846 <UART_SetConfig+0x2e6>
 800369c:	2304      	movs	r3, #4
 800369e:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80036a2:	e0d0      	b.n	8003846 <UART_SetConfig+0x2e6>
 80036a4:	2308      	movs	r3, #8
 80036a6:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80036aa:	e0cc      	b.n	8003846 <UART_SetConfig+0x2e6>
 80036ac:	2310      	movs	r3, #16
 80036ae:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80036b2:	e0c8      	b.n	8003846 <UART_SetConfig+0x2e6>
 80036b4:	68fb      	ldr	r3, [r7, #12]
 80036b6:	681b      	ldr	r3, [r3, #0]
 80036b8:	4a5e      	ldr	r2, [pc, #376]	; (8003834 <UART_SetConfig+0x2d4>)
 80036ba:	4293      	cmp	r3, r2
 80036bc:	d125      	bne.n	800370a <UART_SetConfig+0x1aa>
 80036be:	4b5b      	ldr	r3, [pc, #364]	; (800382c <UART_SetConfig+0x2cc>)
 80036c0:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 80036c4:	f003 0330 	and.w	r3, r3, #48	; 0x30
 80036c8:	2b30      	cmp	r3, #48	; 0x30
 80036ca:	d016      	beq.n	80036fa <UART_SetConfig+0x19a>
 80036cc:	2b30      	cmp	r3, #48	; 0x30
 80036ce:	d818      	bhi.n	8003702 <UART_SetConfig+0x1a2>
 80036d0:	2b20      	cmp	r3, #32
 80036d2:	d00a      	beq.n	80036ea <UART_SetConfig+0x18a>
 80036d4:	2b20      	cmp	r3, #32
 80036d6:	d814      	bhi.n	8003702 <UART_SetConfig+0x1a2>
 80036d8:	2b00      	cmp	r3, #0
 80036da:	d002      	beq.n	80036e2 <UART_SetConfig+0x182>
 80036dc:	2b10      	cmp	r3, #16
 80036de:	d008      	beq.n	80036f2 <UART_SetConfig+0x192>
 80036e0:	e00f      	b.n	8003702 <UART_SetConfig+0x1a2>
 80036e2:	2300      	movs	r3, #0
 80036e4:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80036e8:	e0ad      	b.n	8003846 <UART_SetConfig+0x2e6>
 80036ea:	2302      	movs	r3, #2
 80036ec:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80036f0:	e0a9      	b.n	8003846 <UART_SetConfig+0x2e6>
 80036f2:	2304      	movs	r3, #4
 80036f4:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80036f8:	e0a5      	b.n	8003846 <UART_SetConfig+0x2e6>
 80036fa:	2308      	movs	r3, #8
 80036fc:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 8003700:	e0a1      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003702:	2310      	movs	r3, #16
 8003704:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 8003708:	e09d      	b.n	8003846 <UART_SetConfig+0x2e6>
 800370a:	68fb      	ldr	r3, [r7, #12]
 800370c:	681b      	ldr	r3, [r3, #0]
 800370e:	4a4a      	ldr	r2, [pc, #296]	; (8003838 <UART_SetConfig+0x2d8>)
 8003710:	4293      	cmp	r3, r2
 8003712:	d125      	bne.n	8003760 <UART_SetConfig+0x200>
 8003714:	4b45      	ldr	r3, [pc, #276]	; (800382c <UART_SetConfig+0x2cc>)
 8003716:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 800371a:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
 800371e:	2bc0      	cmp	r3, #192	; 0xc0
 8003720:	d016      	beq.n	8003750 <UART_SetConfig+0x1f0>
 8003722:	2bc0      	cmp	r3, #192	; 0xc0
 8003724:	d818      	bhi.n	8003758 <UART_SetConfig+0x1f8>
 8003726:	2b80      	cmp	r3, #128	; 0x80
 8003728:	d00a      	beq.n	8003740 <UART_SetConfig+0x1e0>
 800372a:	2b80      	cmp	r3, #128	; 0x80
 800372c:	d814      	bhi.n	8003758 <UART_SetConfig+0x1f8>
 800372e:	2b00      	cmp	r3, #0
 8003730:	d002      	beq.n	8003738 <UART_SetConfig+0x1d8>
 8003732:	2b40      	cmp	r3, #64	; 0x40
 8003734:	d008      	beq.n	8003748 <UART_SetConfig+0x1e8>
 8003736:	e00f      	b.n	8003758 <UART_SetConfig+0x1f8>
 8003738:	2300      	movs	r3, #0
 800373a:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 800373e:	e082      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003740:	2302      	movs	r3, #2
 8003742:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 8003746:	e07e      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003748:	2304      	movs	r3, #4
 800374a:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 800374e:	e07a      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003750:	2308      	movs	r3, #8
 8003752:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 8003756:	e076      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003758:	2310      	movs	r3, #16
 800375a:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 800375e:	e072      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003760:	68fb      	ldr	r3, [r7, #12]
 8003762:	681b      	ldr	r3, [r3, #0]
 8003764:	4a35      	ldr	r2, [pc, #212]	; (800383c <UART_SetConfig+0x2dc>)
 8003766:	4293      	cmp	r3, r2
 8003768:	d12a      	bne.n	80037c0 <UART_SetConfig+0x260>
 800376a:	4b30      	ldr	r3, [pc, #192]	; (800382c <UART_SetConfig+0x2cc>)
 800376c:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8003770:	f403 7340 	and.w	r3, r3, #768	; 0x300
 8003774:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
 8003778:	d01a      	beq.n	80037b0 <UART_SetConfig+0x250>
 800377a:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
 800377e:	d81b      	bhi.n	80037b8 <UART_SetConfig+0x258>
 8003780:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 8003784:	d00c      	beq.n	80037a0 <UART_SetConfig+0x240>
 8003786:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 800378a:	d815      	bhi.n	80037b8 <UART_SetConfig+0x258>
 800378c:	2b00      	cmp	r3, #0
 800378e:	d003      	beq.n	8003798 <UART_SetConfig+0x238>
 8003790:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
 8003794:	d008      	beq.n	80037a8 <UART_SetConfig+0x248>
 8003796:	e00f      	b.n	80037b8 <UART_SetConfig+0x258>
 8003798:	2300      	movs	r3, #0
 800379a:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 800379e:	e052      	b.n	8003846 <UART_SetConfig+0x2e6>
 80037a0:	2302      	movs	r3, #2
 80037a2:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80037a6:	e04e      	b.n	8003846 <UART_SetConfig+0x2e6>
 80037a8:	2304      	movs	r3, #4
 80037aa:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80037ae:	e04a      	b.n	8003846 <UART_SetConfig+0x2e6>
 80037b0:	2308      	movs	r3, #8
 80037b2:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80037b6:	e046      	b.n	8003846 <UART_SetConfig+0x2e6>
 80037b8:	2310      	movs	r3, #16
 80037ba:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80037be:	e042      	b.n	8003846 <UART_SetConfig+0x2e6>
 80037c0:	68fb      	ldr	r3, [r7, #12]
 80037c2:	681b      	ldr	r3, [r3, #0]
 80037c4:	4a17      	ldr	r2, [pc, #92]	; (8003824 <UART_SetConfig+0x2c4>)
 80037c6:	4293      	cmp	r3, r2
 80037c8:	d13a      	bne.n	8003840 <UART_SetConfig+0x2e0>
 80037ca:	4b18      	ldr	r3, [pc, #96]	; (800382c <UART_SetConfig+0x2cc>)
 80037cc:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 80037d0:	f403 6340 	and.w	r3, r3, #3072	; 0xc00
 80037d4:	f5b3 6f40 	cmp.w	r3, #3072	; 0xc00
 80037d8:	d01a      	beq.n	8003810 <UART_SetConfig+0x2b0>
 80037da:	f5b3 6f40 	cmp.w	r3, #3072	; 0xc00
 80037de:	d81b      	bhi.n	8003818 <UART_SetConfig+0x2b8>
 80037e0:	f5b3 6f00 	cmp.w	r3, #2048	; 0x800
 80037e4:	d00c      	beq.n	8003800 <UART_SetConfig+0x2a0>
 80037e6:	f5b3 6f00 	cmp.w	r3, #2048	; 0x800
 80037ea:	d815      	bhi.n	8003818 <UART_SetConfig+0x2b8>
 80037ec:	2b00      	cmp	r3, #0
 80037ee:	d003      	beq.n	80037f8 <UART_SetConfig+0x298>
 80037f0:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 80037f4:	d008      	beq.n	8003808 <UART_SetConfig+0x2a8>
 80037f6:	e00f      	b.n	8003818 <UART_SetConfig+0x2b8>
 80037f8:	2300      	movs	r3, #0
 80037fa:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 80037fe:	e022      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003800:	2302      	movs	r3, #2
 8003802:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 8003806:	e01e      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003808:	2304      	movs	r3, #4
 800380a:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 800380e:	e01a      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003810:	2308      	movs	r3, #8
 8003812:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 8003816:	e016      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003818:	2310      	movs	r3, #16
 800381a:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23
 800381e:	e012      	b.n	8003846 <UART_SetConfig+0x2e6>
 8003820:	efff69f3 	.word	0xefff69f3
 8003824:	40008000 	.word	0x40008000
 8003828:	40013800 	.word	0x40013800
 800382c:	40021000 	.word	0x40021000
 8003830:	40004400 	.word	0x40004400
 8003834:	40004800 	.word	0x40004800
 8003838:	40004c00 	.word	0x40004c00
 800383c:	40005000 	.word	0x40005000
 8003840:	2310      	movs	r3, #16
 8003842:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23

  /* Check LPUART instance */
  if (UART_INSTANCE_LOWPOWER(huart))
 8003846:	68fb      	ldr	r3, [r7, #12]
 8003848:	681b      	ldr	r3, [r3, #0]
 800384a:	4a9f      	ldr	r2, [pc, #636]	; (8003ac8 <UART_SetConfig+0x568>)
 800384c:	4293      	cmp	r3, r2
 800384e:	d17a      	bne.n	8003946 <UART_SetConfig+0x3e6>
  {
    /* Retrieve frequency clock */
    switch (clocksource)
 8003850:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
 8003854:	2b08      	cmp	r3, #8
 8003856:	d824      	bhi.n	80038a2 <UART_SetConfig+0x342>
 8003858:	a201      	add	r2, pc, #4	; (adr r2, 8003860 <UART_SetConfig+0x300>)
 800385a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800385e:	bf00      	nop
 8003860:	08003885 	.word	0x08003885
 8003864:	080038a3 	.word	0x080038a3
 8003868:	0800388d 	.word	0x0800388d
 800386c:	080038a3 	.word	0x080038a3
 8003870:	08003893 	.word	0x08003893
 8003874:	080038a3 	.word	0x080038a3
 8003878:	080038a3 	.word	0x080038a3
 800387c:	080038a3 	.word	0x080038a3
 8003880:	0800389b 	.word	0x0800389b
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8003884:	f7fe fc58 	bl	8002138 <HAL_RCC_GetPCLK1Freq>
 8003888:	61f8      	str	r0, [r7, #28]
        break;
 800388a:	e010      	b.n	80038ae <UART_SetConfig+0x34e>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 800388c:	4b8f      	ldr	r3, [pc, #572]	; (8003acc <UART_SetConfig+0x56c>)
 800388e:	61fb      	str	r3, [r7, #28]
        break;
 8003890:	e00d      	b.n	80038ae <UART_SetConfig+0x34e>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 8003892:	f7fe fbb9 	bl	8002008 <HAL_RCC_GetSysClockFreq>
 8003896:	61f8      	str	r0, [r7, #28]
        break;
 8003898:	e009      	b.n	80038ae <UART_SetConfig+0x34e>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 800389a:	f44f 4300 	mov.w	r3, #32768	; 0x8000
 800389e:	61fb      	str	r3, [r7, #28]
        break;
 80038a0:	e005      	b.n	80038ae <UART_SetConfig+0x34e>
      default:
        pclk = 0U;
 80038a2:	2300      	movs	r3, #0
 80038a4:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 80038a6:	2301      	movs	r3, #1
 80038a8:	f887 3022 	strb.w	r3, [r7, #34]	; 0x22
        break;
 80038ac:	bf00      	nop
    }

    /* If proper clock source reported */
    if (pclk != 0U)
 80038ae:	69fb      	ldr	r3, [r7, #28]
 80038b0:	2b00      	cmp	r3, #0
 80038b2:	f000 80fb 	beq.w	8003aac <UART_SetConfig+0x54c>
      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
#else
      /* No Prescaler applicable */
      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
      if ((pclk < (3U * huart->Init.BaudRate)) ||
 80038b6:	68fb      	ldr	r3, [r7, #12]
 80038b8:	685a      	ldr	r2, [r3, #4]
 80038ba:	4613      	mov	r3, r2
 80038bc:	005b      	lsls	r3, r3, #1
 80038be:	4413      	add	r3, r2
 80038c0:	69fa      	ldr	r2, [r7, #28]
 80038c2:	429a      	cmp	r2, r3
 80038c4:	d305      	bcc.n	80038d2 <UART_SetConfig+0x372>
          (pclk > (4096U * huart->Init.BaudRate)))
 80038c6:	68fb      	ldr	r3, [r7, #12]
 80038c8:	685b      	ldr	r3, [r3, #4]
 80038ca:	031b      	lsls	r3, r3, #12
      if ((pclk < (3U * huart->Init.BaudRate)) ||
 80038cc:	69fa      	ldr	r2, [r7, #28]
 80038ce:	429a      	cmp	r2, r3
 80038d0:	d903      	bls.n	80038da <UART_SetConfig+0x37a>
      {
        ret = HAL_ERROR;
 80038d2:	2301      	movs	r3, #1
 80038d4:	f887 3022 	strb.w	r3, [r7, #34]	; 0x22
 80038d8:	e0e8      	b.n	8003aac <UART_SetConfig+0x54c>
      }
      else
      {
        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
 80038da:	69fb      	ldr	r3, [r7, #28]
 80038dc:	2200      	movs	r2, #0
 80038de:	461c      	mov	r4, r3
 80038e0:	4615      	mov	r5, r2
 80038e2:	f04f 0200 	mov.w	r2, #0
 80038e6:	f04f 0300 	mov.w	r3, #0
 80038ea:	022b      	lsls	r3, r5, #8
 80038ec:	ea43 6314 	orr.w	r3, r3, r4, lsr #24
 80038f0:	0222      	lsls	r2, r4, #8
 80038f2:	68f9      	ldr	r1, [r7, #12]
 80038f4:	6849      	ldr	r1, [r1, #4]
 80038f6:	0849      	lsrs	r1, r1, #1
 80038f8:	2000      	movs	r0, #0
 80038fa:	4688      	mov	r8, r1
 80038fc:	4681      	mov	r9, r0
 80038fe:	eb12 0a08 	adds.w	sl, r2, r8
 8003902:	eb43 0b09 	adc.w	fp, r3, r9
 8003906:	68fb      	ldr	r3, [r7, #12]
 8003908:	685b      	ldr	r3, [r3, #4]
 800390a:	2200      	movs	r2, #0
 800390c:	603b      	str	r3, [r7, #0]
 800390e:	607a      	str	r2, [r7, #4]
 8003910:	e9d7 2300 	ldrd	r2, r3, [r7]
 8003914:	4650      	mov	r0, sl
 8003916:	4659      	mov	r1, fp
 8003918:	f7fc fc5a 	bl	80001d0 <__aeabi_uldivmod>
 800391c:	4602      	mov	r2, r0
 800391e:	460b      	mov	r3, r1
 8003920:	4613      	mov	r3, r2
 8003922:	61bb      	str	r3, [r7, #24]
        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
 8003924:	69bb      	ldr	r3, [r7, #24]
 8003926:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
 800392a:	d308      	bcc.n	800393e <UART_SetConfig+0x3de>
 800392c:	69bb      	ldr	r3, [r7, #24]
 800392e:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
 8003932:	d204      	bcs.n	800393e <UART_SetConfig+0x3de>
        {
          huart->Instance->BRR = usartdiv;
 8003934:	68fb      	ldr	r3, [r7, #12]
 8003936:	681b      	ldr	r3, [r3, #0]
 8003938:	69ba      	ldr	r2, [r7, #24]
 800393a:	60da      	str	r2, [r3, #12]
 800393c:	e0b6      	b.n	8003aac <UART_SetConfig+0x54c>
        }
        else
        {
          ret = HAL_ERROR;
 800393e:	2301      	movs	r3, #1
 8003940:	f887 3022 	strb.w	r3, [r7, #34]	; 0x22
 8003944:	e0b2      	b.n	8003aac <UART_SetConfig+0x54c>
      } /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
#endif /* USART_PRESC_PRESCALER */
    } /* if (pclk != 0) */
  }
  /* Check UART Over Sampling to set Baud Rate Register */
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8003946:	68fb      	ldr	r3, [r7, #12]
 8003948:	69db      	ldr	r3, [r3, #28]
 800394a:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
 800394e:	d15e      	bne.n	8003a0e <UART_SetConfig+0x4ae>
  {
    switch (clocksource)
 8003950:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
 8003954:	2b08      	cmp	r3, #8
 8003956:	d828      	bhi.n	80039aa <UART_SetConfig+0x44a>
 8003958:	a201      	add	r2, pc, #4	; (adr r2, 8003960 <UART_SetConfig+0x400>)
 800395a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800395e:	bf00      	nop
 8003960:	08003985 	.word	0x08003985
 8003964:	0800398d 	.word	0x0800398d
 8003968:	08003995 	.word	0x08003995
 800396c:	080039ab 	.word	0x080039ab
 8003970:	0800399b 	.word	0x0800399b
 8003974:	080039ab 	.word	0x080039ab
 8003978:	080039ab 	.word	0x080039ab
 800397c:	080039ab 	.word	0x080039ab
 8003980:	080039a3 	.word	0x080039a3
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8003984:	f7fe fbd8 	bl	8002138 <HAL_RCC_GetPCLK1Freq>
 8003988:	61f8      	str	r0, [r7, #28]
        break;
 800398a:	e014      	b.n	80039b6 <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 800398c:	f7fe fbea 	bl	8002164 <HAL_RCC_GetPCLK2Freq>
 8003990:	61f8      	str	r0, [r7, #28]
        break;
 8003992:	e010      	b.n	80039b6 <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 8003994:	4b4d      	ldr	r3, [pc, #308]	; (8003acc <UART_SetConfig+0x56c>)
 8003996:	61fb      	str	r3, [r7, #28]
        break;
 8003998:	e00d      	b.n	80039b6 <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 800399a:	f7fe fb35 	bl	8002008 <HAL_RCC_GetSysClockFreq>
 800399e:	61f8      	str	r0, [r7, #28]
        break;
 80039a0:	e009      	b.n	80039b6 <UART_SetConfig+0x456>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 80039a2:	f44f 4300 	mov.w	r3, #32768	; 0x8000
 80039a6:	61fb      	str	r3, [r7, #28]
        break;
 80039a8:	e005      	b.n	80039b6 <UART_SetConfig+0x456>
      default:
        pclk = 0U;
 80039aa:	2300      	movs	r3, #0
 80039ac:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 80039ae:	2301      	movs	r3, #1
 80039b0:	f887 3022 	strb.w	r3, [r7, #34]	; 0x22
        break;
 80039b4:	bf00      	nop
    }

    /* USARTDIV must be greater than or equal to 0d16 */
    if (pclk != 0U)
 80039b6:	69fb      	ldr	r3, [r7, #28]
 80039b8:	2b00      	cmp	r3, #0
 80039ba:	d077      	beq.n	8003aac <UART_SetConfig+0x54c>
    {
#if defined(USART_PRESC_PRESCALER)
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
 80039bc:	69fb      	ldr	r3, [r7, #28]
 80039be:	005a      	lsls	r2, r3, #1
 80039c0:	68fb      	ldr	r3, [r7, #12]
 80039c2:	685b      	ldr	r3, [r3, #4]
 80039c4:	085b      	lsrs	r3, r3, #1
 80039c6:	441a      	add	r2, r3
 80039c8:	68fb      	ldr	r3, [r7, #12]
 80039ca:	685b      	ldr	r3, [r3, #4]
 80039cc:	fbb2 f3f3 	udiv	r3, r2, r3
 80039d0:	61bb      	str	r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 80039d2:	69bb      	ldr	r3, [r7, #24]
 80039d4:	2b0f      	cmp	r3, #15
 80039d6:	d916      	bls.n	8003a06 <UART_SetConfig+0x4a6>
 80039d8:	69bb      	ldr	r3, [r7, #24]
 80039da:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 80039de:	d212      	bcs.n	8003a06 <UART_SetConfig+0x4a6>
      {
        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
 80039e0:	69bb      	ldr	r3, [r7, #24]
 80039e2:	b29b      	uxth	r3, r3
 80039e4:	f023 030f 	bic.w	r3, r3, #15
 80039e8:	82fb      	strh	r3, [r7, #22]
        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
 80039ea:	69bb      	ldr	r3, [r7, #24]
 80039ec:	085b      	lsrs	r3, r3, #1
 80039ee:	b29b      	uxth	r3, r3
 80039f0:	f003 0307 	and.w	r3, r3, #7
 80039f4:	b29a      	uxth	r2, r3
 80039f6:	8afb      	ldrh	r3, [r7, #22]
 80039f8:	4313      	orrs	r3, r2
 80039fa:	82fb      	strh	r3, [r7, #22]
        huart->Instance->BRR = brrtemp;
 80039fc:	68fb      	ldr	r3, [r7, #12]
 80039fe:	681b      	ldr	r3, [r3, #0]
 8003a00:	8afa      	ldrh	r2, [r7, #22]
 8003a02:	60da      	str	r2, [r3, #12]
 8003a04:	e052      	b.n	8003aac <UART_SetConfig+0x54c>
      }
      else
      {
        ret = HAL_ERROR;
 8003a06:	2301      	movs	r3, #1
 8003a08:	f887 3022 	strb.w	r3, [r7, #34]	; 0x22
 8003a0c:	e04e      	b.n	8003aac <UART_SetConfig+0x54c>
      }
    }
  }
  else
  {
    switch (clocksource)
 8003a0e:	f897 3023 	ldrb.w	r3, [r7, #35]	; 0x23
 8003a12:	2b08      	cmp	r3, #8
 8003a14:	d827      	bhi.n	8003a66 <UART_SetConfig+0x506>
 8003a16:	a201      	add	r2, pc, #4	; (adr r2, 8003a1c <UART_SetConfig+0x4bc>)
 8003a18:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8003a1c:	08003a41 	.word	0x08003a41
 8003a20:	08003a49 	.word	0x08003a49
 8003a24:	08003a51 	.word	0x08003a51
 8003a28:	08003a67 	.word	0x08003a67
 8003a2c:	08003a57 	.word	0x08003a57
 8003a30:	08003a67 	.word	0x08003a67
 8003a34:	08003a67 	.word	0x08003a67
 8003a38:	08003a67 	.word	0x08003a67
 8003a3c:	08003a5f 	.word	0x08003a5f
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8003a40:	f7fe fb7a 	bl	8002138 <HAL_RCC_GetPCLK1Freq>
 8003a44:	61f8      	str	r0, [r7, #28]
        break;
 8003a46:	e014      	b.n	8003a72 <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 8003a48:	f7fe fb8c 	bl	8002164 <HAL_RCC_GetPCLK2Freq>
 8003a4c:	61f8      	str	r0, [r7, #28]
        break;
 8003a4e:	e010      	b.n	8003a72 <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 8003a50:	4b1e      	ldr	r3, [pc, #120]	; (8003acc <UART_SetConfig+0x56c>)
 8003a52:	61fb      	str	r3, [r7, #28]
        break;
 8003a54:	e00d      	b.n	8003a72 <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 8003a56:	f7fe fad7 	bl	8002008 <HAL_RCC_GetSysClockFreq>
 8003a5a:	61f8      	str	r0, [r7, #28]
        break;
 8003a5c:	e009      	b.n	8003a72 <UART_SetConfig+0x512>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8003a5e:	f44f 4300 	mov.w	r3, #32768	; 0x8000
 8003a62:	61fb      	str	r3, [r7, #28]
        break;
 8003a64:	e005      	b.n	8003a72 <UART_SetConfig+0x512>
      default:
        pclk = 0U;
 8003a66:	2300      	movs	r3, #0
 8003a68:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 8003a6a:	2301      	movs	r3, #1
 8003a6c:	f887 3022 	strb.w	r3, [r7, #34]	; 0x22
        break;
 8003a70:	bf00      	nop
    }

    if (pclk != 0U)
 8003a72:	69fb      	ldr	r3, [r7, #28]
 8003a74:	2b00      	cmp	r3, #0
 8003a76:	d019      	beq.n	8003aac <UART_SetConfig+0x54c>
    {
      /* USARTDIV must be greater than or equal to 0d16 */
#if defined(USART_PRESC_PRESCALER)
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
 8003a78:	68fb      	ldr	r3, [r7, #12]
 8003a7a:	685b      	ldr	r3, [r3, #4]
 8003a7c:	085a      	lsrs	r2, r3, #1
 8003a7e:	69fb      	ldr	r3, [r7, #28]
 8003a80:	441a      	add	r2, r3
 8003a82:	68fb      	ldr	r3, [r7, #12]
 8003a84:	685b      	ldr	r3, [r3, #4]
 8003a86:	fbb2 f3f3 	udiv	r3, r2, r3
 8003a8a:	61bb      	str	r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 8003a8c:	69bb      	ldr	r3, [r7, #24]
 8003a8e:	2b0f      	cmp	r3, #15
 8003a90:	d909      	bls.n	8003aa6 <UART_SetConfig+0x546>
 8003a92:	69bb      	ldr	r3, [r7, #24]
 8003a94:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8003a98:	d205      	bcs.n	8003aa6 <UART_SetConfig+0x546>
      {
        huart->Instance->BRR = (uint16_t)usartdiv;
 8003a9a:	69bb      	ldr	r3, [r7, #24]
 8003a9c:	b29a      	uxth	r2, r3
 8003a9e:	68fb      	ldr	r3, [r7, #12]
 8003aa0:	681b      	ldr	r3, [r3, #0]
 8003aa2:	60da      	str	r2, [r3, #12]
 8003aa4:	e002      	b.n	8003aac <UART_SetConfig+0x54c>
      }
      else
      {
        ret = HAL_ERROR;
 8003aa6:	2301      	movs	r3, #1
 8003aa8:	f887 3022 	strb.w	r3, [r7, #34]	; 0x22
  huart->NbTxDataToProcess = 1;
  huart->NbRxDataToProcess = 1;
#endif /* USART_CR1_FIFOEN */

  /* Clear ISR function pointers */
  huart->RxISR = NULL;
 8003aac:	68fb      	ldr	r3, [r7, #12]
 8003aae:	2200      	movs	r2, #0
 8003ab0:	665a      	str	r2, [r3, #100]	; 0x64
  huart->TxISR = NULL;
 8003ab2:	68fb      	ldr	r3, [r7, #12]
 8003ab4:	2200      	movs	r2, #0
 8003ab6:	669a      	str	r2, [r3, #104]	; 0x68

  return ret;
 8003ab8:	f897 3022 	ldrb.w	r3, [r7, #34]	; 0x22
}
 8003abc:	4618      	mov	r0, r3
 8003abe:	3728      	adds	r7, #40	; 0x28
 8003ac0:	46bd      	mov	sp, r7
 8003ac2:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 8003ac6:	bf00      	nop
 8003ac8:	40008000 	.word	0x40008000
 8003acc:	00f42400 	.word	0x00f42400

08003ad0 <UART_AdvFeatureConfig>:
  * @brief Configure the UART peripheral advanced features.
  * @param huart UART handle.
  * @retval None
  */
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
 8003ad0:	b480      	push	{r7}
 8003ad2:	b083      	sub	sp, #12
 8003ad4:	af00      	add	r7, sp, #0
 8003ad6:	6078      	str	r0, [r7, #4]
  /* Check whether the set of advanced features to configure is properly set */
  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));

  /* if required, configure TX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
 8003ad8:	687b      	ldr	r3, [r7, #4]
 8003ada:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003adc:	f003 0301 	and.w	r3, r3, #1
 8003ae0:	2b00      	cmp	r3, #0
 8003ae2:	d00a      	beq.n	8003afa <UART_AdvFeatureConfig+0x2a>
  {
    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
 8003ae4:	687b      	ldr	r3, [r7, #4]
 8003ae6:	681b      	ldr	r3, [r3, #0]
 8003ae8:	685b      	ldr	r3, [r3, #4]
 8003aea:	f423 3100 	bic.w	r1, r3, #131072	; 0x20000
 8003aee:	687b      	ldr	r3, [r7, #4]
 8003af0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 8003af2:	687b      	ldr	r3, [r7, #4]
 8003af4:	681b      	ldr	r3, [r3, #0]
 8003af6:	430a      	orrs	r2, r1
 8003af8:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
 8003afa:	687b      	ldr	r3, [r7, #4]
 8003afc:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003afe:	f003 0302 	and.w	r3, r3, #2
 8003b02:	2b00      	cmp	r3, #0
 8003b04:	d00a      	beq.n	8003b1c <UART_AdvFeatureConfig+0x4c>
  {
    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
 8003b06:	687b      	ldr	r3, [r7, #4]
 8003b08:	681b      	ldr	r3, [r3, #0]
 8003b0a:	685b      	ldr	r3, [r3, #4]
 8003b0c:	f423 3180 	bic.w	r1, r3, #65536	; 0x10000
 8003b10:	687b      	ldr	r3, [r7, #4]
 8003b12:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8003b14:	687b      	ldr	r3, [r7, #4]
 8003b16:	681b      	ldr	r3, [r3, #0]
 8003b18:	430a      	orrs	r2, r1
 8003b1a:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure data inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
 8003b1c:	687b      	ldr	r3, [r7, #4]
 8003b1e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003b20:	f003 0304 	and.w	r3, r3, #4
 8003b24:	2b00      	cmp	r3, #0
 8003b26:	d00a      	beq.n	8003b3e <UART_AdvFeatureConfig+0x6e>
  {
    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
 8003b28:	687b      	ldr	r3, [r7, #4]
 8003b2a:	681b      	ldr	r3, [r3, #0]
 8003b2c:	685b      	ldr	r3, [r3, #4]
 8003b2e:	f423 2180 	bic.w	r1, r3, #262144	; 0x40000
 8003b32:	687b      	ldr	r3, [r7, #4]
 8003b34:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8003b36:	687b      	ldr	r3, [r7, #4]
 8003b38:	681b      	ldr	r3, [r3, #0]
 8003b3a:	430a      	orrs	r2, r1
 8003b3c:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX/TX pins swap */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
 8003b3e:	687b      	ldr	r3, [r7, #4]
 8003b40:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003b42:	f003 0308 	and.w	r3, r3, #8
 8003b46:	2b00      	cmp	r3, #0
 8003b48:	d00a      	beq.n	8003b60 <UART_AdvFeatureConfig+0x90>
  {
    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
 8003b4a:	687b      	ldr	r3, [r7, #4]
 8003b4c:	681b      	ldr	r3, [r3, #0]
 8003b4e:	685b      	ldr	r3, [r3, #4]
 8003b50:	f423 4100 	bic.w	r1, r3, #32768	; 0x8000
 8003b54:	687b      	ldr	r3, [r7, #4]
 8003b56:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 8003b58:	687b      	ldr	r3, [r7, #4]
 8003b5a:	681b      	ldr	r3, [r3, #0]
 8003b5c:	430a      	orrs	r2, r1
 8003b5e:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX overrun detection disabling */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
 8003b60:	687b      	ldr	r3, [r7, #4]
 8003b62:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003b64:	f003 0310 	and.w	r3, r3, #16
 8003b68:	2b00      	cmp	r3, #0
 8003b6a:	d00a      	beq.n	8003b82 <UART_AdvFeatureConfig+0xb2>
  {
    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
 8003b6c:	687b      	ldr	r3, [r7, #4]
 8003b6e:	681b      	ldr	r3, [r3, #0]
 8003b70:	689b      	ldr	r3, [r3, #8]
 8003b72:	f423 5180 	bic.w	r1, r3, #4096	; 0x1000
 8003b76:	687b      	ldr	r3, [r7, #4]
 8003b78:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 8003b7a:	687b      	ldr	r3, [r7, #4]
 8003b7c:	681b      	ldr	r3, [r3, #0]
 8003b7e:	430a      	orrs	r2, r1
 8003b80:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure DMA disabling on reception error */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
 8003b82:	687b      	ldr	r3, [r7, #4]
 8003b84:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003b86:	f003 0320 	and.w	r3, r3, #32
 8003b8a:	2b00      	cmp	r3, #0
 8003b8c:	d00a      	beq.n	8003ba4 <UART_AdvFeatureConfig+0xd4>
  {
    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
 8003b8e:	687b      	ldr	r3, [r7, #4]
 8003b90:	681b      	ldr	r3, [r3, #0]
 8003b92:	689b      	ldr	r3, [r3, #8]
 8003b94:	f423 5100 	bic.w	r1, r3, #8192	; 0x2000
 8003b98:	687b      	ldr	r3, [r7, #4]
 8003b9a:	6bda      	ldr	r2, [r3, #60]	; 0x3c
 8003b9c:	687b      	ldr	r3, [r7, #4]
 8003b9e:	681b      	ldr	r3, [r3, #0]
 8003ba0:	430a      	orrs	r2, r1
 8003ba2:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure auto Baud rate detection scheme */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
 8003ba4:	687b      	ldr	r3, [r7, #4]
 8003ba6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003ba8:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8003bac:	2b00      	cmp	r3, #0
 8003bae:	d01a      	beq.n	8003be6 <UART_AdvFeatureConfig+0x116>
  {
    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
 8003bb0:	687b      	ldr	r3, [r7, #4]
 8003bb2:	681b      	ldr	r3, [r3, #0]
 8003bb4:	685b      	ldr	r3, [r3, #4]
 8003bb6:	f423 1180 	bic.w	r1, r3, #1048576	; 0x100000
 8003bba:	687b      	ldr	r3, [r7, #4]
 8003bbc:	6c1a      	ldr	r2, [r3, #64]	; 0x40
 8003bbe:	687b      	ldr	r3, [r7, #4]
 8003bc0:	681b      	ldr	r3, [r3, #0]
 8003bc2:	430a      	orrs	r2, r1
 8003bc4:	605a      	str	r2, [r3, #4]
    /* set auto Baudrate detection parameters if detection is enabled */
    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
 8003bc6:	687b      	ldr	r3, [r7, #4]
 8003bc8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8003bca:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
 8003bce:	d10a      	bne.n	8003be6 <UART_AdvFeatureConfig+0x116>
    {
      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
 8003bd0:	687b      	ldr	r3, [r7, #4]
 8003bd2:	681b      	ldr	r3, [r3, #0]
 8003bd4:	685b      	ldr	r3, [r3, #4]
 8003bd6:	f423 01c0 	bic.w	r1, r3, #6291456	; 0x600000
 8003bda:	687b      	ldr	r3, [r7, #4]
 8003bdc:	6c5a      	ldr	r2, [r3, #68]	; 0x44
 8003bde:	687b      	ldr	r3, [r7, #4]
 8003be0:	681b      	ldr	r3, [r3, #0]
 8003be2:	430a      	orrs	r2, r1
 8003be4:	605a      	str	r2, [r3, #4]
    }
  }

  /* if required, configure MSB first on communication line */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
 8003be6:	687b      	ldr	r3, [r7, #4]
 8003be8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003bea:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8003bee:	2b00      	cmp	r3, #0
 8003bf0:	d00a      	beq.n	8003c08 <UART_AdvFeatureConfig+0x138>
  {
    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
 8003bf2:	687b      	ldr	r3, [r7, #4]
 8003bf4:	681b      	ldr	r3, [r3, #0]
 8003bf6:	685b      	ldr	r3, [r3, #4]
 8003bf8:	f423 2100 	bic.w	r1, r3, #524288	; 0x80000
 8003bfc:	687b      	ldr	r3, [r7, #4]
 8003bfe:	6c9a      	ldr	r2, [r3, #72]	; 0x48
 8003c00:	687b      	ldr	r3, [r7, #4]
 8003c02:	681b      	ldr	r3, [r3, #0]
 8003c04:	430a      	orrs	r2, r1
 8003c06:	605a      	str	r2, [r3, #4]
  }
}
 8003c08:	bf00      	nop
 8003c0a:	370c      	adds	r7, #12
 8003c0c:	46bd      	mov	sp, r7
 8003c0e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003c12:	4770      	bx	lr

08003c14 <UART_CheckIdleState>:
  * @brief Check the UART Idle State.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
 8003c14:	b580      	push	{r7, lr}
 8003c16:	b086      	sub	sp, #24
 8003c18:	af02      	add	r7, sp, #8
 8003c1a:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

  /* Initialize the UART ErrorCode */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8003c1c:	687b      	ldr	r3, [r7, #4]
 8003c1e:	2200      	movs	r2, #0
 8003c20:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80

  /* Init tickstart for timeout management */
  tickstart = HAL_GetTick();
 8003c24:	f7fd f86e 	bl	8000d04 <HAL_GetTick>
 8003c28:	60f8      	str	r0, [r7, #12]

  /* Check if the Transmitter is enabled */
  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
 8003c2a:	687b      	ldr	r3, [r7, #4]
 8003c2c:	681b      	ldr	r3, [r3, #0]
 8003c2e:	681b      	ldr	r3, [r3, #0]
 8003c30:	f003 0308 	and.w	r3, r3, #8
 8003c34:	2b08      	cmp	r3, #8
 8003c36:	d10e      	bne.n	8003c56 <UART_CheckIdleState+0x42>
  {
    /* Wait until TEACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 8003c38:	f06f 437e 	mvn.w	r3, #4261412864	; 0xfe000000
 8003c3c:	9300      	str	r3, [sp, #0]
 8003c3e:	68fb      	ldr	r3, [r7, #12]
 8003c40:	2200      	movs	r2, #0
 8003c42:	f44f 1100 	mov.w	r1, #2097152	; 0x200000
 8003c46:	6878      	ldr	r0, [r7, #4]
 8003c48:	f000 f82d 	bl	8003ca6 <UART_WaitOnFlagUntilTimeout>
 8003c4c:	4603      	mov	r3, r0
 8003c4e:	2b00      	cmp	r3, #0
 8003c50:	d001      	beq.n	8003c56 <UART_CheckIdleState+0x42>
    {
      /* Timeout occurred */
      return HAL_TIMEOUT;
 8003c52:	2303      	movs	r3, #3
 8003c54:	e023      	b.n	8003c9e <UART_CheckIdleState+0x8a>
    }
  }

  /* Check if the Receiver is enabled */
  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
 8003c56:	687b      	ldr	r3, [r7, #4]
 8003c58:	681b      	ldr	r3, [r3, #0]
 8003c5a:	681b      	ldr	r3, [r3, #0]
 8003c5c:	f003 0304 	and.w	r3, r3, #4
 8003c60:	2b04      	cmp	r3, #4
 8003c62:	d10e      	bne.n	8003c82 <UART_CheckIdleState+0x6e>
  {
    /* Wait until REACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 8003c64:	f06f 437e 	mvn.w	r3, #4261412864	; 0xfe000000
 8003c68:	9300      	str	r3, [sp, #0]
 8003c6a:	68fb      	ldr	r3, [r7, #12]
 8003c6c:	2200      	movs	r2, #0
 8003c6e:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
 8003c72:	6878      	ldr	r0, [r7, #4]
 8003c74:	f000 f817 	bl	8003ca6 <UART_WaitOnFlagUntilTimeout>
 8003c78:	4603      	mov	r3, r0
 8003c7a:	2b00      	cmp	r3, #0
 8003c7c:	d001      	beq.n	8003c82 <UART_CheckIdleState+0x6e>
    {
      /* Timeout occurred */
      return HAL_TIMEOUT;
 8003c7e:	2303      	movs	r3, #3
 8003c80:	e00d      	b.n	8003c9e <UART_CheckIdleState+0x8a>
    }
  }

  /* Initialize the UART State */
  huart->gState = HAL_UART_STATE_READY;
 8003c82:	687b      	ldr	r3, [r7, #4]
 8003c84:	2220      	movs	r2, #32
 8003c86:	679a      	str	r2, [r3, #120]	; 0x78
  huart->RxState = HAL_UART_STATE_READY;
 8003c88:	687b      	ldr	r3, [r7, #4]
 8003c8a:	2220      	movs	r2, #32
 8003c8c:	67da      	str	r2, [r3, #124]	; 0x7c
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8003c8e:	687b      	ldr	r3, [r7, #4]
 8003c90:	2200      	movs	r2, #0
 8003c92:	661a      	str	r2, [r3, #96]	; 0x60

  __HAL_UNLOCK(huart);
 8003c94:	687b      	ldr	r3, [r7, #4]
 8003c96:	2200      	movs	r2, #0
 8003c98:	f883 2074 	strb.w	r2, [r3, #116]	; 0x74

  return HAL_OK;
 8003c9c:	2300      	movs	r3, #0
}
 8003c9e:	4618      	mov	r0, r3
 8003ca0:	3710      	adds	r7, #16
 8003ca2:	46bd      	mov	sp, r7
 8003ca4:	bd80      	pop	{r7, pc}

08003ca6 <UART_WaitOnFlagUntilTimeout>:
  * @param Timeout   Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
                                              uint32_t Tickstart, uint32_t Timeout)
{
 8003ca6:	b580      	push	{r7, lr}
 8003ca8:	b09c      	sub	sp, #112	; 0x70
 8003caa:	af00      	add	r7, sp, #0
 8003cac:	60f8      	str	r0, [r7, #12]
 8003cae:	60b9      	str	r1, [r7, #8]
 8003cb0:	603b      	str	r3, [r7, #0]
 8003cb2:	4613      	mov	r3, r2
 8003cb4:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8003cb6:	e0a5      	b.n	8003e04 <UART_WaitOnFlagUntilTimeout+0x15e>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8003cb8:	6fbb      	ldr	r3, [r7, #120]	; 0x78
 8003cba:	f1b3 3fff 	cmp.w	r3, #4294967295
 8003cbe:	f000 80a1 	beq.w	8003e04 <UART_WaitOnFlagUntilTimeout+0x15e>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8003cc2:	f7fd f81f 	bl	8000d04 <HAL_GetTick>
 8003cc6:	4602      	mov	r2, r0
 8003cc8:	683b      	ldr	r3, [r7, #0]
 8003cca:	1ad3      	subs	r3, r2, r3
 8003ccc:	6fba      	ldr	r2, [r7, #120]	; 0x78
 8003cce:	429a      	cmp	r2, r3
 8003cd0:	d302      	bcc.n	8003cd8 <UART_WaitOnFlagUntilTimeout+0x32>
 8003cd2:	6fbb      	ldr	r3, [r7, #120]	; 0x78
 8003cd4:	2b00      	cmp	r3, #0
 8003cd6:	d13e      	bne.n	8003d56 <UART_WaitOnFlagUntilTimeout+0xb0>
           interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
                                                USART_CR1_TXEIE_TXFNFIE));
#else
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 8003cd8:	68fb      	ldr	r3, [r7, #12]
 8003cda:	681b      	ldr	r3, [r3, #0]
 8003cdc:	653b      	str	r3, [r7, #80]	; 0x50
 */
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
    uint32_t result;

   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8003cde:	6d3b      	ldr	r3, [r7, #80]	; 0x50
 8003ce0:	e853 3f00 	ldrex	r3, [r3]
 8003ce4:	64fb      	str	r3, [r7, #76]	; 0x4c
   return(result);
 8003ce6:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
 8003ce8:	f423 73d0 	bic.w	r3, r3, #416	; 0x1a0
 8003cec:	667b      	str	r3, [r7, #100]	; 0x64
 8003cee:	68fb      	ldr	r3, [r7, #12]
 8003cf0:	681b      	ldr	r3, [r3, #0]
 8003cf2:	461a      	mov	r2, r3
 8003cf4:	6e7b      	ldr	r3, [r7, #100]	; 0x64
 8003cf6:	65fb      	str	r3, [r7, #92]	; 0x5c
 8003cf8:	65ba      	str	r2, [r7, #88]	; 0x58
 */
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
   uint32_t result;

   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8003cfa:	6db9      	ldr	r1, [r7, #88]	; 0x58
 8003cfc:	6dfa      	ldr	r2, [r7, #92]	; 0x5c
 8003cfe:	e841 2300 	strex	r3, r2, [r1]
 8003d02:	657b      	str	r3, [r7, #84]	; 0x54
   return(result);
 8003d04:	6d7b      	ldr	r3, [r7, #84]	; 0x54
 8003d06:	2b00      	cmp	r3, #0
 8003d08:	d1e6      	bne.n	8003cd8 <UART_WaitOnFlagUntilTimeout+0x32>
#endif /* USART_CR1_FIFOEN */
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8003d0a:	68fb      	ldr	r3, [r7, #12]
 8003d0c:	681b      	ldr	r3, [r3, #0]
 8003d0e:	3308      	adds	r3, #8
 8003d10:	63fb      	str	r3, [r7, #60]	; 0x3c
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8003d12:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
 8003d14:	e853 3f00 	ldrex	r3, [r3]
 8003d18:	63bb      	str	r3, [r7, #56]	; 0x38
   return(result);
 8003d1a:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003d1c:	f023 0301 	bic.w	r3, r3, #1
 8003d20:	663b      	str	r3, [r7, #96]	; 0x60
 8003d22:	68fb      	ldr	r3, [r7, #12]
 8003d24:	681b      	ldr	r3, [r3, #0]
 8003d26:	3308      	adds	r3, #8
 8003d28:	6e3a      	ldr	r2, [r7, #96]	; 0x60
 8003d2a:	64ba      	str	r2, [r7, #72]	; 0x48
 8003d2c:	647b      	str	r3, [r7, #68]	; 0x44
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8003d2e:	6c79      	ldr	r1, [r7, #68]	; 0x44
 8003d30:	6cba      	ldr	r2, [r7, #72]	; 0x48
 8003d32:	e841 2300 	strex	r3, r2, [r1]
 8003d36:	643b      	str	r3, [r7, #64]	; 0x40
   return(result);
 8003d38:	6c3b      	ldr	r3, [r7, #64]	; 0x40
 8003d3a:	2b00      	cmp	r3, #0
 8003d3c:	d1e5      	bne.n	8003d0a <UART_WaitOnFlagUntilTimeout+0x64>

        huart->gState = HAL_UART_STATE_READY;
 8003d3e:	68fb      	ldr	r3, [r7, #12]
 8003d40:	2220      	movs	r2, #32
 8003d42:	679a      	str	r2, [r3, #120]	; 0x78
        huart->RxState = HAL_UART_STATE_READY;
 8003d44:	68fb      	ldr	r3, [r7, #12]
 8003d46:	2220      	movs	r2, #32
 8003d48:	67da      	str	r2, [r3, #124]	; 0x7c

        __HAL_UNLOCK(huart);
 8003d4a:	68fb      	ldr	r3, [r7, #12]
 8003d4c:	2200      	movs	r2, #0
 8003d4e:	f883 2074 	strb.w	r2, [r3, #116]	; 0x74

        return HAL_TIMEOUT;
 8003d52:	2303      	movs	r3, #3
 8003d54:	e067      	b.n	8003e26 <UART_WaitOnFlagUntilTimeout+0x180>
      }

      if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
 8003d56:	68fb      	ldr	r3, [r7, #12]
 8003d58:	681b      	ldr	r3, [r3, #0]
 8003d5a:	681b      	ldr	r3, [r3, #0]
 8003d5c:	f003 0304 	and.w	r3, r3, #4
 8003d60:	2b00      	cmp	r3, #0
 8003d62:	d04f      	beq.n	8003e04 <UART_WaitOnFlagUntilTimeout+0x15e>
      {
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
 8003d64:	68fb      	ldr	r3, [r7, #12]
 8003d66:	681b      	ldr	r3, [r3, #0]
 8003d68:	69db      	ldr	r3, [r3, #28]
 8003d6a:	f403 6300 	and.w	r3, r3, #2048	; 0x800
 8003d6e:	f5b3 6f00 	cmp.w	r3, #2048	; 0x800
 8003d72:	d147      	bne.n	8003e04 <UART_WaitOnFlagUntilTimeout+0x15e>
        {
          /* Clear Receiver Timeout flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 8003d74:	68fb      	ldr	r3, [r7, #12]
 8003d76:	681b      	ldr	r3, [r3, #0]
 8003d78:	f44f 6200 	mov.w	r2, #2048	; 0x800
 8003d7c:	621a      	str	r2, [r3, #32]
             interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
                                                  USART_CR1_TXEIE_TXFNFIE));
#else
          ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 8003d7e:	68fb      	ldr	r3, [r7, #12]
 8003d80:	681b      	ldr	r3, [r3, #0]
 8003d82:	62bb      	str	r3, [r7, #40]	; 0x28
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8003d84:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003d86:	e853 3f00 	ldrex	r3, [r3]
 8003d8a:	627b      	str	r3, [r7, #36]	; 0x24
   return(result);
 8003d8c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8003d8e:	f423 73d0 	bic.w	r3, r3, #416	; 0x1a0
 8003d92:	66fb      	str	r3, [r7, #108]	; 0x6c
 8003d94:	68fb      	ldr	r3, [r7, #12]
 8003d96:	681b      	ldr	r3, [r3, #0]
 8003d98:	461a      	mov	r2, r3
 8003d9a:	6efb      	ldr	r3, [r7, #108]	; 0x6c
 8003d9c:	637b      	str	r3, [r7, #52]	; 0x34
 8003d9e:	633a      	str	r2, [r7, #48]	; 0x30
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8003da0:	6b39      	ldr	r1, [r7, #48]	; 0x30
 8003da2:	6b7a      	ldr	r2, [r7, #52]	; 0x34
 8003da4:	e841 2300 	strex	r3, r2, [r1]
 8003da8:	62fb      	str	r3, [r7, #44]	; 0x2c
   return(result);
 8003daa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8003dac:	2b00      	cmp	r3, #0
 8003dae:	d1e6      	bne.n	8003d7e <UART_WaitOnFlagUntilTimeout+0xd8>
#endif /* USART_CR1_FIFOEN */
          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8003db0:	68fb      	ldr	r3, [r7, #12]
 8003db2:	681b      	ldr	r3, [r3, #0]
 8003db4:	3308      	adds	r3, #8
 8003db6:	617b      	str	r3, [r7, #20]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8003db8:	697b      	ldr	r3, [r7, #20]
 8003dba:	e853 3f00 	ldrex	r3, [r3]
 8003dbe:	613b      	str	r3, [r7, #16]
   return(result);
 8003dc0:	693b      	ldr	r3, [r7, #16]
 8003dc2:	f023 0301 	bic.w	r3, r3, #1
 8003dc6:	66bb      	str	r3, [r7, #104]	; 0x68
 8003dc8:	68fb      	ldr	r3, [r7, #12]
 8003dca:	681b      	ldr	r3, [r3, #0]
 8003dcc:	3308      	adds	r3, #8
 8003dce:	6eba      	ldr	r2, [r7, #104]	; 0x68
 8003dd0:	623a      	str	r2, [r7, #32]
 8003dd2:	61fb      	str	r3, [r7, #28]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8003dd4:	69f9      	ldr	r1, [r7, #28]
 8003dd6:	6a3a      	ldr	r2, [r7, #32]
 8003dd8:	e841 2300 	strex	r3, r2, [r1]
 8003ddc:	61bb      	str	r3, [r7, #24]
   return(result);
 8003dde:	69bb      	ldr	r3, [r7, #24]
 8003de0:	2b00      	cmp	r3, #0
 8003de2:	d1e5      	bne.n	8003db0 <UART_WaitOnFlagUntilTimeout+0x10a>

          huart->gState = HAL_UART_STATE_READY;
 8003de4:	68fb      	ldr	r3, [r7, #12]
 8003de6:	2220      	movs	r2, #32
 8003de8:	679a      	str	r2, [r3, #120]	; 0x78
          huart->RxState = HAL_UART_STATE_READY;
 8003dea:	68fb      	ldr	r3, [r7, #12]
 8003dec:	2220      	movs	r2, #32
 8003dee:	67da      	str	r2, [r3, #124]	; 0x7c
          huart->ErrorCode = HAL_UART_ERROR_RTO;
 8003df0:	68fb      	ldr	r3, [r7, #12]
 8003df2:	2220      	movs	r2, #32
 8003df4:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 8003df8:	68fb      	ldr	r3, [r7, #12]
 8003dfa:	2200      	movs	r2, #0
 8003dfc:	f883 2074 	strb.w	r2, [r3, #116]	; 0x74

          return HAL_TIMEOUT;
 8003e00:	2303      	movs	r3, #3
 8003e02:	e010      	b.n	8003e26 <UART_WaitOnFlagUntilTimeout+0x180>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8003e04:	68fb      	ldr	r3, [r7, #12]
 8003e06:	681b      	ldr	r3, [r3, #0]
 8003e08:	69da      	ldr	r2, [r3, #28]
 8003e0a:	68bb      	ldr	r3, [r7, #8]
 8003e0c:	4013      	ands	r3, r2
 8003e0e:	68ba      	ldr	r2, [r7, #8]
 8003e10:	429a      	cmp	r2, r3
 8003e12:	bf0c      	ite	eq
 8003e14:	2301      	moveq	r3, #1
 8003e16:	2300      	movne	r3, #0
 8003e18:	b2db      	uxtb	r3, r3
 8003e1a:	461a      	mov	r2, r3
 8003e1c:	79fb      	ldrb	r3, [r7, #7]
 8003e1e:	429a      	cmp	r2, r3
 8003e20:	f43f af4a 	beq.w	8003cb8 <UART_WaitOnFlagUntilTimeout+0x12>
        }
      }
    }
  }
  return HAL_OK;
 8003e24:	2300      	movs	r3, #0
}
 8003e26:	4618      	mov	r0, r3
 8003e28:	3770      	adds	r7, #112	; 0x70
 8003e2a:	46bd      	mov	sp, r7
 8003e2c:	bd80      	pop	{r7, pc}
	...

08003e30 <__NVIC_SetPriority>:
{
 8003e30:	b480      	push	{r7}
 8003e32:	b083      	sub	sp, #12
 8003e34:	af00      	add	r7, sp, #0
 8003e36:	4603      	mov	r3, r0
 8003e38:	6039      	str	r1, [r7, #0]
 8003e3a:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8003e3c:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8003e40:	2b00      	cmp	r3, #0
 8003e42:	db0a      	blt.n	8003e5a <__NVIC_SetPriority+0x2a>
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8003e44:	683b      	ldr	r3, [r7, #0]
 8003e46:	b2da      	uxtb	r2, r3
 8003e48:	490c      	ldr	r1, [pc, #48]	; (8003e7c <__NVIC_SetPriority+0x4c>)
 8003e4a:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8003e4e:	0112      	lsls	r2, r2, #4
 8003e50:	b2d2      	uxtb	r2, r2
 8003e52:	440b      	add	r3, r1
 8003e54:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
}
 8003e58:	e00a      	b.n	8003e70 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8003e5a:	683b      	ldr	r3, [r7, #0]
 8003e5c:	b2da      	uxtb	r2, r3
 8003e5e:	4908      	ldr	r1, [pc, #32]	; (8003e80 <__NVIC_SetPriority+0x50>)
 8003e60:	79fb      	ldrb	r3, [r7, #7]
 8003e62:	f003 030f 	and.w	r3, r3, #15
 8003e66:	3b04      	subs	r3, #4
 8003e68:	0112      	lsls	r2, r2, #4
 8003e6a:	b2d2      	uxtb	r2, r2
 8003e6c:	440b      	add	r3, r1
 8003e6e:	761a      	strb	r2, [r3, #24]
}
 8003e70:	bf00      	nop
 8003e72:	370c      	adds	r7, #12
 8003e74:	46bd      	mov	sp, r7
 8003e76:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003e7a:	4770      	bx	lr
 8003e7c:	e000e100 	.word	0xe000e100
 8003e80:	e000ed00 	.word	0xe000ed00

08003e84 <SysTick_Handler>:

/*
  SysTick handler implementation that also clears overflow flag.
*/
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
void SysTick_Handler (void) {
 8003e84:	b580      	push	{r7, lr}
 8003e86:	af00      	add	r7, sp, #0
  /* Clear overflow flag */
  SysTick->CTRL;
 8003e88:	4b05      	ldr	r3, [pc, #20]	; (8003ea0 <SysTick_Handler+0x1c>)
 8003e8a:	681b      	ldr	r3, [r3, #0]

  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
 8003e8c:	f001 fd34 	bl	80058f8 <xTaskGetSchedulerState>
 8003e90:	4603      	mov	r3, r0
 8003e92:	2b01      	cmp	r3, #1
 8003e94:	d001      	beq.n	8003e9a <SysTick_Handler+0x16>
    /* Call tick handler */
    xPortSysTickHandler();
 8003e96:	f002 fb1f 	bl	80064d8 <xPortSysTickHandler>
  }
}
 8003e9a:	bf00      	nop
 8003e9c:	bd80      	pop	{r7, pc}
 8003e9e:	bf00      	nop
 8003ea0:	e000e010 	.word	0xe000e010

08003ea4 <SVC_Setup>:
#endif /* SysTick */

/*
  Setup SVC to reset value.
*/
__STATIC_INLINE void SVC_Setup (void) {
 8003ea4:	b580      	push	{r7, lr}
 8003ea6:	af00      	add	r7, sp, #0
#if (__ARM_ARCH_7A__ == 0U)
  /* Service Call interrupt might be configured before kernel start     */
  /* and when its priority is lower or equal to BASEPRI, svc intruction */
  /* causes a Hard Fault.                                               */
  NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
 8003ea8:	2100      	movs	r1, #0
 8003eaa:	f06f 0004 	mvn.w	r0, #4
 8003eae:	f7ff ffbf 	bl	8003e30 <__NVIC_SetPriority>
#endif
}
 8003eb2:	bf00      	nop
 8003eb4:	bd80      	pop	{r7, pc}
	...

08003eb8 <osKernelInitialize>:
static uint32_t OS_Tick_GetOverflow (void);
/* Get OS Tick interval */
static uint32_t OS_Tick_GetInterval (void);
/*---------------------------------------------------------------------------*/

osStatus_t osKernelInitialize (void) {
 8003eb8:	b580      	push	{r7, lr}
 8003eba:	b082      	sub	sp, #8
 8003ebc:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8003ebe:	f3ef 8305 	mrs	r3, IPSR
 8003ec2:	603b      	str	r3, [r7, #0]
  return(result);
 8003ec4:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 8003ec6:	2b00      	cmp	r3, #0
 8003ec8:	d003      	beq.n	8003ed2 <osKernelInitialize+0x1a>
    stat = osErrorISR;
 8003eca:	f06f 0305 	mvn.w	r3, #5
 8003ece:	607b      	str	r3, [r7, #4]
 8003ed0:	e00f      	b.n	8003ef2 <osKernelInitialize+0x3a>
  }
  else {
    if (KernelState == osKernelInactive) {
 8003ed2:	4b0a      	ldr	r3, [pc, #40]	; (8003efc <osKernelInitialize+0x44>)
 8003ed4:	681b      	ldr	r3, [r3, #0]
 8003ed6:	2b00      	cmp	r3, #0
 8003ed8:	d108      	bne.n	8003eec <osKernelInitialize+0x34>
      #if defined(USE_TRACE_EVENT_RECORDER)
        EvrFreeRTOSSetup(0U);
      #endif
      #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
        vPortDefineHeapRegions (configHEAP_5_REGIONS);
 8003eda:	4809      	ldr	r0, [pc, #36]	; (8003f00 <osKernelInitialize+0x48>)
 8003edc:	f002 fcec 	bl	80068b8 <vPortDefineHeapRegions>
      #endif
      KernelState = osKernelReady;
 8003ee0:	4b06      	ldr	r3, [pc, #24]	; (8003efc <osKernelInitialize+0x44>)
 8003ee2:	2201      	movs	r2, #1
 8003ee4:	601a      	str	r2, [r3, #0]
      stat = osOK;
 8003ee6:	2300      	movs	r3, #0
 8003ee8:	607b      	str	r3, [r7, #4]
 8003eea:	e002      	b.n	8003ef2 <osKernelInitialize+0x3a>
    } else {
      stat = osError;
 8003eec:	f04f 33ff 	mov.w	r3, #4294967295
 8003ef0:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 8003ef2:	687b      	ldr	r3, [r7, #4]
}
 8003ef4:	4618      	mov	r0, r3
 8003ef6:	3708      	adds	r7, #8
 8003ef8:	46bd      	mov	sp, r7
 8003efa:	bd80      	pop	{r7, pc}
 8003efc:	20000240 	.word	0x20000240
 8003f00:	2000000c 	.word	0x2000000c

08003f04 <osKernelStart>:
  }

  return (state);
}

osStatus_t osKernelStart (void) {
 8003f04:	b580      	push	{r7, lr}
 8003f06:	b082      	sub	sp, #8
 8003f08:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8003f0a:	f3ef 8305 	mrs	r3, IPSR
 8003f0e:	603b      	str	r3, [r7, #0]
  return(result);
 8003f10:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 8003f12:	2b00      	cmp	r3, #0
 8003f14:	d003      	beq.n	8003f1e <osKernelStart+0x1a>
    stat = osErrorISR;
 8003f16:	f06f 0305 	mvn.w	r3, #5
 8003f1a:	607b      	str	r3, [r7, #4]
 8003f1c:	e010      	b.n	8003f40 <osKernelStart+0x3c>
  }
  else {
    if (KernelState == osKernelReady) {
 8003f1e:	4b0b      	ldr	r3, [pc, #44]	; (8003f4c <osKernelStart+0x48>)
 8003f20:	681b      	ldr	r3, [r3, #0]
 8003f22:	2b01      	cmp	r3, #1
 8003f24:	d109      	bne.n	8003f3a <osKernelStart+0x36>
      /* Ensure SVC priority is at the reset value */
      SVC_Setup();
 8003f26:	f7ff ffbd 	bl	8003ea4 <SVC_Setup>
      /* Change state to enable IRQ masking check */
      KernelState = osKernelRunning;
 8003f2a:	4b08      	ldr	r3, [pc, #32]	; (8003f4c <osKernelStart+0x48>)
 8003f2c:	2202      	movs	r2, #2
 8003f2e:	601a      	str	r2, [r3, #0]
      /* Start the kernel scheduler */
      vTaskStartScheduler();
 8003f30:	f001 f87c 	bl	800502c <vTaskStartScheduler>
      stat = osOK;
 8003f34:	2300      	movs	r3, #0
 8003f36:	607b      	str	r3, [r7, #4]
 8003f38:	e002      	b.n	8003f40 <osKernelStart+0x3c>
    } else {
      stat = osError;
 8003f3a:	f04f 33ff 	mov.w	r3, #4294967295
 8003f3e:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 8003f40:	687b      	ldr	r3, [r7, #4]
}
 8003f42:	4618      	mov	r0, r3
 8003f44:	3708      	adds	r7, #8
 8003f46:	46bd      	mov	sp, r7
 8003f48:	bd80      	pop	{r7, pc}
 8003f4a:	bf00      	nop
 8003f4c:	20000240 	.word	0x20000240

08003f50 <osThreadNew>:
  return (configCPU_CLOCK_HZ);
}

/*---------------------------------------------------------------------------*/

osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
 8003f50:	b580      	push	{r7, lr}
 8003f52:	b08e      	sub	sp, #56	; 0x38
 8003f54:	af04      	add	r7, sp, #16
 8003f56:	60f8      	str	r0, [r7, #12]
 8003f58:	60b9      	str	r1, [r7, #8]
 8003f5a:	607a      	str	r2, [r7, #4]
  uint32_t stack;
  TaskHandle_t hTask;
  UBaseType_t prio;
  int32_t mem;

  hTask = NULL;
 8003f5c:	2300      	movs	r3, #0
 8003f5e:	613b      	str	r3, [r7, #16]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8003f60:	f3ef 8305 	mrs	r3, IPSR
 8003f64:	617b      	str	r3, [r7, #20]
  return(result);
 8003f66:	697b      	ldr	r3, [r7, #20]

  if (!IS_IRQ() && (func != NULL)) {
 8003f68:	2b00      	cmp	r3, #0
 8003f6a:	d17e      	bne.n	800406a <osThreadNew+0x11a>
 8003f6c:	68fb      	ldr	r3, [r7, #12]
 8003f6e:	2b00      	cmp	r3, #0
 8003f70:	d07b      	beq.n	800406a <osThreadNew+0x11a>
    stack = configMINIMAL_STACK_SIZE;
 8003f72:	2380      	movs	r3, #128	; 0x80
 8003f74:	623b      	str	r3, [r7, #32]
    prio  = (UBaseType_t)osPriorityNormal;
 8003f76:	2318      	movs	r3, #24
 8003f78:	61fb      	str	r3, [r7, #28]

    name = NULL;
 8003f7a:	2300      	movs	r3, #0
 8003f7c:	627b      	str	r3, [r7, #36]	; 0x24
    mem  = -1;
 8003f7e:	f04f 33ff 	mov.w	r3, #4294967295
 8003f82:	61bb      	str	r3, [r7, #24]

    if (attr != NULL) {
 8003f84:	687b      	ldr	r3, [r7, #4]
 8003f86:	2b00      	cmp	r3, #0
 8003f88:	d045      	beq.n	8004016 <osThreadNew+0xc6>
      if (attr->name != NULL) {
 8003f8a:	687b      	ldr	r3, [r7, #4]
 8003f8c:	681b      	ldr	r3, [r3, #0]
 8003f8e:	2b00      	cmp	r3, #0
 8003f90:	d002      	beq.n	8003f98 <osThreadNew+0x48>
        name = attr->name;
 8003f92:	687b      	ldr	r3, [r7, #4]
 8003f94:	681b      	ldr	r3, [r3, #0]
 8003f96:	627b      	str	r3, [r7, #36]	; 0x24
      }
      if (attr->priority != osPriorityNone) {
 8003f98:	687b      	ldr	r3, [r7, #4]
 8003f9a:	699b      	ldr	r3, [r3, #24]
 8003f9c:	2b00      	cmp	r3, #0
 8003f9e:	d002      	beq.n	8003fa6 <osThreadNew+0x56>
        prio = (UBaseType_t)attr->priority;
 8003fa0:	687b      	ldr	r3, [r7, #4]
 8003fa2:	699b      	ldr	r3, [r3, #24]
 8003fa4:	61fb      	str	r3, [r7, #28]
      }

      if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
 8003fa6:	69fb      	ldr	r3, [r7, #28]
 8003fa8:	2b00      	cmp	r3, #0
 8003faa:	d008      	beq.n	8003fbe <osThreadNew+0x6e>
 8003fac:	69fb      	ldr	r3, [r7, #28]
 8003fae:	2b38      	cmp	r3, #56	; 0x38
 8003fb0:	d805      	bhi.n	8003fbe <osThreadNew+0x6e>
 8003fb2:	687b      	ldr	r3, [r7, #4]
 8003fb4:	685b      	ldr	r3, [r3, #4]
 8003fb6:	f003 0301 	and.w	r3, r3, #1
 8003fba:	2b00      	cmp	r3, #0
 8003fbc:	d001      	beq.n	8003fc2 <osThreadNew+0x72>
        return (NULL);
 8003fbe:	2300      	movs	r3, #0
 8003fc0:	e054      	b.n	800406c <osThreadNew+0x11c>
      }

      if (attr->stack_size > 0U) {
 8003fc2:	687b      	ldr	r3, [r7, #4]
 8003fc4:	695b      	ldr	r3, [r3, #20]
 8003fc6:	2b00      	cmp	r3, #0
 8003fc8:	d003      	beq.n	8003fd2 <osThreadNew+0x82>
        /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports.       */
        /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
        stack = attr->stack_size / sizeof(StackType_t);
 8003fca:	687b      	ldr	r3, [r7, #4]
 8003fcc:	695b      	ldr	r3, [r3, #20]
 8003fce:	089b      	lsrs	r3, r3, #2
 8003fd0:	623b      	str	r3, [r7, #32]
      }

      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
 8003fd2:	687b      	ldr	r3, [r7, #4]
 8003fd4:	689b      	ldr	r3, [r3, #8]
 8003fd6:	2b00      	cmp	r3, #0
 8003fd8:	d00e      	beq.n	8003ff8 <osThreadNew+0xa8>
 8003fda:	687b      	ldr	r3, [r7, #4]
 8003fdc:	68db      	ldr	r3, [r3, #12]
 8003fde:	2bbb      	cmp	r3, #187	; 0xbb
 8003fe0:	d90a      	bls.n	8003ff8 <osThreadNew+0xa8>
          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
 8003fe2:	687b      	ldr	r3, [r7, #4]
 8003fe4:	691b      	ldr	r3, [r3, #16]
      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
 8003fe6:	2b00      	cmp	r3, #0
 8003fe8:	d006      	beq.n	8003ff8 <osThreadNew+0xa8>
          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
 8003fea:	687b      	ldr	r3, [r7, #4]
 8003fec:	695b      	ldr	r3, [r3, #20]
 8003fee:	2b00      	cmp	r3, #0
 8003ff0:	d002      	beq.n	8003ff8 <osThreadNew+0xa8>
        mem = 1;
 8003ff2:	2301      	movs	r3, #1
 8003ff4:	61bb      	str	r3, [r7, #24]
 8003ff6:	e010      	b.n	800401a <osThreadNew+0xca>
      }
      else {
        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
 8003ff8:	687b      	ldr	r3, [r7, #4]
 8003ffa:	689b      	ldr	r3, [r3, #8]
 8003ffc:	2b00      	cmp	r3, #0
 8003ffe:	d10c      	bne.n	800401a <osThreadNew+0xca>
 8004000:	687b      	ldr	r3, [r7, #4]
 8004002:	68db      	ldr	r3, [r3, #12]
 8004004:	2b00      	cmp	r3, #0
 8004006:	d108      	bne.n	800401a <osThreadNew+0xca>
 8004008:	687b      	ldr	r3, [r7, #4]
 800400a:	691b      	ldr	r3, [r3, #16]
 800400c:	2b00      	cmp	r3, #0
 800400e:	d104      	bne.n	800401a <osThreadNew+0xca>
          mem = 0;
 8004010:	2300      	movs	r3, #0
 8004012:	61bb      	str	r3, [r7, #24]
 8004014:	e001      	b.n	800401a <osThreadNew+0xca>
        }
      }
    }
    else {
      mem = 0;
 8004016:	2300      	movs	r3, #0
 8004018:	61bb      	str	r3, [r7, #24]
    }

    if (mem == 1) {
 800401a:	69bb      	ldr	r3, [r7, #24]
 800401c:	2b01      	cmp	r3, #1
 800401e:	d110      	bne.n	8004042 <osThreadNew+0xf2>
      #if (configSUPPORT_STATIC_ALLOCATION == 1)
        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
 8004020:	687b      	ldr	r3, [r7, #4]
 8004022:	691b      	ldr	r3, [r3, #16]
                                                                                      (StaticTask_t *)attr->cb_mem);
 8004024:	687a      	ldr	r2, [r7, #4]
 8004026:	6892      	ldr	r2, [r2, #8]
        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
 8004028:	9202      	str	r2, [sp, #8]
 800402a:	9301      	str	r3, [sp, #4]
 800402c:	69fb      	ldr	r3, [r7, #28]
 800402e:	9300      	str	r3, [sp, #0]
 8004030:	68bb      	ldr	r3, [r7, #8]
 8004032:	6a3a      	ldr	r2, [r7, #32]
 8004034:	6a79      	ldr	r1, [r7, #36]	; 0x24
 8004036:	68f8      	ldr	r0, [r7, #12]
 8004038:	f000 fe0c 	bl	8004c54 <xTaskCreateStatic>
 800403c:	4603      	mov	r3, r0
 800403e:	613b      	str	r3, [r7, #16]
 8004040:	e013      	b.n	800406a <osThreadNew+0x11a>
      #endif
    }
    else {
      if (mem == 0) {
 8004042:	69bb      	ldr	r3, [r7, #24]
 8004044:	2b00      	cmp	r3, #0
 8004046:	d110      	bne.n	800406a <osThreadNew+0x11a>
        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
          if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
 8004048:	6a3b      	ldr	r3, [r7, #32]
 800404a:	b29a      	uxth	r2, r3
 800404c:	f107 0310 	add.w	r3, r7, #16
 8004050:	9301      	str	r3, [sp, #4]
 8004052:	69fb      	ldr	r3, [r7, #28]
 8004054:	9300      	str	r3, [sp, #0]
 8004056:	68bb      	ldr	r3, [r7, #8]
 8004058:	6a79      	ldr	r1, [r7, #36]	; 0x24
 800405a:	68f8      	ldr	r0, [r7, #12]
 800405c:	f000 fe57 	bl	8004d0e <xTaskCreate>
 8004060:	4603      	mov	r3, r0
 8004062:	2b01      	cmp	r3, #1
 8004064:	d001      	beq.n	800406a <osThreadNew+0x11a>
            hTask = NULL;
 8004066:	2300      	movs	r3, #0
 8004068:	613b      	str	r3, [r7, #16]
        #endif
      }
    }
  }

  return ((osThreadId_t)hTask);
 800406a:	693b      	ldr	r3, [r7, #16]
}
 800406c:	4618      	mov	r0, r3
 800406e:	3728      	adds	r7, #40	; 0x28
 8004070:	46bd      	mov	sp, r7
 8004072:	bd80      	pop	{r7, pc}

08004074 <osDelay>:
  /* Return flags before clearing */
  return (rflags);
}
#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */

osStatus_t osDelay (uint32_t ticks) {
 8004074:	b580      	push	{r7, lr}
 8004076:	b084      	sub	sp, #16
 8004078:	af00      	add	r7, sp, #0
 800407a:	6078      	str	r0, [r7, #4]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800407c:	f3ef 8305 	mrs	r3, IPSR
 8004080:	60bb      	str	r3, [r7, #8]
  return(result);
 8004082:	68bb      	ldr	r3, [r7, #8]
  osStatus_t stat;

  if (IS_IRQ()) {
 8004084:	2b00      	cmp	r3, #0
 8004086:	d003      	beq.n	8004090 <osDelay+0x1c>
    stat = osErrorISR;
 8004088:	f06f 0305 	mvn.w	r3, #5
 800408c:	60fb      	str	r3, [r7, #12]
 800408e:	e007      	b.n	80040a0 <osDelay+0x2c>
  }
  else {
    stat = osOK;
 8004090:	2300      	movs	r3, #0
 8004092:	60fb      	str	r3, [r7, #12]

    if (ticks != 0U) {
 8004094:	687b      	ldr	r3, [r7, #4]
 8004096:	2b00      	cmp	r3, #0
 8004098:	d002      	beq.n	80040a0 <osDelay+0x2c>
      vTaskDelay(ticks);
 800409a:	6878      	ldr	r0, [r7, #4]
 800409c:	f000 ff92 	bl	8004fc4 <vTaskDelay>
    }
  }

  return (stat);
 80040a0:	68fb      	ldr	r3, [r7, #12]
}
 80040a2:	4618      	mov	r0, r3
 80040a4:	3710      	adds	r7, #16
 80040a6:	46bd      	mov	sp, r7
 80040a8:	bd80      	pop	{r7, pc}
	...

080040ac <vApplicationGetIdleTaskMemory>:

/*
  vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
 80040ac:	b480      	push	{r7}
 80040ae:	b085      	sub	sp, #20
 80040b0:	af00      	add	r7, sp, #0
 80040b2:	60f8      	str	r0, [r7, #12]
 80040b4:	60b9      	str	r1, [r7, #8]
 80040b6:	607a      	str	r2, [r7, #4]
  /* Idle task control block and stack */
  static StaticTask_t Idle_TCB;
  static StackType_t  Idle_Stack[configMINIMAL_STACK_SIZE];

  *ppxIdleTaskTCBBuffer   = &Idle_TCB;
 80040b8:	68fb      	ldr	r3, [r7, #12]
 80040ba:	4a07      	ldr	r2, [pc, #28]	; (80040d8 <vApplicationGetIdleTaskMemory+0x2c>)
 80040bc:	601a      	str	r2, [r3, #0]
  *ppxIdleTaskStackBuffer = &Idle_Stack[0];
 80040be:	68bb      	ldr	r3, [r7, #8]
 80040c0:	4a06      	ldr	r2, [pc, #24]	; (80040dc <vApplicationGetIdleTaskMemory+0x30>)
 80040c2:	601a      	str	r2, [r3, #0]
  *pulIdleTaskStackSize   = (uint32_t)configMINIMAL_STACK_SIZE;
 80040c4:	687b      	ldr	r3, [r7, #4]
 80040c6:	2280      	movs	r2, #128	; 0x80
 80040c8:	601a      	str	r2, [r3, #0]
}
 80040ca:	bf00      	nop
 80040cc:	3714      	adds	r7, #20
 80040ce:	46bd      	mov	sp, r7
 80040d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80040d4:	4770      	bx	lr
 80040d6:	bf00      	nop
 80040d8:	20003124 	.word	0x20003124
 80040dc:	200031e0 	.word	0x200031e0

080040e0 <vApplicationGetTimerTaskMemory>:

/*
  vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
 80040e0:	b480      	push	{r7}
 80040e2:	b085      	sub	sp, #20
 80040e4:	af00      	add	r7, sp, #0
 80040e6:	60f8      	str	r0, [r7, #12]
 80040e8:	60b9      	str	r1, [r7, #8]
 80040ea:	607a      	str	r2, [r7, #4]
  /* Timer task control block and stack */
  static StaticTask_t Timer_TCB;
  static StackType_t  Timer_Stack[configTIMER_TASK_STACK_DEPTH];

  *ppxTimerTaskTCBBuffer   = &Timer_TCB;
 80040ec:	68fb      	ldr	r3, [r7, #12]
 80040ee:	4a07      	ldr	r2, [pc, #28]	; (800410c <vApplicationGetTimerTaskMemory+0x2c>)
 80040f0:	601a      	str	r2, [r3, #0]
  *ppxTimerTaskStackBuffer = &Timer_Stack[0];
 80040f2:	68bb      	ldr	r3, [r7, #8]
 80040f4:	4a06      	ldr	r2, [pc, #24]	; (8004110 <vApplicationGetTimerTaskMemory+0x30>)
 80040f6:	601a      	str	r2, [r3, #0]
  *pulTimerTaskStackSize   = (uint32_t)configTIMER_TASK_STACK_DEPTH;
 80040f8:	687b      	ldr	r3, [r7, #4]
 80040fa:	f44f 7280 	mov.w	r2, #256	; 0x100
 80040fe:	601a      	str	r2, [r3, #0]
}
 8004100:	bf00      	nop
 8004102:	3714      	adds	r7, #20
 8004104:	46bd      	mov	sp, r7
 8004106:	f85d 7b04 	ldr.w	r7, [sp], #4
 800410a:	4770      	bx	lr
 800410c:	200033e0 	.word	0x200033e0
 8004110:	2000349c 	.word	0x2000349c

08004114 <vListInitialise>:
/*-----------------------------------------------------------
 * PUBLIC LIST API documented in list.h
 *----------------------------------------------------------*/

void vListInitialise( List_t * const pxList )
{
 8004114:	b480      	push	{r7}
 8004116:	b083      	sub	sp, #12
 8004118:	af00      	add	r7, sp, #0
 800411a:	6078      	str	r0, [r7, #4]
	/* The list structure contains a list item which is used to mark the
	end of the list.  To initialise the list the list end is inserted
	as the only list entry. */
	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 800411c:	687b      	ldr	r3, [r7, #4]
 800411e:	f103 0208 	add.w	r2, r3, #8
 8004122:	687b      	ldr	r3, [r7, #4]
 8004124:	605a      	str	r2, [r3, #4]

	/* The list end value is the highest possible value in the list to
	ensure it remains at the end of the list. */
	pxList->xListEnd.xItemValue = portMAX_DELAY;
 8004126:	687b      	ldr	r3, [r7, #4]
 8004128:	f04f 32ff 	mov.w	r2, #4294967295
 800412c:	609a      	str	r2, [r3, #8]

	/* The list end next and previous pointers point to itself so we know
	when the list is empty. */
	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 800412e:	687b      	ldr	r3, [r7, #4]
 8004130:	f103 0208 	add.w	r2, r3, #8
 8004134:	687b      	ldr	r3, [r7, #4]
 8004136:	60da      	str	r2, [r3, #12]
	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 8004138:	687b      	ldr	r3, [r7, #4]
 800413a:	f103 0208 	add.w	r2, r3, #8
 800413e:	687b      	ldr	r3, [r7, #4]
 8004140:	611a      	str	r2, [r3, #16]

	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
 8004142:	687b      	ldr	r3, [r7, #4]
 8004144:	2200      	movs	r2, #0
 8004146:	601a      	str	r2, [r3, #0]

	/* Write known values into the list if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
 8004148:	bf00      	nop
 800414a:	370c      	adds	r7, #12
 800414c:	46bd      	mov	sp, r7
 800414e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004152:	4770      	bx	lr

08004154 <vListInitialiseItem>:
/*-----------------------------------------------------------*/

void vListInitialiseItem( ListItem_t * const pxItem )
{
 8004154:	b480      	push	{r7}
 8004156:	b083      	sub	sp, #12
 8004158:	af00      	add	r7, sp, #0
 800415a:	6078      	str	r0, [r7, #4]
	/* Make sure the list item is not recorded as being on a list. */
	pxItem->pxContainer = NULL;
 800415c:	687b      	ldr	r3, [r7, #4]
 800415e:	2200      	movs	r2, #0
 8004160:	611a      	str	r2, [r3, #16]

	/* Write known values into the list item if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
 8004162:	bf00      	nop
 8004164:	370c      	adds	r7, #12
 8004166:	46bd      	mov	sp, r7
 8004168:	f85d 7b04 	ldr.w	r7, [sp], #4
 800416c:	4770      	bx	lr

0800416e <vListInsertEnd>:
/*-----------------------------------------------------------*/

void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 800416e:	b480      	push	{r7}
 8004170:	b085      	sub	sp, #20
 8004172:	af00      	add	r7, sp, #0
 8004174:	6078      	str	r0, [r7, #4]
 8004176:	6039      	str	r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
 8004178:	687b      	ldr	r3, [r7, #4]
 800417a:	685b      	ldr	r3, [r3, #4]
 800417c:	60fb      	str	r3, [r7, #12]
	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );

	/* Insert a new list item into pxList, but rather than sort the list,
	makes the new list item the last item to be removed by a call to
	listGET_OWNER_OF_NEXT_ENTRY(). */
	pxNewListItem->pxNext = pxIndex;
 800417e:	683b      	ldr	r3, [r7, #0]
 8004180:	68fa      	ldr	r2, [r7, #12]
 8004182:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
 8004184:	68fb      	ldr	r3, [r7, #12]
 8004186:	689a      	ldr	r2, [r3, #8]
 8004188:	683b      	ldr	r3, [r7, #0]
 800418a:	609a      	str	r2, [r3, #8]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	pxIndex->pxPrevious->pxNext = pxNewListItem;
 800418c:	68fb      	ldr	r3, [r7, #12]
 800418e:	689b      	ldr	r3, [r3, #8]
 8004190:	683a      	ldr	r2, [r7, #0]
 8004192:	605a      	str	r2, [r3, #4]
	pxIndex->pxPrevious = pxNewListItem;
 8004194:	68fb      	ldr	r3, [r7, #12]
 8004196:	683a      	ldr	r2, [r7, #0]
 8004198:	609a      	str	r2, [r3, #8]

	/* Remember which list the item is in. */
	pxNewListItem->pxContainer = pxList;
 800419a:	683b      	ldr	r3, [r7, #0]
 800419c:	687a      	ldr	r2, [r7, #4]
 800419e:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 80041a0:	687b      	ldr	r3, [r7, #4]
 80041a2:	681b      	ldr	r3, [r3, #0]
 80041a4:	1c5a      	adds	r2, r3, #1
 80041a6:	687b      	ldr	r3, [r7, #4]
 80041a8:	601a      	str	r2, [r3, #0]
}
 80041aa:	bf00      	nop
 80041ac:	3714      	adds	r7, #20
 80041ae:	46bd      	mov	sp, r7
 80041b0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80041b4:	4770      	bx	lr

080041b6 <vListInsert>:
/*-----------------------------------------------------------*/

void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 80041b6:	b480      	push	{r7}
 80041b8:	b085      	sub	sp, #20
 80041ba:	af00      	add	r7, sp, #0
 80041bc:	6078      	str	r0, [r7, #4]
 80041be:	6039      	str	r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 80041c0:	683b      	ldr	r3, [r7, #0]
 80041c2:	681b      	ldr	r3, [r3, #0]
 80041c4:	60bb      	str	r3, [r7, #8]
	new list item should be placed after it.  This ensures that TCBs which are
	stored in ready lists (all of which have the same xItemValue value) get a
	share of the CPU.  However, if the xItemValue is the same as the back marker
	the iteration loop below will not end.  Therefore the value is checked
	first, and the algorithm slightly modified if necessary. */
	if( xValueOfInsertion == portMAX_DELAY )
 80041c6:	68bb      	ldr	r3, [r7, #8]
 80041c8:	f1b3 3fff 	cmp.w	r3, #4294967295
 80041cc:	d103      	bne.n	80041d6 <vListInsert+0x20>
	{
		pxIterator = pxList->xListEnd.pxPrevious;
 80041ce:	687b      	ldr	r3, [r7, #4]
 80041d0:	691b      	ldr	r3, [r3, #16]
 80041d2:	60fb      	str	r3, [r7, #12]
 80041d4:	e00c      	b.n	80041f0 <vListInsert+0x3a>
			4) Using a queue or semaphore before it has been initialised or
			   before the scheduler has been started (are interrupts firing
			   before vTaskStartScheduler() has been called?).
		**********************************************************************/

		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
 80041d6:	687b      	ldr	r3, [r7, #4]
 80041d8:	3308      	adds	r3, #8
 80041da:	60fb      	str	r3, [r7, #12]
 80041dc:	e002      	b.n	80041e4 <vListInsert+0x2e>
 80041de:	68fb      	ldr	r3, [r7, #12]
 80041e0:	685b      	ldr	r3, [r3, #4]
 80041e2:	60fb      	str	r3, [r7, #12]
 80041e4:	68fb      	ldr	r3, [r7, #12]
 80041e6:	685b      	ldr	r3, [r3, #4]
 80041e8:	681b      	ldr	r3, [r3, #0]
 80041ea:	68ba      	ldr	r2, [r7, #8]
 80041ec:	429a      	cmp	r2, r3
 80041ee:	d2f6      	bcs.n	80041de <vListInsert+0x28>
			/* There is nothing to do here, just iterating to the wanted
			insertion position. */
		}
	}

	pxNewListItem->pxNext = pxIterator->pxNext;
 80041f0:	68fb      	ldr	r3, [r7, #12]
 80041f2:	685a      	ldr	r2, [r3, #4]
 80041f4:	683b      	ldr	r3, [r7, #0]
 80041f6:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
 80041f8:	683b      	ldr	r3, [r7, #0]
 80041fa:	685b      	ldr	r3, [r3, #4]
 80041fc:	683a      	ldr	r2, [r7, #0]
 80041fe:	609a      	str	r2, [r3, #8]
	pxNewListItem->pxPrevious = pxIterator;
 8004200:	683b      	ldr	r3, [r7, #0]
 8004202:	68fa      	ldr	r2, [r7, #12]
 8004204:	609a      	str	r2, [r3, #8]
	pxIterator->pxNext = pxNewListItem;
 8004206:	68fb      	ldr	r3, [r7, #12]
 8004208:	683a      	ldr	r2, [r7, #0]
 800420a:	605a      	str	r2, [r3, #4]

	/* Remember which list the item is in.  This allows fast removal of the
	item later. */
	pxNewListItem->pxContainer = pxList;
 800420c:	683b      	ldr	r3, [r7, #0]
 800420e:	687a      	ldr	r2, [r7, #4]
 8004210:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 8004212:	687b      	ldr	r3, [r7, #4]
 8004214:	681b      	ldr	r3, [r3, #0]
 8004216:	1c5a      	adds	r2, r3, #1
 8004218:	687b      	ldr	r3, [r7, #4]
 800421a:	601a      	str	r2, [r3, #0]
}
 800421c:	bf00      	nop
 800421e:	3714      	adds	r7, #20
 8004220:	46bd      	mov	sp, r7
 8004222:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004226:	4770      	bx	lr

08004228 <uxListRemove>:
/*-----------------------------------------------------------*/

UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
 8004228:	b480      	push	{r7}
 800422a:	b085      	sub	sp, #20
 800422c:	af00      	add	r7, sp, #0
 800422e:	6078      	str	r0, [r7, #4]
/* The list item knows which list it is in.  Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
 8004230:	687b      	ldr	r3, [r7, #4]
 8004232:	691b      	ldr	r3, [r3, #16]
 8004234:	60fb      	str	r3, [r7, #12]

	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
 8004236:	687b      	ldr	r3, [r7, #4]
 8004238:	685b      	ldr	r3, [r3, #4]
 800423a:	687a      	ldr	r2, [r7, #4]
 800423c:	6892      	ldr	r2, [r2, #8]
 800423e:	609a      	str	r2, [r3, #8]
	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
 8004240:	687b      	ldr	r3, [r7, #4]
 8004242:	689b      	ldr	r3, [r3, #8]
 8004244:	687a      	ldr	r2, [r7, #4]
 8004246:	6852      	ldr	r2, [r2, #4]
 8004248:	605a      	str	r2, [r3, #4]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	/* Make sure the index is left pointing to a valid item. */
	if( pxList->pxIndex == pxItemToRemove )
 800424a:	68fb      	ldr	r3, [r7, #12]
 800424c:	685b      	ldr	r3, [r3, #4]
 800424e:	687a      	ldr	r2, [r7, #4]
 8004250:	429a      	cmp	r2, r3
 8004252:	d103      	bne.n	800425c <uxListRemove+0x34>
	{
		pxList->pxIndex = pxItemToRemove->pxPrevious;
 8004254:	687b      	ldr	r3, [r7, #4]
 8004256:	689a      	ldr	r2, [r3, #8]
 8004258:	68fb      	ldr	r3, [r7, #12]
 800425a:	605a      	str	r2, [r3, #4]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxItemToRemove->pxContainer = NULL;
 800425c:	687b      	ldr	r3, [r7, #4]
 800425e:	2200      	movs	r2, #0
 8004260:	611a      	str	r2, [r3, #16]
	( pxList->uxNumberOfItems )--;
 8004262:	68fb      	ldr	r3, [r7, #12]
 8004264:	681b      	ldr	r3, [r3, #0]
 8004266:	1e5a      	subs	r2, r3, #1
 8004268:	68fb      	ldr	r3, [r7, #12]
 800426a:	601a      	str	r2, [r3, #0]

	return pxList->uxNumberOfItems;
 800426c:	68fb      	ldr	r3, [r7, #12]
 800426e:	681b      	ldr	r3, [r3, #0]
}
 8004270:	4618      	mov	r0, r3
 8004272:	3714      	adds	r7, #20
 8004274:	46bd      	mov	sp, r7
 8004276:	f85d 7b04 	ldr.w	r7, [sp], #4
 800427a:	4770      	bx	lr

0800427c <xQueueGenericReset>:
	}														\
	taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
 800427c:	b580      	push	{r7, lr}
 800427e:	b084      	sub	sp, #16
 8004280:	af00      	add	r7, sp, #0
 8004282:	6078      	str	r0, [r7, #4]
 8004284:	6039      	str	r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
 8004286:	687b      	ldr	r3, [r7, #4]
 8004288:	60fb      	str	r3, [r7, #12]

	configASSERT( pxQueue );
 800428a:	68fb      	ldr	r3, [r7, #12]
 800428c:	2b00      	cmp	r3, #0
 800428e:	d10a      	bne.n	80042a6 <xQueueGenericReset+0x2a>

portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;

	__asm volatile
 8004290:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004294:	f383 8811 	msr	BASEPRI, r3
 8004298:	f3bf 8f6f 	isb	sy
 800429c:	f3bf 8f4f 	dsb	sy
 80042a0:	60bb      	str	r3, [r7, #8]
		"	msr basepri, %0											\n" \
		"	isb														\n" \
		"	dsb														\n" \
		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);
}
 80042a2:	bf00      	nop
 80042a4:	e7fe      	b.n	80042a4 <xQueueGenericReset+0x28>

	taskENTER_CRITICAL();
 80042a6:	f002 f885 	bl	80063b4 <vPortEnterCritical>
	{
		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 80042aa:	68fb      	ldr	r3, [r7, #12]
 80042ac:	681a      	ldr	r2, [r3, #0]
 80042ae:	68fb      	ldr	r3, [r7, #12]
 80042b0:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80042b2:	68f9      	ldr	r1, [r7, #12]
 80042b4:	6c09      	ldr	r1, [r1, #64]	; 0x40
 80042b6:	fb01 f303 	mul.w	r3, r1, r3
 80042ba:	441a      	add	r2, r3
 80042bc:	68fb      	ldr	r3, [r7, #12]
 80042be:	609a      	str	r2, [r3, #8]
		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
 80042c0:	68fb      	ldr	r3, [r7, #12]
 80042c2:	2200      	movs	r2, #0
 80042c4:	639a      	str	r2, [r3, #56]	; 0x38
		pxQueue->pcWriteTo = pxQueue->pcHead;
 80042c6:	68fb      	ldr	r3, [r7, #12]
 80042c8:	681a      	ldr	r2, [r3, #0]
 80042ca:	68fb      	ldr	r3, [r7, #12]
 80042cc:	605a      	str	r2, [r3, #4]
		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 80042ce:	68fb      	ldr	r3, [r7, #12]
 80042d0:	681a      	ldr	r2, [r3, #0]
 80042d2:	68fb      	ldr	r3, [r7, #12]
 80042d4:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80042d6:	3b01      	subs	r3, #1
 80042d8:	68f9      	ldr	r1, [r7, #12]
 80042da:	6c09      	ldr	r1, [r1, #64]	; 0x40
 80042dc:	fb01 f303 	mul.w	r3, r1, r3
 80042e0:	441a      	add	r2, r3
 80042e2:	68fb      	ldr	r3, [r7, #12]
 80042e4:	60da      	str	r2, [r3, #12]
		pxQueue->cRxLock = queueUNLOCKED;
 80042e6:	68fb      	ldr	r3, [r7, #12]
 80042e8:	22ff      	movs	r2, #255	; 0xff
 80042ea:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
		pxQueue->cTxLock = queueUNLOCKED;
 80042ee:	68fb      	ldr	r3, [r7, #12]
 80042f0:	22ff      	movs	r2, #255	; 0xff
 80042f2:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45

		if( xNewQueue == pdFALSE )
 80042f6:	683b      	ldr	r3, [r7, #0]
 80042f8:	2b00      	cmp	r3, #0
 80042fa:	d114      	bne.n	8004326 <xQueueGenericReset+0xaa>
			/* If there are tasks blocked waiting to read from the queue, then
			the tasks will remain blocked as after this function exits the queue
			will still be empty.  If there are tasks blocked waiting to write to
			the queue, then one should be unblocked as after this function exits
			it will be possible to write to it. */
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 80042fc:	68fb      	ldr	r3, [r7, #12]
 80042fe:	691b      	ldr	r3, [r3, #16]
 8004300:	2b00      	cmp	r3, #0
 8004302:	d01a      	beq.n	800433a <xQueueGenericReset+0xbe>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8004304:	68fb      	ldr	r3, [r7, #12]
 8004306:	3310      	adds	r3, #16
 8004308:	4618      	mov	r0, r3
 800430a:	f001 f931 	bl	8005570 <xTaskRemoveFromEventList>
 800430e:	4603      	mov	r3, r0
 8004310:	2b00      	cmp	r3, #0
 8004312:	d012      	beq.n	800433a <xQueueGenericReset+0xbe>
				{
					queueYIELD_IF_USING_PREEMPTION();
 8004314:	4b0c      	ldr	r3, [pc, #48]	; (8004348 <xQueueGenericReset+0xcc>)
 8004316:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 800431a:	601a      	str	r2, [r3, #0]
 800431c:	f3bf 8f4f 	dsb	sy
 8004320:	f3bf 8f6f 	isb	sy
 8004324:	e009      	b.n	800433a <xQueueGenericReset+0xbe>
			}
		}
		else
		{
			/* Ensure the event queues start in the correct state. */
			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
 8004326:	68fb      	ldr	r3, [r7, #12]
 8004328:	3310      	adds	r3, #16
 800432a:	4618      	mov	r0, r3
 800432c:	f7ff fef2 	bl	8004114 <vListInitialise>
			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
 8004330:	68fb      	ldr	r3, [r7, #12]
 8004332:	3324      	adds	r3, #36	; 0x24
 8004334:	4618      	mov	r0, r3
 8004336:	f7ff feed 	bl	8004114 <vListInitialise>
		}
	}
	taskEXIT_CRITICAL();
 800433a:	f002 f86b 	bl	8006414 <vPortExitCritical>

	/* A value is returned for calling semantic consistency with previous
	versions. */
	return pdPASS;
 800433e:	2301      	movs	r3, #1
}
 8004340:	4618      	mov	r0, r3
 8004342:	3710      	adds	r7, #16
 8004344:	46bd      	mov	sp, r7
 8004346:	bd80      	pop	{r7, pc}
 8004348:	e000ed04 	.word	0xe000ed04

0800434c <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/

#if( configSUPPORT_STATIC_ALLOCATION == 1 )

	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
	{
 800434c:	b580      	push	{r7, lr}
 800434e:	b08e      	sub	sp, #56	; 0x38
 8004350:	af02      	add	r7, sp, #8
 8004352:	60f8      	str	r0, [r7, #12]
 8004354:	60b9      	str	r1, [r7, #8]
 8004356:	607a      	str	r2, [r7, #4]
 8004358:	603b      	str	r3, [r7, #0]
	Queue_t *pxNewQueue;

		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
 800435a:	68fb      	ldr	r3, [r7, #12]
 800435c:	2b00      	cmp	r3, #0
 800435e:	d10a      	bne.n	8004376 <xQueueGenericCreateStatic+0x2a>
	__asm volatile
 8004360:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004364:	f383 8811 	msr	BASEPRI, r3
 8004368:	f3bf 8f6f 	isb	sy
 800436c:	f3bf 8f4f 	dsb	sy
 8004370:	62bb      	str	r3, [r7, #40]	; 0x28
}
 8004372:	bf00      	nop
 8004374:	e7fe      	b.n	8004374 <xQueueGenericCreateStatic+0x28>

		/* The StaticQueue_t structure and the queue storage area must be
		supplied. */
		configASSERT( pxStaticQueue != NULL );
 8004376:	683b      	ldr	r3, [r7, #0]
 8004378:	2b00      	cmp	r3, #0
 800437a:	d10a      	bne.n	8004392 <xQueueGenericCreateStatic+0x46>
	__asm volatile
 800437c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004380:	f383 8811 	msr	BASEPRI, r3
 8004384:	f3bf 8f6f 	isb	sy
 8004388:	f3bf 8f4f 	dsb	sy
 800438c:	627b      	str	r3, [r7, #36]	; 0x24
}
 800438e:	bf00      	nop
 8004390:	e7fe      	b.n	8004390 <xQueueGenericCreateStatic+0x44>

		/* A queue storage area should be provided if the item size is not 0, and
		should not be provided if the item size is 0. */
		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
 8004392:	687b      	ldr	r3, [r7, #4]
 8004394:	2b00      	cmp	r3, #0
 8004396:	d002      	beq.n	800439e <xQueueGenericCreateStatic+0x52>
 8004398:	68bb      	ldr	r3, [r7, #8]
 800439a:	2b00      	cmp	r3, #0
 800439c:	d001      	beq.n	80043a2 <xQueueGenericCreateStatic+0x56>
 800439e:	2301      	movs	r3, #1
 80043a0:	e000      	b.n	80043a4 <xQueueGenericCreateStatic+0x58>
 80043a2:	2300      	movs	r3, #0
 80043a4:	2b00      	cmp	r3, #0
 80043a6:	d10a      	bne.n	80043be <xQueueGenericCreateStatic+0x72>
	__asm volatile
 80043a8:	f04f 0350 	mov.w	r3, #80	; 0x50
 80043ac:	f383 8811 	msr	BASEPRI, r3
 80043b0:	f3bf 8f6f 	isb	sy
 80043b4:	f3bf 8f4f 	dsb	sy
 80043b8:	623b      	str	r3, [r7, #32]
}
 80043ba:	bf00      	nop
 80043bc:	e7fe      	b.n	80043bc <xQueueGenericCreateStatic+0x70>
		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
 80043be:	687b      	ldr	r3, [r7, #4]
 80043c0:	2b00      	cmp	r3, #0
 80043c2:	d102      	bne.n	80043ca <xQueueGenericCreateStatic+0x7e>
 80043c4:	68bb      	ldr	r3, [r7, #8]
 80043c6:	2b00      	cmp	r3, #0
 80043c8:	d101      	bne.n	80043ce <xQueueGenericCreateStatic+0x82>
 80043ca:	2301      	movs	r3, #1
 80043cc:	e000      	b.n	80043d0 <xQueueGenericCreateStatic+0x84>
 80043ce:	2300      	movs	r3, #0
 80043d0:	2b00      	cmp	r3, #0
 80043d2:	d10a      	bne.n	80043ea <xQueueGenericCreateStatic+0x9e>
	__asm volatile
 80043d4:	f04f 0350 	mov.w	r3, #80	; 0x50
 80043d8:	f383 8811 	msr	BASEPRI, r3
 80043dc:	f3bf 8f6f 	isb	sy
 80043e0:	f3bf 8f4f 	dsb	sy
 80043e4:	61fb      	str	r3, [r7, #28]
}
 80043e6:	bf00      	nop
 80043e8:	e7fe      	b.n	80043e8 <xQueueGenericCreateStatic+0x9c>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
			the real queue and semaphore structures. */
			volatile size_t xSize = sizeof( StaticQueue_t );
 80043ea:	2350      	movs	r3, #80	; 0x50
 80043ec:	617b      	str	r3, [r7, #20]
			configASSERT( xSize == sizeof( Queue_t ) );
 80043ee:	697b      	ldr	r3, [r7, #20]
 80043f0:	2b50      	cmp	r3, #80	; 0x50
 80043f2:	d00a      	beq.n	800440a <xQueueGenericCreateStatic+0xbe>
	__asm volatile
 80043f4:	f04f 0350 	mov.w	r3, #80	; 0x50
 80043f8:	f383 8811 	msr	BASEPRI, r3
 80043fc:	f3bf 8f6f 	isb	sy
 8004400:	f3bf 8f4f 	dsb	sy
 8004404:	61bb      	str	r3, [r7, #24]
}
 8004406:	bf00      	nop
 8004408:	e7fe      	b.n	8004408 <xQueueGenericCreateStatic+0xbc>
			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 800440a:	697b      	ldr	r3, [r7, #20]
		#endif /* configASSERT_DEFINED */

		/* The address of a statically allocated queue was passed in, use it.
		The address of a statically allocated storage area was also passed in
		but is already set. */
		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 800440c:	683b      	ldr	r3, [r7, #0]
 800440e:	62fb      	str	r3, [r7, #44]	; 0x2c

		if( pxNewQueue != NULL )
 8004410:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8004412:	2b00      	cmp	r3, #0
 8004414:	d00d      	beq.n	8004432 <xQueueGenericCreateStatic+0xe6>
			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
			{
				/* Queues can be allocated wither statically or dynamically, so
				note this queue was allocated statically in case the queue is
				later deleted. */
				pxNewQueue->ucStaticallyAllocated = pdTRUE;
 8004416:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8004418:	2201      	movs	r2, #1
 800441a:	f883 2046 	strb.w	r2, [r3, #70]	; 0x46
			}
			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */

			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 800441e:	f897 2038 	ldrb.w	r2, [r7, #56]	; 0x38
 8004422:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8004424:	9300      	str	r3, [sp, #0]
 8004426:	4613      	mov	r3, r2
 8004428:	687a      	ldr	r2, [r7, #4]
 800442a:	68b9      	ldr	r1, [r7, #8]
 800442c:	68f8      	ldr	r0, [r7, #12]
 800442e:	f000 f805 	bl	800443c <prvInitialiseNewQueue>
		{
			traceQUEUE_CREATE_FAILED( ucQueueType );
			mtCOVERAGE_TEST_MARKER();
		}

		return pxNewQueue;
 8004432:	6afb      	ldr	r3, [r7, #44]	; 0x2c
	}
 8004434:	4618      	mov	r0, r3
 8004436:	3730      	adds	r7, #48	; 0x30
 8004438:	46bd      	mov	sp, r7
 800443a:	bd80      	pop	{r7, pc}

0800443c <prvInitialiseNewQueue>:

#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
 800443c:	b580      	push	{r7, lr}
 800443e:	b084      	sub	sp, #16
 8004440:	af00      	add	r7, sp, #0
 8004442:	60f8      	str	r0, [r7, #12]
 8004444:	60b9      	str	r1, [r7, #8]
 8004446:	607a      	str	r2, [r7, #4]
 8004448:	70fb      	strb	r3, [r7, #3]
	/* Remove compiler warnings about unused parameters should
	configUSE_TRACE_FACILITY not be set to 1. */
	( void ) ucQueueType;

	if( uxItemSize == ( UBaseType_t ) 0 )
 800444a:	68bb      	ldr	r3, [r7, #8]
 800444c:	2b00      	cmp	r3, #0
 800444e:	d103      	bne.n	8004458 <prvInitialiseNewQueue+0x1c>
	{
		/* No RAM was allocated for the queue storage area, but PC head cannot
		be set to NULL because NULL is used as a key to say the queue is used as
		a mutex.  Therefore just set pcHead to point to the queue as a benign
		value that is known to be within the memory map. */
		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
 8004450:	69bb      	ldr	r3, [r7, #24]
 8004452:	69ba      	ldr	r2, [r7, #24]
 8004454:	601a      	str	r2, [r3, #0]
 8004456:	e002      	b.n	800445e <prvInitialiseNewQueue+0x22>
	}
	else
	{
		/* Set the head to the start of the queue storage area. */
		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
 8004458:	69bb      	ldr	r3, [r7, #24]
 800445a:	687a      	ldr	r2, [r7, #4]
 800445c:	601a      	str	r2, [r3, #0]
	}

	/* Initialise the queue members as described where the queue type is
	defined. */
	pxNewQueue->uxLength = uxQueueLength;
 800445e:	69bb      	ldr	r3, [r7, #24]
 8004460:	68fa      	ldr	r2, [r7, #12]
 8004462:	63da      	str	r2, [r3, #60]	; 0x3c
	pxNewQueue->uxItemSize = uxItemSize;
 8004464:	69bb      	ldr	r3, [r7, #24]
 8004466:	68ba      	ldr	r2, [r7, #8]
 8004468:	641a      	str	r2, [r3, #64]	; 0x40
	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
 800446a:	2101      	movs	r1, #1
 800446c:	69b8      	ldr	r0, [r7, #24]
 800446e:	f7ff ff05 	bl	800427c <xQueueGenericReset>

	#if ( configUSE_TRACE_FACILITY == 1 )
	{
		pxNewQueue->ucQueueType = ucQueueType;
 8004472:	69bb      	ldr	r3, [r7, #24]
 8004474:	78fa      	ldrb	r2, [r7, #3]
 8004476:	f883 204c 	strb.w	r2, [r3, #76]	; 0x4c
		pxNewQueue->pxQueueSetContainer = NULL;
	}
	#endif /* configUSE_QUEUE_SETS */

	traceQUEUE_CREATE( pxNewQueue );
}
 800447a:	bf00      	nop
 800447c:	3710      	adds	r7, #16
 800447e:	46bd      	mov	sp, r7
 8004480:	bd80      	pop	{r7, pc}
	...

08004484 <xQueueGenericSend>:

#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
 8004484:	b580      	push	{r7, lr}
 8004486:	b08e      	sub	sp, #56	; 0x38
 8004488:	af00      	add	r7, sp, #0
 800448a:	60f8      	str	r0, [r7, #12]
 800448c:	60b9      	str	r1, [r7, #8]
 800448e:	607a      	str	r2, [r7, #4]
 8004490:	603b      	str	r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
 8004492:	2300      	movs	r3, #0
 8004494:	637b      	str	r3, [r7, #52]	; 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 8004496:	68fb      	ldr	r3, [r7, #12]
 8004498:	633b      	str	r3, [r7, #48]	; 0x30

	configASSERT( pxQueue );
 800449a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 800449c:	2b00      	cmp	r3, #0
 800449e:	d10a      	bne.n	80044b6 <xQueueGenericSend+0x32>
	__asm volatile
 80044a0:	f04f 0350 	mov.w	r3, #80	; 0x50
 80044a4:	f383 8811 	msr	BASEPRI, r3
 80044a8:	f3bf 8f6f 	isb	sy
 80044ac:	f3bf 8f4f 	dsb	sy
 80044b0:	62bb      	str	r3, [r7, #40]	; 0x28
}
 80044b2:	bf00      	nop
 80044b4:	e7fe      	b.n	80044b4 <xQueueGenericSend+0x30>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80044b6:	68bb      	ldr	r3, [r7, #8]
 80044b8:	2b00      	cmp	r3, #0
 80044ba:	d103      	bne.n	80044c4 <xQueueGenericSend+0x40>
 80044bc:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 80044be:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80044c0:	2b00      	cmp	r3, #0
 80044c2:	d101      	bne.n	80044c8 <xQueueGenericSend+0x44>
 80044c4:	2301      	movs	r3, #1
 80044c6:	e000      	b.n	80044ca <xQueueGenericSend+0x46>
 80044c8:	2300      	movs	r3, #0
 80044ca:	2b00      	cmp	r3, #0
 80044cc:	d10a      	bne.n	80044e4 <xQueueGenericSend+0x60>
	__asm volatile
 80044ce:	f04f 0350 	mov.w	r3, #80	; 0x50
 80044d2:	f383 8811 	msr	BASEPRI, r3
 80044d6:	f3bf 8f6f 	isb	sy
 80044da:	f3bf 8f4f 	dsb	sy
 80044de:	627b      	str	r3, [r7, #36]	; 0x24
}
 80044e0:	bf00      	nop
 80044e2:	e7fe      	b.n	80044e2 <xQueueGenericSend+0x5e>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 80044e4:	683b      	ldr	r3, [r7, #0]
 80044e6:	2b02      	cmp	r3, #2
 80044e8:	d103      	bne.n	80044f2 <xQueueGenericSend+0x6e>
 80044ea:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 80044ec:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80044ee:	2b01      	cmp	r3, #1
 80044f0:	d101      	bne.n	80044f6 <xQueueGenericSend+0x72>
 80044f2:	2301      	movs	r3, #1
 80044f4:	e000      	b.n	80044f8 <xQueueGenericSend+0x74>
 80044f6:	2300      	movs	r3, #0
 80044f8:	2b00      	cmp	r3, #0
 80044fa:	d10a      	bne.n	8004512 <xQueueGenericSend+0x8e>
	__asm volatile
 80044fc:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004500:	f383 8811 	msr	BASEPRI, r3
 8004504:	f3bf 8f6f 	isb	sy
 8004508:	f3bf 8f4f 	dsb	sy
 800450c:	623b      	str	r3, [r7, #32]
}
 800450e:	bf00      	nop
 8004510:	e7fe      	b.n	8004510 <xQueueGenericSend+0x8c>
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8004512:	f001 f9f1 	bl	80058f8 <xTaskGetSchedulerState>
 8004516:	4603      	mov	r3, r0
 8004518:	2b00      	cmp	r3, #0
 800451a:	d102      	bne.n	8004522 <xQueueGenericSend+0x9e>
 800451c:	687b      	ldr	r3, [r7, #4]
 800451e:	2b00      	cmp	r3, #0
 8004520:	d101      	bne.n	8004526 <xQueueGenericSend+0xa2>
 8004522:	2301      	movs	r3, #1
 8004524:	e000      	b.n	8004528 <xQueueGenericSend+0xa4>
 8004526:	2300      	movs	r3, #0
 8004528:	2b00      	cmp	r3, #0
 800452a:	d10a      	bne.n	8004542 <xQueueGenericSend+0xbe>
	__asm volatile
 800452c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004530:	f383 8811 	msr	BASEPRI, r3
 8004534:	f3bf 8f6f 	isb	sy
 8004538:	f3bf 8f4f 	dsb	sy
 800453c:	61fb      	str	r3, [r7, #28]
}
 800453e:	bf00      	nop
 8004540:	e7fe      	b.n	8004540 <xQueueGenericSend+0xbc>
	/*lint -save -e904 This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 8004542:	f001 ff37 	bl	80063b4 <vPortEnterCritical>
		{
			/* Is there room on the queue now?  The running task must be the
			highest priority task wanting to access the queue.  If the head item
			in the queue is to be overwritten then it does not matter if the
			queue is full. */
			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 8004546:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004548:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 800454a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 800454c:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 800454e:	429a      	cmp	r2, r3
 8004550:	d302      	bcc.n	8004558 <xQueueGenericSend+0xd4>
 8004552:	683b      	ldr	r3, [r7, #0]
 8004554:	2b02      	cmp	r3, #2
 8004556:	d129      	bne.n	80045ac <xQueueGenericSend+0x128>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 8004558:	683a      	ldr	r2, [r7, #0]
 800455a:	68b9      	ldr	r1, [r7, #8]
 800455c:	6b38      	ldr	r0, [r7, #48]	; 0x30
 800455e:	f000 fa0b 	bl	8004978 <prvCopyDataToQueue>
 8004562:	62f8      	str	r0, [r7, #44]	; 0x2c

					/* If there was a task waiting for data to arrive on the
					queue then unblock it now. */
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8004564:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004566:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004568:	2b00      	cmp	r3, #0
 800456a:	d010      	beq.n	800458e <xQueueGenericSend+0x10a>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 800456c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 800456e:	3324      	adds	r3, #36	; 0x24
 8004570:	4618      	mov	r0, r3
 8004572:	f000 fffd 	bl	8005570 <xTaskRemoveFromEventList>
 8004576:	4603      	mov	r3, r0
 8004578:	2b00      	cmp	r3, #0
 800457a:	d013      	beq.n	80045a4 <xQueueGenericSend+0x120>
						{
							/* The unblocked task has a priority higher than
							our own so yield immediately.  Yes it is ok to do
							this from within the critical section - the kernel
							takes care of that. */
							queueYIELD_IF_USING_PREEMPTION();
 800457c:	4b3f      	ldr	r3, [pc, #252]	; (800467c <xQueueGenericSend+0x1f8>)
 800457e:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8004582:	601a      	str	r2, [r3, #0]
 8004584:	f3bf 8f4f 	dsb	sy
 8004588:	f3bf 8f6f 	isb	sy
 800458c:	e00a      	b.n	80045a4 <xQueueGenericSend+0x120>
						else
						{
							mtCOVERAGE_TEST_MARKER();
						}
					}
					else if( xYieldRequired != pdFALSE )
 800458e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8004590:	2b00      	cmp	r3, #0
 8004592:	d007      	beq.n	80045a4 <xQueueGenericSend+0x120>
					{
						/* This path is a special case that will only get
						executed if the task was holding multiple mutexes and
						the mutexes were given back in an order that is
						different to that in which they were taken. */
						queueYIELD_IF_USING_PREEMPTION();
 8004594:	4b39      	ldr	r3, [pc, #228]	; (800467c <xQueueGenericSend+0x1f8>)
 8004596:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 800459a:	601a      	str	r2, [r3, #0]
 800459c:	f3bf 8f4f 	dsb	sy
 80045a0:	f3bf 8f6f 	isb	sy
						mtCOVERAGE_TEST_MARKER();
					}
				}
				#endif /* configUSE_QUEUE_SETS */

				taskEXIT_CRITICAL();
 80045a4:	f001 ff36 	bl	8006414 <vPortExitCritical>
				return pdPASS;
 80045a8:	2301      	movs	r3, #1
 80045aa:	e063      	b.n	8004674 <xQueueGenericSend+0x1f0>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 80045ac:	687b      	ldr	r3, [r7, #4]
 80045ae:	2b00      	cmp	r3, #0
 80045b0:	d103      	bne.n	80045ba <xQueueGenericSend+0x136>
				{
					/* The queue was full and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 80045b2:	f001 ff2f 	bl	8006414 <vPortExitCritical>

					/* Return to the original privilege level before exiting
					the function. */
					traceQUEUE_SEND_FAILED( pxQueue );
					return errQUEUE_FULL;
 80045b6:	2300      	movs	r3, #0
 80045b8:	e05c      	b.n	8004674 <xQueueGenericSend+0x1f0>
				}
				else if( xEntryTimeSet == pdFALSE )
 80045ba:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 80045bc:	2b00      	cmp	r3, #0
 80045be:	d106      	bne.n	80045ce <xQueueGenericSend+0x14a>
				{
					/* The queue was full and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 80045c0:	f107 0314 	add.w	r3, r7, #20
 80045c4:	4618      	mov	r0, r3
 80045c6:	f001 f837 	bl	8005638 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 80045ca:	2301      	movs	r3, #1
 80045cc:	637b      	str	r3, [r7, #52]	; 0x34
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 80045ce:	f001 ff21 	bl	8006414 <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 80045d2:	f000 fd9b 	bl	800510c <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 80045d6:	f001 feed 	bl	80063b4 <vPortEnterCritical>
 80045da:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 80045dc:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
 80045e0:	b25b      	sxtb	r3, r3
 80045e2:	f1b3 3fff 	cmp.w	r3, #4294967295
 80045e6:	d103      	bne.n	80045f0 <xQueueGenericSend+0x16c>
 80045e8:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 80045ea:	2200      	movs	r2, #0
 80045ec:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
 80045f0:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 80045f2:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
 80045f6:	b25b      	sxtb	r3, r3
 80045f8:	f1b3 3fff 	cmp.w	r3, #4294967295
 80045fc:	d103      	bne.n	8004606 <xQueueGenericSend+0x182>
 80045fe:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004600:	2200      	movs	r2, #0
 8004602:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
 8004606:	f001 ff05 	bl	8006414 <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 800460a:	1d3a      	adds	r2, r7, #4
 800460c:	f107 0314 	add.w	r3, r7, #20
 8004610:	4611      	mov	r1, r2
 8004612:	4618      	mov	r0, r3
 8004614:	f001 f826 	bl	8005664 <xTaskCheckForTimeOut>
 8004618:	4603      	mov	r3, r0
 800461a:	2b00      	cmp	r3, #0
 800461c:	d124      	bne.n	8004668 <xQueueGenericSend+0x1e4>
		{
			if( prvIsQueueFull( pxQueue ) != pdFALSE )
 800461e:	6b38      	ldr	r0, [r7, #48]	; 0x30
 8004620:	f000 faa2 	bl	8004b68 <prvIsQueueFull>
 8004624:	4603      	mov	r3, r0
 8004626:	2b00      	cmp	r3, #0
 8004628:	d018      	beq.n	800465c <xQueueGenericSend+0x1d8>
			{
				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
 800462a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 800462c:	3310      	adds	r3, #16
 800462e:	687a      	ldr	r2, [r7, #4]
 8004630:	4611      	mov	r1, r2
 8004632:	4618      	mov	r0, r3
 8004634:	f000 ff4c 	bl	80054d0 <vTaskPlaceOnEventList>
				/* Unlocking the queue means queue events can effect the
				event list.  It is possible that interrupts occurring now
				remove this task from the event list again - but as the
				scheduler is suspended the task will go onto the pending
				ready last instead of the actual ready list. */
				prvUnlockQueue( pxQueue );
 8004638:	6b38      	ldr	r0, [r7, #48]	; 0x30
 800463a:	f000 fa2d 	bl	8004a98 <prvUnlockQueue>
				/* Resuming the scheduler will move tasks from the pending
				ready list into the ready list - so it is feasible that this
				task is already in a ready list before it yields - in which
				case the yield will not cause a context switch unless there
				is also a higher priority task in the pending ready list. */
				if( xTaskResumeAll() == pdFALSE )
 800463e:	f000 fd73 	bl	8005128 <xTaskResumeAll>
 8004642:	4603      	mov	r3, r0
 8004644:	2b00      	cmp	r3, #0
 8004646:	f47f af7c 	bne.w	8004542 <xQueueGenericSend+0xbe>
				{
					portYIELD_WITHIN_API();
 800464a:	4b0c      	ldr	r3, [pc, #48]	; (800467c <xQueueGenericSend+0x1f8>)
 800464c:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8004650:	601a      	str	r2, [r3, #0]
 8004652:	f3bf 8f4f 	dsb	sy
 8004656:	f3bf 8f6f 	isb	sy
 800465a:	e772      	b.n	8004542 <xQueueGenericSend+0xbe>
				}
			}
			else
			{
				/* Try again. */
				prvUnlockQueue( pxQueue );
 800465c:	6b38      	ldr	r0, [r7, #48]	; 0x30
 800465e:	f000 fa1b 	bl	8004a98 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 8004662:	f000 fd61 	bl	8005128 <xTaskResumeAll>
 8004666:	e76c      	b.n	8004542 <xQueueGenericSend+0xbe>
			}
		}
		else
		{
			/* The timeout has expired. */
			prvUnlockQueue( pxQueue );
 8004668:	6b38      	ldr	r0, [r7, #48]	; 0x30
 800466a:	f000 fa15 	bl	8004a98 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 800466e:	f000 fd5b 	bl	8005128 <xTaskResumeAll>

			traceQUEUE_SEND_FAILED( pxQueue );
			return errQUEUE_FULL;
 8004672:	2300      	movs	r3, #0
		}
	} /*lint -restore */
}
 8004674:	4618      	mov	r0, r3
 8004676:	3738      	adds	r7, #56	; 0x38
 8004678:	46bd      	mov	sp, r7
 800467a:	bd80      	pop	{r7, pc}
 800467c:	e000ed04 	.word	0xe000ed04

08004680 <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
 8004680:	b580      	push	{r7, lr}
 8004682:	b090      	sub	sp, #64	; 0x40
 8004684:	af00      	add	r7, sp, #0
 8004686:	60f8      	str	r0, [r7, #12]
 8004688:	60b9      	str	r1, [r7, #8]
 800468a:	607a      	str	r2, [r7, #4]
 800468c:	603b      	str	r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
 800468e:	68fb      	ldr	r3, [r7, #12]
 8004690:	63bb      	str	r3, [r7, #56]	; 0x38

	configASSERT( pxQueue );
 8004692:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8004694:	2b00      	cmp	r3, #0
 8004696:	d10a      	bne.n	80046ae <xQueueGenericSendFromISR+0x2e>
	__asm volatile
 8004698:	f04f 0350 	mov.w	r3, #80	; 0x50
 800469c:	f383 8811 	msr	BASEPRI, r3
 80046a0:	f3bf 8f6f 	isb	sy
 80046a4:	f3bf 8f4f 	dsb	sy
 80046a8:	62bb      	str	r3, [r7, #40]	; 0x28
}
 80046aa:	bf00      	nop
 80046ac:	e7fe      	b.n	80046ac <xQueueGenericSendFromISR+0x2c>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80046ae:	68bb      	ldr	r3, [r7, #8]
 80046b0:	2b00      	cmp	r3, #0
 80046b2:	d103      	bne.n	80046bc <xQueueGenericSendFromISR+0x3c>
 80046b4:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 80046b6:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80046b8:	2b00      	cmp	r3, #0
 80046ba:	d101      	bne.n	80046c0 <xQueueGenericSendFromISR+0x40>
 80046bc:	2301      	movs	r3, #1
 80046be:	e000      	b.n	80046c2 <xQueueGenericSendFromISR+0x42>
 80046c0:	2300      	movs	r3, #0
 80046c2:	2b00      	cmp	r3, #0
 80046c4:	d10a      	bne.n	80046dc <xQueueGenericSendFromISR+0x5c>
	__asm volatile
 80046c6:	f04f 0350 	mov.w	r3, #80	; 0x50
 80046ca:	f383 8811 	msr	BASEPRI, r3
 80046ce:	f3bf 8f6f 	isb	sy
 80046d2:	f3bf 8f4f 	dsb	sy
 80046d6:	627b      	str	r3, [r7, #36]	; 0x24
}
 80046d8:	bf00      	nop
 80046da:	e7fe      	b.n	80046da <xQueueGenericSendFromISR+0x5a>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 80046dc:	683b      	ldr	r3, [r7, #0]
 80046de:	2b02      	cmp	r3, #2
 80046e0:	d103      	bne.n	80046ea <xQueueGenericSendFromISR+0x6a>
 80046e2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 80046e4:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80046e6:	2b01      	cmp	r3, #1
 80046e8:	d101      	bne.n	80046ee <xQueueGenericSendFromISR+0x6e>
 80046ea:	2301      	movs	r3, #1
 80046ec:	e000      	b.n	80046f0 <xQueueGenericSendFromISR+0x70>
 80046ee:	2300      	movs	r3, #0
 80046f0:	2b00      	cmp	r3, #0
 80046f2:	d10a      	bne.n	800470a <xQueueGenericSendFromISR+0x8a>
	__asm volatile
 80046f4:	f04f 0350 	mov.w	r3, #80	; 0x50
 80046f8:	f383 8811 	msr	BASEPRI, r3
 80046fc:	f3bf 8f6f 	isb	sy
 8004700:	f3bf 8f4f 	dsb	sy
 8004704:	623b      	str	r3, [r7, #32]
}
 8004706:	bf00      	nop
 8004708:	e7fe      	b.n	8004708 <xQueueGenericSendFromISR+0x88>
	that have been assigned a priority at or (logically) below the maximum
	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
	safe API to ensure interrupt entry is as fast and as simple as possible.
	More information (albeit Cortex-M specific) is provided on the following
	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 800470a:	f001 ff35 	bl	8006578 <vPortValidateInterruptPriority>

portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;

	__asm volatile
 800470e:	f3ef 8211 	mrs	r2, BASEPRI
 8004712:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004716:	f383 8811 	msr	BASEPRI, r3
 800471a:	f3bf 8f6f 	isb	sy
 800471e:	f3bf 8f4f 	dsb	sy
 8004722:	61fa      	str	r2, [r7, #28]
 8004724:	61bb      	str	r3, [r7, #24]
		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);

	/* This return will not be reached but is necessary to prevent compiler
	warnings. */
	return ulOriginalBASEPRI;
 8004726:	69fb      	ldr	r3, [r7, #28]
	/* Similar to xQueueGenericSend, except without blocking if there is no room
	in the queue.  Also don't directly wake a task that was blocked on a queue
	read, instead return a flag to say whether a context switch is required or
	not (i.e. has a task with a higher priority than us been woken by this
	post). */
	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 8004728:	637b      	str	r3, [r7, #52]	; 0x34
	{
		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 800472a:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 800472c:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 800472e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8004730:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8004732:	429a      	cmp	r2, r3
 8004734:	d302      	bcc.n	800473c <xQueueGenericSendFromISR+0xbc>
 8004736:	683b      	ldr	r3, [r7, #0]
 8004738:	2b02      	cmp	r3, #2
 800473a:	d12f      	bne.n	800479c <xQueueGenericSendFromISR+0x11c>
		{
			const int8_t cTxLock = pxQueue->cTxLock;
 800473c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 800473e:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
 8004742:	f887 3033 	strb.w	r3, [r7, #51]	; 0x33
			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
 8004746:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8004748:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 800474a:	62fb      	str	r3, [r7, #44]	; 0x2c
			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
			in a task disinheriting a priority and prvCopyDataToQueue() can be
			called here even though the disinherit function does not check if
			the scheduler is suspended before accessing the ready lists. */
			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 800474c:	683a      	ldr	r2, [r7, #0]
 800474e:	68b9      	ldr	r1, [r7, #8]
 8004750:	6bb8      	ldr	r0, [r7, #56]	; 0x38
 8004752:	f000 f911 	bl	8004978 <prvCopyDataToQueue>

			/* The event list is not altered if the queue is locked.  This will
			be done when the queue is unlocked later. */
			if( cTxLock == queueUNLOCKED )
 8004756:	f997 3033 	ldrsb.w	r3, [r7, #51]	; 0x33
 800475a:	f1b3 3fff 	cmp.w	r3, #4294967295
 800475e:	d112      	bne.n	8004786 <xQueueGenericSendFromISR+0x106>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8004760:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8004762:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004764:	2b00      	cmp	r3, #0
 8004766:	d016      	beq.n	8004796 <xQueueGenericSendFromISR+0x116>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8004768:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 800476a:	3324      	adds	r3, #36	; 0x24
 800476c:	4618      	mov	r0, r3
 800476e:	f000 feff 	bl	8005570 <xTaskRemoveFromEventList>
 8004772:	4603      	mov	r3, r0
 8004774:	2b00      	cmp	r3, #0
 8004776:	d00e      	beq.n	8004796 <xQueueGenericSendFromISR+0x116>
						{
							/* The task waiting has a higher priority so record that a
							context	switch is required. */
							if( pxHigherPriorityTaskWoken != NULL )
 8004778:	687b      	ldr	r3, [r7, #4]
 800477a:	2b00      	cmp	r3, #0
 800477c:	d00b      	beq.n	8004796 <xQueueGenericSendFromISR+0x116>
							{
								*pxHigherPriorityTaskWoken = pdTRUE;
 800477e:	687b      	ldr	r3, [r7, #4]
 8004780:	2201      	movs	r2, #1
 8004782:	601a      	str	r2, [r3, #0]
 8004784:	e007      	b.n	8004796 <xQueueGenericSendFromISR+0x116>
			}
			else
			{
				/* Increment the lock count so the task that unlocks the queue
				knows that data was posted while it was locked. */
				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
 8004786:	f897 3033 	ldrb.w	r3, [r7, #51]	; 0x33
 800478a:	3301      	adds	r3, #1
 800478c:	b2db      	uxtb	r3, r3
 800478e:	b25a      	sxtb	r2, r3
 8004790:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8004792:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
			}

			xReturn = pdPASS;
 8004796:	2301      	movs	r3, #1
 8004798:	63fb      	str	r3, [r7, #60]	; 0x3c
		{
 800479a:	e001      	b.n	80047a0 <xQueueGenericSendFromISR+0x120>
		}
		else
		{
			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
			xReturn = errQUEUE_FULL;
 800479c:	2300      	movs	r3, #0
 800479e:	63fb      	str	r3, [r7, #60]	; 0x3c
 80047a0:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 80047a2:	617b      	str	r3, [r7, #20]
}
/*-----------------------------------------------------------*/

portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
	__asm volatile
 80047a4:	697b      	ldr	r3, [r7, #20]
 80047a6:	f383 8811 	msr	BASEPRI, r3
	(
		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
	);
}
 80047aa:	bf00      	nop
		}
	}
	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

	return xReturn;
 80047ac:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
}
 80047ae:	4618      	mov	r0, r3
 80047b0:	3740      	adds	r7, #64	; 0x40
 80047b2:	46bd      	mov	sp, r7
 80047b4:	bd80      	pop	{r7, pc}
	...

080047b8 <xQueueReceive>:
	return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
 80047b8:	b580      	push	{r7, lr}
 80047ba:	b08c      	sub	sp, #48	; 0x30
 80047bc:	af00      	add	r7, sp, #0
 80047be:	60f8      	str	r0, [r7, #12]
 80047c0:	60b9      	str	r1, [r7, #8]
 80047c2:	607a      	str	r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
 80047c4:	2300      	movs	r3, #0
 80047c6:	62fb      	str	r3, [r7, #44]	; 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 80047c8:	68fb      	ldr	r3, [r7, #12]
 80047ca:	62bb      	str	r3, [r7, #40]	; 0x28

	/* Check the pointer is not NULL. */
	configASSERT( ( pxQueue ) );
 80047cc:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80047ce:	2b00      	cmp	r3, #0
 80047d0:	d10a      	bne.n	80047e8 <xQueueReceive+0x30>
	__asm volatile
 80047d2:	f04f 0350 	mov.w	r3, #80	; 0x50
 80047d6:	f383 8811 	msr	BASEPRI, r3
 80047da:	f3bf 8f6f 	isb	sy
 80047de:	f3bf 8f4f 	dsb	sy
 80047e2:	623b      	str	r3, [r7, #32]
}
 80047e4:	bf00      	nop
 80047e6:	e7fe      	b.n	80047e6 <xQueueReceive+0x2e>

	/* The buffer into which data is received can only be NULL if the data size
	is zero (so no data is copied into the buffer. */
	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
 80047e8:	68bb      	ldr	r3, [r7, #8]
 80047ea:	2b00      	cmp	r3, #0
 80047ec:	d103      	bne.n	80047f6 <xQueueReceive+0x3e>
 80047ee:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80047f0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80047f2:	2b00      	cmp	r3, #0
 80047f4:	d101      	bne.n	80047fa <xQueueReceive+0x42>
 80047f6:	2301      	movs	r3, #1
 80047f8:	e000      	b.n	80047fc <xQueueReceive+0x44>
 80047fa:	2300      	movs	r3, #0
 80047fc:	2b00      	cmp	r3, #0
 80047fe:	d10a      	bne.n	8004816 <xQueueReceive+0x5e>
	__asm volatile
 8004800:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004804:	f383 8811 	msr	BASEPRI, r3
 8004808:	f3bf 8f6f 	isb	sy
 800480c:	f3bf 8f4f 	dsb	sy
 8004810:	61fb      	str	r3, [r7, #28]
}
 8004812:	bf00      	nop
 8004814:	e7fe      	b.n	8004814 <xQueueReceive+0x5c>

	/* Cannot block if the scheduler is suspended. */
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8004816:	f001 f86f 	bl	80058f8 <xTaskGetSchedulerState>
 800481a:	4603      	mov	r3, r0
 800481c:	2b00      	cmp	r3, #0
 800481e:	d102      	bne.n	8004826 <xQueueReceive+0x6e>
 8004820:	687b      	ldr	r3, [r7, #4]
 8004822:	2b00      	cmp	r3, #0
 8004824:	d101      	bne.n	800482a <xQueueReceive+0x72>
 8004826:	2301      	movs	r3, #1
 8004828:	e000      	b.n	800482c <xQueueReceive+0x74>
 800482a:	2300      	movs	r3, #0
 800482c:	2b00      	cmp	r3, #0
 800482e:	d10a      	bne.n	8004846 <xQueueReceive+0x8e>
	__asm volatile
 8004830:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004834:	f383 8811 	msr	BASEPRI, r3
 8004838:	f3bf 8f6f 	isb	sy
 800483c:	f3bf 8f4f 	dsb	sy
 8004840:	61bb      	str	r3, [r7, #24]
}
 8004842:	bf00      	nop
 8004844:	e7fe      	b.n	8004844 <xQueueReceive+0x8c>
	/*lint -save -e904  This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 8004846:	f001 fdb5 	bl	80063b4 <vPortEnterCritical>
		{
			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 800484a:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800484c:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 800484e:	627b      	str	r3, [r7, #36]	; 0x24

			/* Is there data in the queue now?  To be running the calling task
			must be the highest priority task wanting to access the queue. */
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8004850:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8004852:	2b00      	cmp	r3, #0
 8004854:	d01f      	beq.n	8004896 <xQueueReceive+0xde>
			{
				/* Data available, remove one item. */
				prvCopyDataFromQueue( pxQueue, pvBuffer );
 8004856:	68b9      	ldr	r1, [r7, #8]
 8004858:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 800485a:	f000 f8f7 	bl	8004a4c <prvCopyDataFromQueue>
				traceQUEUE_RECEIVE( pxQueue );
				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
 800485e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8004860:	1e5a      	subs	r2, r3, #1
 8004862:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8004864:	639a      	str	r2, [r3, #56]	; 0x38

				/* There is now space in the queue, were any tasks waiting to
				post to the queue?  If so, unblock the highest priority waiting
				task. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8004866:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8004868:	691b      	ldr	r3, [r3, #16]
 800486a:	2b00      	cmp	r3, #0
 800486c:	d00f      	beq.n	800488e <xQueueReceive+0xd6>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 800486e:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8004870:	3310      	adds	r3, #16
 8004872:	4618      	mov	r0, r3
 8004874:	f000 fe7c 	bl	8005570 <xTaskRemoveFromEventList>
 8004878:	4603      	mov	r3, r0
 800487a:	2b00      	cmp	r3, #0
 800487c:	d007      	beq.n	800488e <xQueueReceive+0xd6>
					{
						queueYIELD_IF_USING_PREEMPTION();
 800487e:	4b3d      	ldr	r3, [pc, #244]	; (8004974 <xQueueReceive+0x1bc>)
 8004880:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8004884:	601a      	str	r2, [r3, #0]
 8004886:	f3bf 8f4f 	dsb	sy
 800488a:	f3bf 8f6f 	isb	sy
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				taskEXIT_CRITICAL();
 800488e:	f001 fdc1 	bl	8006414 <vPortExitCritical>
				return pdPASS;
 8004892:	2301      	movs	r3, #1
 8004894:	e069      	b.n	800496a <xQueueReceive+0x1b2>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 8004896:	687b      	ldr	r3, [r7, #4]
 8004898:	2b00      	cmp	r3, #0
 800489a:	d103      	bne.n	80048a4 <xQueueReceive+0xec>
				{
					/* The queue was empty and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 800489c:	f001 fdba 	bl	8006414 <vPortExitCritical>
					traceQUEUE_RECEIVE_FAILED( pxQueue );
					return errQUEUE_EMPTY;
 80048a0:	2300      	movs	r3, #0
 80048a2:	e062      	b.n	800496a <xQueueReceive+0x1b2>
				}
				else if( xEntryTimeSet == pdFALSE )
 80048a4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 80048a6:	2b00      	cmp	r3, #0
 80048a8:	d106      	bne.n	80048b8 <xQueueReceive+0x100>
				{
					/* The queue was empty and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 80048aa:	f107 0310 	add.w	r3, r7, #16
 80048ae:	4618      	mov	r0, r3
 80048b0:	f000 fec2 	bl	8005638 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 80048b4:	2301      	movs	r3, #1
 80048b6:	62fb      	str	r3, [r7, #44]	; 0x2c
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 80048b8:	f001 fdac 	bl	8006414 <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 80048bc:	f000 fc26 	bl	800510c <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 80048c0:	f001 fd78 	bl	80063b4 <vPortEnterCritical>
 80048c4:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80048c6:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
 80048ca:	b25b      	sxtb	r3, r3
 80048cc:	f1b3 3fff 	cmp.w	r3, #4294967295
 80048d0:	d103      	bne.n	80048da <xQueueReceive+0x122>
 80048d2:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80048d4:	2200      	movs	r2, #0
 80048d6:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
 80048da:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80048dc:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
 80048e0:	b25b      	sxtb	r3, r3
 80048e2:	f1b3 3fff 	cmp.w	r3, #4294967295
 80048e6:	d103      	bne.n	80048f0 <xQueueReceive+0x138>
 80048e8:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80048ea:	2200      	movs	r2, #0
 80048ec:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
 80048f0:	f001 fd90 	bl	8006414 <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 80048f4:	1d3a      	adds	r2, r7, #4
 80048f6:	f107 0310 	add.w	r3, r7, #16
 80048fa:	4611      	mov	r1, r2
 80048fc:	4618      	mov	r0, r3
 80048fe:	f000 feb1 	bl	8005664 <xTaskCheckForTimeOut>
 8004902:	4603      	mov	r3, r0
 8004904:	2b00      	cmp	r3, #0
 8004906:	d123      	bne.n	8004950 <xQueueReceive+0x198>
		{
			/* The timeout has not expired.  If the queue is still empty place
			the task on the list of tasks waiting to receive from the queue. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8004908:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 800490a:	f000 f917 	bl	8004b3c <prvIsQueueEmpty>
 800490e:	4603      	mov	r3, r0
 8004910:	2b00      	cmp	r3, #0
 8004912:	d017      	beq.n	8004944 <xQueueReceive+0x18c>
			{
				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
 8004914:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8004916:	3324      	adds	r3, #36	; 0x24
 8004918:	687a      	ldr	r2, [r7, #4]
 800491a:	4611      	mov	r1, r2
 800491c:	4618      	mov	r0, r3
 800491e:	f000 fdd7 	bl	80054d0 <vTaskPlaceOnEventList>
				prvUnlockQueue( pxQueue );
 8004922:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8004924:	f000 f8b8 	bl	8004a98 <prvUnlockQueue>
				if( xTaskResumeAll() == pdFALSE )
 8004928:	f000 fbfe 	bl	8005128 <xTaskResumeAll>
 800492c:	4603      	mov	r3, r0
 800492e:	2b00      	cmp	r3, #0
 8004930:	d189      	bne.n	8004846 <xQueueReceive+0x8e>
				{
					portYIELD_WITHIN_API();
 8004932:	4b10      	ldr	r3, [pc, #64]	; (8004974 <xQueueReceive+0x1bc>)
 8004934:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8004938:	601a      	str	r2, [r3, #0]
 800493a:	f3bf 8f4f 	dsb	sy
 800493e:	f3bf 8f6f 	isb	sy
 8004942:	e780      	b.n	8004846 <xQueueReceive+0x8e>
			}
			else
			{
				/* The queue contains data again.  Loop back to try and read the
				data. */
				prvUnlockQueue( pxQueue );
 8004944:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8004946:	f000 f8a7 	bl	8004a98 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 800494a:	f000 fbed 	bl	8005128 <xTaskResumeAll>
 800494e:	e77a      	b.n	8004846 <xQueueReceive+0x8e>
		}
		else
		{
			/* Timed out.  If there is no data in the queue exit, otherwise loop
			back and attempt to read the data. */
			prvUnlockQueue( pxQueue );
 8004950:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8004952:	f000 f8a1 	bl	8004a98 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 8004956:	f000 fbe7 	bl	8005128 <xTaskResumeAll>

			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 800495a:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 800495c:	f000 f8ee 	bl	8004b3c <prvIsQueueEmpty>
 8004960:	4603      	mov	r3, r0
 8004962:	2b00      	cmp	r3, #0
 8004964:	f43f af6f 	beq.w	8004846 <xQueueReceive+0x8e>
			{
				traceQUEUE_RECEIVE_FAILED( pxQueue );
				return errQUEUE_EMPTY;
 8004968:	2300      	movs	r3, #0
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	} /*lint -restore */
}
 800496a:	4618      	mov	r0, r3
 800496c:	3730      	adds	r7, #48	; 0x30
 800496e:	46bd      	mov	sp, r7
 8004970:	bd80      	pop	{r7, pc}
 8004972:	bf00      	nop
 8004974:	e000ed04 	.word	0xe000ed04

08004978 <prvCopyDataToQueue>:

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
 8004978:	b580      	push	{r7, lr}
 800497a:	b086      	sub	sp, #24
 800497c:	af00      	add	r7, sp, #0
 800497e:	60f8      	str	r0, [r7, #12]
 8004980:	60b9      	str	r1, [r7, #8]
 8004982:	607a      	str	r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
 8004984:	2300      	movs	r3, #0
 8004986:	617b      	str	r3, [r7, #20]
UBaseType_t uxMessagesWaiting;

	/* This function is called from a critical section. */

	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8004988:	68fb      	ldr	r3, [r7, #12]
 800498a:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 800498c:	613b      	str	r3, [r7, #16]

	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
 800498e:	68fb      	ldr	r3, [r7, #12]
 8004990:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004992:	2b00      	cmp	r3, #0
 8004994:	d10d      	bne.n	80049b2 <prvCopyDataToQueue+0x3a>
	{
		#if ( configUSE_MUTEXES == 1 )
		{
			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 8004996:	68fb      	ldr	r3, [r7, #12]
 8004998:	681b      	ldr	r3, [r3, #0]
 800499a:	2b00      	cmp	r3, #0
 800499c:	d14d      	bne.n	8004a3a <prvCopyDataToQueue+0xc2>
			{
				/* The mutex is no longer being held. */
				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
 800499e:	68fb      	ldr	r3, [r7, #12]
 80049a0:	689b      	ldr	r3, [r3, #8]
 80049a2:	4618      	mov	r0, r3
 80049a4:	f000 ffc6 	bl	8005934 <xTaskPriorityDisinherit>
 80049a8:	6178      	str	r0, [r7, #20]
				pxQueue->u.xSemaphore.xMutexHolder = NULL;
 80049aa:	68fb      	ldr	r3, [r7, #12]
 80049ac:	2200      	movs	r2, #0
 80049ae:	609a      	str	r2, [r3, #8]
 80049b0:	e043      	b.n	8004a3a <prvCopyDataToQueue+0xc2>
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configUSE_MUTEXES */
	}
	else if( xPosition == queueSEND_TO_BACK )
 80049b2:	687b      	ldr	r3, [r7, #4]
 80049b4:	2b00      	cmp	r3, #0
 80049b6:	d119      	bne.n	80049ec <prvCopyDataToQueue+0x74>
	{
		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 80049b8:	68fb      	ldr	r3, [r7, #12]
 80049ba:	6858      	ldr	r0, [r3, #4]
 80049bc:	68fb      	ldr	r3, [r7, #12]
 80049be:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80049c0:	461a      	mov	r2, r3
 80049c2:	68b9      	ldr	r1, [r7, #8]
 80049c4:	f002 f868 	bl	8006a98 <memcpy>
		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 80049c8:	68fb      	ldr	r3, [r7, #12]
 80049ca:	685a      	ldr	r2, [r3, #4]
 80049cc:	68fb      	ldr	r3, [r7, #12]
 80049ce:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80049d0:	441a      	add	r2, r3
 80049d2:	68fb      	ldr	r3, [r7, #12]
 80049d4:	605a      	str	r2, [r3, #4]
		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 80049d6:	68fb      	ldr	r3, [r7, #12]
 80049d8:	685a      	ldr	r2, [r3, #4]
 80049da:	68fb      	ldr	r3, [r7, #12]
 80049dc:	689b      	ldr	r3, [r3, #8]
 80049de:	429a      	cmp	r2, r3
 80049e0:	d32b      	bcc.n	8004a3a <prvCopyDataToQueue+0xc2>
		{
			pxQueue->pcWriteTo = pxQueue->pcHead;
 80049e2:	68fb      	ldr	r3, [r7, #12]
 80049e4:	681a      	ldr	r2, [r3, #0]
 80049e6:	68fb      	ldr	r3, [r7, #12]
 80049e8:	605a      	str	r2, [r3, #4]
 80049ea:	e026      	b.n	8004a3a <prvCopyDataToQueue+0xc2>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
 80049ec:	68fb      	ldr	r3, [r7, #12]
 80049ee:	68d8      	ldr	r0, [r3, #12]
 80049f0:	68fb      	ldr	r3, [r7, #12]
 80049f2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80049f4:	461a      	mov	r2, r3
 80049f6:	68b9      	ldr	r1, [r7, #8]
 80049f8:	f002 f84e 	bl	8006a98 <memcpy>
		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
 80049fc:	68fb      	ldr	r3, [r7, #12]
 80049fe:	68da      	ldr	r2, [r3, #12]
 8004a00:	68fb      	ldr	r3, [r7, #12]
 8004a02:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004a04:	425b      	negs	r3, r3
 8004a06:	441a      	add	r2, r3
 8004a08:	68fb      	ldr	r3, [r7, #12]
 8004a0a:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 8004a0c:	68fb      	ldr	r3, [r7, #12]
 8004a0e:	68da      	ldr	r2, [r3, #12]
 8004a10:	68fb      	ldr	r3, [r7, #12]
 8004a12:	681b      	ldr	r3, [r3, #0]
 8004a14:	429a      	cmp	r2, r3
 8004a16:	d207      	bcs.n	8004a28 <prvCopyDataToQueue+0xb0>
		{
			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
 8004a18:	68fb      	ldr	r3, [r7, #12]
 8004a1a:	689a      	ldr	r2, [r3, #8]
 8004a1c:	68fb      	ldr	r3, [r7, #12]
 8004a1e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004a20:	425b      	negs	r3, r3
 8004a22:	441a      	add	r2, r3
 8004a24:	68fb      	ldr	r3, [r7, #12]
 8004a26:	60da      	str	r2, [r3, #12]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		if( xPosition == queueOVERWRITE )
 8004a28:	687b      	ldr	r3, [r7, #4]
 8004a2a:	2b02      	cmp	r3, #2
 8004a2c:	d105      	bne.n	8004a3a <prvCopyDataToQueue+0xc2>
		{
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8004a2e:	693b      	ldr	r3, [r7, #16]
 8004a30:	2b00      	cmp	r3, #0
 8004a32:	d002      	beq.n	8004a3a <prvCopyDataToQueue+0xc2>
			{
				/* An item is not being added but overwritten, so subtract
				one from the recorded number of items in the queue so when
				one is added again below the number of recorded items remains
				correct. */
				--uxMessagesWaiting;
 8004a34:	693b      	ldr	r3, [r7, #16]
 8004a36:	3b01      	subs	r3, #1
 8004a38:	613b      	str	r3, [r7, #16]
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
 8004a3a:	693b      	ldr	r3, [r7, #16]
 8004a3c:	1c5a      	adds	r2, r3, #1
 8004a3e:	68fb      	ldr	r3, [r7, #12]
 8004a40:	639a      	str	r2, [r3, #56]	; 0x38

	return xReturn;
 8004a42:	697b      	ldr	r3, [r7, #20]
}
 8004a44:	4618      	mov	r0, r3
 8004a46:	3718      	adds	r7, #24
 8004a48:	46bd      	mov	sp, r7
 8004a4a:	bd80      	pop	{r7, pc}

08004a4c <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/

static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
 8004a4c:	b580      	push	{r7, lr}
 8004a4e:	b082      	sub	sp, #8
 8004a50:	af00      	add	r7, sp, #0
 8004a52:	6078      	str	r0, [r7, #4]
 8004a54:	6039      	str	r1, [r7, #0]
	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
 8004a56:	687b      	ldr	r3, [r7, #4]
 8004a58:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004a5a:	2b00      	cmp	r3, #0
 8004a5c:	d018      	beq.n	8004a90 <prvCopyDataFromQueue+0x44>
	{
		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 8004a5e:	687b      	ldr	r3, [r7, #4]
 8004a60:	68da      	ldr	r2, [r3, #12]
 8004a62:	687b      	ldr	r3, [r7, #4]
 8004a64:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004a66:	441a      	add	r2, r3
 8004a68:	687b      	ldr	r3, [r7, #4]
 8004a6a:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
 8004a6c:	687b      	ldr	r3, [r7, #4]
 8004a6e:	68da      	ldr	r2, [r3, #12]
 8004a70:	687b      	ldr	r3, [r7, #4]
 8004a72:	689b      	ldr	r3, [r3, #8]
 8004a74:	429a      	cmp	r2, r3
 8004a76:	d303      	bcc.n	8004a80 <prvCopyDataFromQueue+0x34>
		{
			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 8004a78:	687b      	ldr	r3, [r7, #4]
 8004a7a:	681a      	ldr	r2, [r3, #0]
 8004a7c:	687b      	ldr	r3, [r7, #4]
 8004a7e:	60da      	str	r2, [r3, #12]
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 8004a80:	687b      	ldr	r3, [r7, #4]
 8004a82:	68d9      	ldr	r1, [r3, #12]
 8004a84:	687b      	ldr	r3, [r7, #4]
 8004a86:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004a88:	461a      	mov	r2, r3
 8004a8a:	6838      	ldr	r0, [r7, #0]
 8004a8c:	f002 f804 	bl	8006a98 <memcpy>
	}
}
 8004a90:	bf00      	nop
 8004a92:	3708      	adds	r7, #8
 8004a94:	46bd      	mov	sp, r7
 8004a96:	bd80      	pop	{r7, pc}

08004a98 <prvUnlockQueue>:
/*-----------------------------------------------------------*/

static void prvUnlockQueue( Queue_t * const pxQueue )
{
 8004a98:	b580      	push	{r7, lr}
 8004a9a:	b084      	sub	sp, #16
 8004a9c:	af00      	add	r7, sp, #0
 8004a9e:	6078      	str	r0, [r7, #4]

	/* The lock counts contains the number of extra data items placed or
	removed from the queue while the queue was locked.  When a queue is
	locked items can be added or removed, but the event lists cannot be
	updated. */
	taskENTER_CRITICAL();
 8004aa0:	f001 fc88 	bl	80063b4 <vPortEnterCritical>
	{
		int8_t cTxLock = pxQueue->cTxLock;
 8004aa4:	687b      	ldr	r3, [r7, #4]
 8004aa6:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
 8004aaa:	73fb      	strb	r3, [r7, #15]

		/* See if data was added to the queue while it was locked. */
		while( cTxLock > queueLOCKED_UNMODIFIED )
 8004aac:	e011      	b.n	8004ad2 <prvUnlockQueue+0x3a>
			}
			#else /* configUSE_QUEUE_SETS */
			{
				/* Tasks that are removed from the event list will get added to
				the pending ready list as the scheduler is still suspended. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8004aae:	687b      	ldr	r3, [r7, #4]
 8004ab0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004ab2:	2b00      	cmp	r3, #0
 8004ab4:	d012      	beq.n	8004adc <prvUnlockQueue+0x44>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8004ab6:	687b      	ldr	r3, [r7, #4]
 8004ab8:	3324      	adds	r3, #36	; 0x24
 8004aba:	4618      	mov	r0, r3
 8004abc:	f000 fd58 	bl	8005570 <xTaskRemoveFromEventList>
 8004ac0:	4603      	mov	r3, r0
 8004ac2:	2b00      	cmp	r3, #0
 8004ac4:	d001      	beq.n	8004aca <prvUnlockQueue+0x32>
					{
						/* The task waiting has a higher priority so record that
						a context switch is required. */
						vTaskMissedYield();
 8004ac6:	f000 fe2f 	bl	8005728 <vTaskMissedYield>
					break;
				}
			}
			#endif /* configUSE_QUEUE_SETS */

			--cTxLock;
 8004aca:	7bfb      	ldrb	r3, [r7, #15]
 8004acc:	3b01      	subs	r3, #1
 8004ace:	b2db      	uxtb	r3, r3
 8004ad0:	73fb      	strb	r3, [r7, #15]
		while( cTxLock > queueLOCKED_UNMODIFIED )
 8004ad2:	f997 300f 	ldrsb.w	r3, [r7, #15]
 8004ad6:	2b00      	cmp	r3, #0
 8004ad8:	dce9      	bgt.n	8004aae <prvUnlockQueue+0x16>
 8004ada:	e000      	b.n	8004ade <prvUnlockQueue+0x46>
					break;
 8004adc:	bf00      	nop
		}

		pxQueue->cTxLock = queueUNLOCKED;
 8004ade:	687b      	ldr	r3, [r7, #4]
 8004ae0:	22ff      	movs	r2, #255	; 0xff
 8004ae2:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
	}
	taskEXIT_CRITICAL();
 8004ae6:	f001 fc95 	bl	8006414 <vPortExitCritical>

	/* Do the same for the Rx lock. */
	taskENTER_CRITICAL();
 8004aea:	f001 fc63 	bl	80063b4 <vPortEnterCritical>
	{
		int8_t cRxLock = pxQueue->cRxLock;
 8004aee:	687b      	ldr	r3, [r7, #4]
 8004af0:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
 8004af4:	73bb      	strb	r3, [r7, #14]

		while( cRxLock > queueLOCKED_UNMODIFIED )
 8004af6:	e011      	b.n	8004b1c <prvUnlockQueue+0x84>
		{
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8004af8:	687b      	ldr	r3, [r7, #4]
 8004afa:	691b      	ldr	r3, [r3, #16]
 8004afc:	2b00      	cmp	r3, #0
 8004afe:	d012      	beq.n	8004b26 <prvUnlockQueue+0x8e>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8004b00:	687b      	ldr	r3, [r7, #4]
 8004b02:	3310      	adds	r3, #16
 8004b04:	4618      	mov	r0, r3
 8004b06:	f000 fd33 	bl	8005570 <xTaskRemoveFromEventList>
 8004b0a:	4603      	mov	r3, r0
 8004b0c:	2b00      	cmp	r3, #0
 8004b0e:	d001      	beq.n	8004b14 <prvUnlockQueue+0x7c>
				{
					vTaskMissedYield();
 8004b10:	f000 fe0a 	bl	8005728 <vTaskMissedYield>
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				--cRxLock;
 8004b14:	7bbb      	ldrb	r3, [r7, #14]
 8004b16:	3b01      	subs	r3, #1
 8004b18:	b2db      	uxtb	r3, r3
 8004b1a:	73bb      	strb	r3, [r7, #14]
		while( cRxLock > queueLOCKED_UNMODIFIED )
 8004b1c:	f997 300e 	ldrsb.w	r3, [r7, #14]
 8004b20:	2b00      	cmp	r3, #0
 8004b22:	dce9      	bgt.n	8004af8 <prvUnlockQueue+0x60>
 8004b24:	e000      	b.n	8004b28 <prvUnlockQueue+0x90>
			}
			else
			{
				break;
 8004b26:	bf00      	nop
			}
		}

		pxQueue->cRxLock = queueUNLOCKED;
 8004b28:	687b      	ldr	r3, [r7, #4]
 8004b2a:	22ff      	movs	r2, #255	; 0xff
 8004b2c:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
	}
	taskEXIT_CRITICAL();
 8004b30:	f001 fc70 	bl	8006414 <vPortExitCritical>
}
 8004b34:	bf00      	nop
 8004b36:	3710      	adds	r7, #16
 8004b38:	46bd      	mov	sp, r7
 8004b3a:	bd80      	pop	{r7, pc}

08004b3c <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
 8004b3c:	b580      	push	{r7, lr}
 8004b3e:	b084      	sub	sp, #16
 8004b40:	af00      	add	r7, sp, #0
 8004b42:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 8004b44:	f001 fc36 	bl	80063b4 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
 8004b48:	687b      	ldr	r3, [r7, #4]
 8004b4a:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 8004b4c:	2b00      	cmp	r3, #0
 8004b4e:	d102      	bne.n	8004b56 <prvIsQueueEmpty+0x1a>
		{
			xReturn = pdTRUE;
 8004b50:	2301      	movs	r3, #1
 8004b52:	60fb      	str	r3, [r7, #12]
 8004b54:	e001      	b.n	8004b5a <prvIsQueueEmpty+0x1e>
		}
		else
		{
			xReturn = pdFALSE;
 8004b56:	2300      	movs	r3, #0
 8004b58:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 8004b5a:	f001 fc5b 	bl	8006414 <vPortExitCritical>

	return xReturn;
 8004b5e:	68fb      	ldr	r3, [r7, #12]
}
 8004b60:	4618      	mov	r0, r3
 8004b62:	3710      	adds	r7, #16
 8004b64:	46bd      	mov	sp, r7
 8004b66:	bd80      	pop	{r7, pc}

08004b68 <prvIsQueueFull>:
	return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
 8004b68:	b580      	push	{r7, lr}
 8004b6a:	b084      	sub	sp, #16
 8004b6c:	af00      	add	r7, sp, #0
 8004b6e:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 8004b70:	f001 fc20 	bl	80063b4 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
 8004b74:	687b      	ldr	r3, [r7, #4]
 8004b76:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 8004b78:	687b      	ldr	r3, [r7, #4]
 8004b7a:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8004b7c:	429a      	cmp	r2, r3
 8004b7e:	d102      	bne.n	8004b86 <prvIsQueueFull+0x1e>
		{
			xReturn = pdTRUE;
 8004b80:	2301      	movs	r3, #1
 8004b82:	60fb      	str	r3, [r7, #12]
 8004b84:	e001      	b.n	8004b8a <prvIsQueueFull+0x22>
		}
		else
		{
			xReturn = pdFALSE;
 8004b86:	2300      	movs	r3, #0
 8004b88:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 8004b8a:	f001 fc43 	bl	8006414 <vPortExitCritical>

	return xReturn;
 8004b8e:	68fb      	ldr	r3, [r7, #12]
}
 8004b90:	4618      	mov	r0, r3
 8004b92:	3710      	adds	r7, #16
 8004b94:	46bd      	mov	sp, r7
 8004b96:	bd80      	pop	{r7, pc}

08004b98 <vQueueAddToRegistry>:
/*-----------------------------------------------------------*/

#if ( configQUEUE_REGISTRY_SIZE > 0 )

	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
	{
 8004b98:	b480      	push	{r7}
 8004b9a:	b085      	sub	sp, #20
 8004b9c:	af00      	add	r7, sp, #0
 8004b9e:	6078      	str	r0, [r7, #4]
 8004ba0:	6039      	str	r1, [r7, #0]
	UBaseType_t ux;

		/* See if there is an empty space in the registry.  A NULL name denotes
		a free slot. */
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 8004ba2:	2300      	movs	r3, #0
 8004ba4:	60fb      	str	r3, [r7, #12]
 8004ba6:	e014      	b.n	8004bd2 <vQueueAddToRegistry+0x3a>
		{
			if( xQueueRegistry[ ux ].pcQueueName == NULL )
 8004ba8:	4a0f      	ldr	r2, [pc, #60]	; (8004be8 <vQueueAddToRegistry+0x50>)
 8004baa:	68fb      	ldr	r3, [r7, #12]
 8004bac:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
 8004bb0:	2b00      	cmp	r3, #0
 8004bb2:	d10b      	bne.n	8004bcc <vQueueAddToRegistry+0x34>
			{
				/* Store the information on this queue. */
				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
 8004bb4:	490c      	ldr	r1, [pc, #48]	; (8004be8 <vQueueAddToRegistry+0x50>)
 8004bb6:	68fb      	ldr	r3, [r7, #12]
 8004bb8:	683a      	ldr	r2, [r7, #0]
 8004bba:	f841 2033 	str.w	r2, [r1, r3, lsl #3]
				xQueueRegistry[ ux ].xHandle = xQueue;
 8004bbe:	4a0a      	ldr	r2, [pc, #40]	; (8004be8 <vQueueAddToRegistry+0x50>)
 8004bc0:	68fb      	ldr	r3, [r7, #12]
 8004bc2:	00db      	lsls	r3, r3, #3
 8004bc4:	4413      	add	r3, r2
 8004bc6:	687a      	ldr	r2, [r7, #4]
 8004bc8:	605a      	str	r2, [r3, #4]

				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
				break;
 8004bca:	e006      	b.n	8004bda <vQueueAddToRegistry+0x42>
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 8004bcc:	68fb      	ldr	r3, [r7, #12]
 8004bce:	3301      	adds	r3, #1
 8004bd0:	60fb      	str	r3, [r7, #12]
 8004bd2:	68fb      	ldr	r3, [r7, #12]
 8004bd4:	2b07      	cmp	r3, #7
 8004bd6:	d9e7      	bls.n	8004ba8 <vQueueAddToRegistry+0x10>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	}
 8004bd8:	bf00      	nop
 8004bda:	bf00      	nop
 8004bdc:	3714      	adds	r7, #20
 8004bde:	46bd      	mov	sp, r7
 8004be0:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004be4:	4770      	bx	lr
 8004be6:	bf00      	nop
 8004be8:	2000389c 	.word	0x2000389c

08004bec <vQueueWaitForMessageRestricted>:
/*-----------------------------------------------------------*/

#if ( configUSE_TIMERS == 1 )

	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 8004bec:	b580      	push	{r7, lr}
 8004bee:	b086      	sub	sp, #24
 8004bf0:	af00      	add	r7, sp, #0
 8004bf2:	60f8      	str	r0, [r7, #12]
 8004bf4:	60b9      	str	r1, [r7, #8]
 8004bf6:	607a      	str	r2, [r7, #4]
	Queue_t * const pxQueue = xQueue;
 8004bf8:	68fb      	ldr	r3, [r7, #12]
 8004bfa:	617b      	str	r3, [r7, #20]
		will not actually cause the task to block, just place it on a blocked
		list.  It will not block until the scheduler is unlocked - at which
		time a yield will be performed.  If an item is added to the queue while
		the queue is locked, and the calling task blocks on the queue, then the
		calling task will be immediately unblocked when the queue is unlocked. */
		prvLockQueue( pxQueue );
 8004bfc:	f001 fbda 	bl	80063b4 <vPortEnterCritical>
 8004c00:	697b      	ldr	r3, [r7, #20]
 8004c02:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
 8004c06:	b25b      	sxtb	r3, r3
 8004c08:	f1b3 3fff 	cmp.w	r3, #4294967295
 8004c0c:	d103      	bne.n	8004c16 <vQueueWaitForMessageRestricted+0x2a>
 8004c0e:	697b      	ldr	r3, [r7, #20]
 8004c10:	2200      	movs	r2, #0
 8004c12:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
 8004c16:	697b      	ldr	r3, [r7, #20]
 8004c18:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
 8004c1c:	b25b      	sxtb	r3, r3
 8004c1e:	f1b3 3fff 	cmp.w	r3, #4294967295
 8004c22:	d103      	bne.n	8004c2c <vQueueWaitForMessageRestricted+0x40>
 8004c24:	697b      	ldr	r3, [r7, #20]
 8004c26:	2200      	movs	r2, #0
 8004c28:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
 8004c2c:	f001 fbf2 	bl	8006414 <vPortExitCritical>
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
 8004c30:	697b      	ldr	r3, [r7, #20]
 8004c32:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 8004c34:	2b00      	cmp	r3, #0
 8004c36:	d106      	bne.n	8004c46 <vQueueWaitForMessageRestricted+0x5a>
		{
			/* There is nothing in the queue, block for the specified period. */
			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
 8004c38:	697b      	ldr	r3, [r7, #20]
 8004c3a:	3324      	adds	r3, #36	; 0x24
 8004c3c:	687a      	ldr	r2, [r7, #4]
 8004c3e:	68b9      	ldr	r1, [r7, #8]
 8004c40:	4618      	mov	r0, r3
 8004c42:	f000 fc69 	bl	8005518 <vTaskPlaceOnEventListRestricted>
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		prvUnlockQueue( pxQueue );
 8004c46:	6978      	ldr	r0, [r7, #20]
 8004c48:	f7ff ff26 	bl	8004a98 <prvUnlockQueue>
	}
 8004c4c:	bf00      	nop
 8004c4e:	3718      	adds	r7, #24
 8004c50:	46bd      	mov	sp, r7
 8004c52:	bd80      	pop	{r7, pc}

08004c54 <xTaskCreateStatic>:
									const uint32_t ulStackDepth,
									void * const pvParameters,
									UBaseType_t uxPriority,
									StackType_t * const puxStackBuffer,
									StaticTask_t * const pxTaskBuffer )
	{
 8004c54:	b580      	push	{r7, lr}
 8004c56:	b08e      	sub	sp, #56	; 0x38
 8004c58:	af04      	add	r7, sp, #16
 8004c5a:	60f8      	str	r0, [r7, #12]
 8004c5c:	60b9      	str	r1, [r7, #8]
 8004c5e:	607a      	str	r2, [r7, #4]
 8004c60:	603b      	str	r3, [r7, #0]
	TCB_t *pxNewTCB;
	TaskHandle_t xReturn;

		configASSERT( puxStackBuffer != NULL );
 8004c62:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 8004c64:	2b00      	cmp	r3, #0
 8004c66:	d10a      	bne.n	8004c7e <xTaskCreateStatic+0x2a>
	__asm volatile
 8004c68:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004c6c:	f383 8811 	msr	BASEPRI, r3
 8004c70:	f3bf 8f6f 	isb	sy
 8004c74:	f3bf 8f4f 	dsb	sy
 8004c78:	623b      	str	r3, [r7, #32]
}
 8004c7a:	bf00      	nop
 8004c7c:	e7fe      	b.n	8004c7c <xTaskCreateStatic+0x28>
		configASSERT( pxTaskBuffer != NULL );
 8004c7e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8004c80:	2b00      	cmp	r3, #0
 8004c82:	d10a      	bne.n	8004c9a <xTaskCreateStatic+0x46>
	__asm volatile
 8004c84:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004c88:	f383 8811 	msr	BASEPRI, r3
 8004c8c:	f3bf 8f6f 	isb	sy
 8004c90:	f3bf 8f4f 	dsb	sy
 8004c94:	61fb      	str	r3, [r7, #28]
}
 8004c96:	bf00      	nop
 8004c98:	e7fe      	b.n	8004c98 <xTaskCreateStatic+0x44>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticTask_t equals the size of the real task
			structure. */
			volatile size_t xSize = sizeof( StaticTask_t );
 8004c9a:	23bc      	movs	r3, #188	; 0xbc
 8004c9c:	613b      	str	r3, [r7, #16]
			configASSERT( xSize == sizeof( TCB_t ) );
 8004c9e:	693b      	ldr	r3, [r7, #16]
 8004ca0:	2bbc      	cmp	r3, #188	; 0xbc
 8004ca2:	d00a      	beq.n	8004cba <xTaskCreateStatic+0x66>
	__asm volatile
 8004ca4:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004ca8:	f383 8811 	msr	BASEPRI, r3
 8004cac:	f3bf 8f6f 	isb	sy
 8004cb0:	f3bf 8f4f 	dsb	sy
 8004cb4:	61bb      	str	r3, [r7, #24]
}
 8004cb6:	bf00      	nop
 8004cb8:	e7fe      	b.n	8004cb8 <xTaskCreateStatic+0x64>
			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
 8004cba:	693b      	ldr	r3, [r7, #16]
		}
		#endif /* configASSERT_DEFINED */


		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
 8004cbc:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8004cbe:	2b00      	cmp	r3, #0
 8004cc0:	d01e      	beq.n	8004d00 <xTaskCreateStatic+0xac>
 8004cc2:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 8004cc4:	2b00      	cmp	r3, #0
 8004cc6:	d01b      	beq.n	8004d00 <xTaskCreateStatic+0xac>
		{
			/* The memory used for the task's TCB and stack are passed into this
			function - use them. */
			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 8004cc8:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8004cca:	627b      	str	r3, [r7, #36]	; 0x24
			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 8004ccc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8004cce:	6b7a      	ldr	r2, [r7, #52]	; 0x34
 8004cd0:	631a      	str	r2, [r3, #48]	; 0x30

			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created statically in case the task is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
 8004cd2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8004cd4:	2202      	movs	r2, #2
 8004cd6:	f883 20b9 	strb.w	r2, [r3, #185]	; 0xb9
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
 8004cda:	2300      	movs	r3, #0
 8004cdc:	9303      	str	r3, [sp, #12]
 8004cde:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8004ce0:	9302      	str	r3, [sp, #8]
 8004ce2:	f107 0314 	add.w	r3, r7, #20
 8004ce6:	9301      	str	r3, [sp, #4]
 8004ce8:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004cea:	9300      	str	r3, [sp, #0]
 8004cec:	683b      	ldr	r3, [r7, #0]
 8004cee:	687a      	ldr	r2, [r7, #4]
 8004cf0:	68b9      	ldr	r1, [r7, #8]
 8004cf2:	68f8      	ldr	r0, [r7, #12]
 8004cf4:	f000 f850 	bl	8004d98 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 8004cf8:	6a78      	ldr	r0, [r7, #36]	; 0x24
 8004cfa:	f000 f8f3 	bl	8004ee4 <prvAddNewTaskToReadyList>
 8004cfe:	e001      	b.n	8004d04 <xTaskCreateStatic+0xb0>
		}
		else
		{
			xReturn = NULL;
 8004d00:	2300      	movs	r3, #0
 8004d02:	617b      	str	r3, [r7, #20]
		}

		return xReturn;
 8004d04:	697b      	ldr	r3, [r7, #20]
	}
 8004d06:	4618      	mov	r0, r3
 8004d08:	3728      	adds	r7, #40	; 0x28
 8004d0a:	46bd      	mov	sp, r7
 8004d0c:	bd80      	pop	{r7, pc}

08004d0e <xTaskCreate>:
							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
							const configSTACK_DEPTH_TYPE usStackDepth,
							void * const pvParameters,
							UBaseType_t uxPriority,
							TaskHandle_t * const pxCreatedTask )
	{
 8004d0e:	b580      	push	{r7, lr}
 8004d10:	b08c      	sub	sp, #48	; 0x30
 8004d12:	af04      	add	r7, sp, #16
 8004d14:	60f8      	str	r0, [r7, #12]
 8004d16:	60b9      	str	r1, [r7, #8]
 8004d18:	603b      	str	r3, [r7, #0]
 8004d1a:	4613      	mov	r3, r2
 8004d1c:	80fb      	strh	r3, [r7, #6]
		#else /* portSTACK_GROWTH */
		{
		StackType_t *pxStack;

			/* Allocate space for the stack used by the task being created. */
			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
 8004d1e:	88fb      	ldrh	r3, [r7, #6]
 8004d20:	009b      	lsls	r3, r3, #2
 8004d22:	4618      	mov	r0, r3
 8004d24:	f001 fc68 	bl	80065f8 <pvPortMalloc>
 8004d28:	6178      	str	r0, [r7, #20]

			if( pxStack != NULL )
 8004d2a:	697b      	ldr	r3, [r7, #20]
 8004d2c:	2b00      	cmp	r3, #0
 8004d2e:	d00e      	beq.n	8004d4e <xTaskCreate+0x40>
			{
				/* Allocate space for the TCB. */
				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
 8004d30:	20bc      	movs	r0, #188	; 0xbc
 8004d32:	f001 fc61 	bl	80065f8 <pvPortMalloc>
 8004d36:	61f8      	str	r0, [r7, #28]

				if( pxNewTCB != NULL )
 8004d38:	69fb      	ldr	r3, [r7, #28]
 8004d3a:	2b00      	cmp	r3, #0
 8004d3c:	d003      	beq.n	8004d46 <xTaskCreate+0x38>
				{
					/* Store the stack location in the TCB. */
					pxNewTCB->pxStack = pxStack;
 8004d3e:	69fb      	ldr	r3, [r7, #28]
 8004d40:	697a      	ldr	r2, [r7, #20]
 8004d42:	631a      	str	r2, [r3, #48]	; 0x30
 8004d44:	e005      	b.n	8004d52 <xTaskCreate+0x44>
				}
				else
				{
					/* The stack cannot be used as the TCB was not created.  Free
					it again. */
					vPortFree( pxStack );
 8004d46:	6978      	ldr	r0, [r7, #20]
 8004d48:	f001 fcfa 	bl	8006740 <vPortFree>
 8004d4c:	e001      	b.n	8004d52 <xTaskCreate+0x44>
				}
			}
			else
			{
				pxNewTCB = NULL;
 8004d4e:	2300      	movs	r3, #0
 8004d50:	61fb      	str	r3, [r7, #28]
			}
		}
		#endif /* portSTACK_GROWTH */

		if( pxNewTCB != NULL )
 8004d52:	69fb      	ldr	r3, [r7, #28]
 8004d54:	2b00      	cmp	r3, #0
 8004d56:	d017      	beq.n	8004d88 <xTaskCreate+0x7a>
		{
			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created dynamically in case it is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
 8004d58:	69fb      	ldr	r3, [r7, #28]
 8004d5a:	2200      	movs	r2, #0
 8004d5c:	f883 20b9 	strb.w	r2, [r3, #185]	; 0xb9
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
 8004d60:	88fa      	ldrh	r2, [r7, #6]
 8004d62:	2300      	movs	r3, #0
 8004d64:	9303      	str	r3, [sp, #12]
 8004d66:	69fb      	ldr	r3, [r7, #28]
 8004d68:	9302      	str	r3, [sp, #8]
 8004d6a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8004d6c:	9301      	str	r3, [sp, #4]
 8004d6e:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8004d70:	9300      	str	r3, [sp, #0]
 8004d72:	683b      	ldr	r3, [r7, #0]
 8004d74:	68b9      	ldr	r1, [r7, #8]
 8004d76:	68f8      	ldr	r0, [r7, #12]
 8004d78:	f000 f80e 	bl	8004d98 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 8004d7c:	69f8      	ldr	r0, [r7, #28]
 8004d7e:	f000 f8b1 	bl	8004ee4 <prvAddNewTaskToReadyList>
			xReturn = pdPASS;
 8004d82:	2301      	movs	r3, #1
 8004d84:	61bb      	str	r3, [r7, #24]
 8004d86:	e002      	b.n	8004d8e <xTaskCreate+0x80>
		}
		else
		{
			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
 8004d88:	f04f 33ff 	mov.w	r3, #4294967295
 8004d8c:	61bb      	str	r3, [r7, #24]
		}

		return xReturn;
 8004d8e:	69bb      	ldr	r3, [r7, #24]
	}
 8004d90:	4618      	mov	r0, r3
 8004d92:	3720      	adds	r7, #32
 8004d94:	46bd      	mov	sp, r7
 8004d96:	bd80      	pop	{r7, pc}

08004d98 <prvInitialiseNewTask>:
									void * const pvParameters,
									UBaseType_t uxPriority,
									TaskHandle_t * const pxCreatedTask,
									TCB_t *pxNewTCB,
									const MemoryRegion_t * const xRegions )
{
 8004d98:	b580      	push	{r7, lr}
 8004d9a:	b088      	sub	sp, #32
 8004d9c:	af00      	add	r7, sp, #0
 8004d9e:	60f8      	str	r0, [r7, #12]
 8004da0:	60b9      	str	r1, [r7, #8]
 8004da2:	607a      	str	r2, [r7, #4]
 8004da4:	603b      	str	r3, [r7, #0]

	/* Avoid dependency on memset() if it is not required. */
	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
	{
		/* Fill the stack with a known value to assist debugging. */
		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
 8004da6:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004da8:	6b18      	ldr	r0, [r3, #48]	; 0x30
 8004daa:	687b      	ldr	r3, [r7, #4]
 8004dac:	009b      	lsls	r3, r3, #2
 8004dae:	461a      	mov	r2, r3
 8004db0:	21a5      	movs	r1, #165	; 0xa5
 8004db2:	f001 fe7f 	bl	8006ab4 <memset>
	grows from high memory to low (as per the 80x86) or vice versa.
	portSTACK_GROWTH is used to make the result positive or negative as required
	by the port. */
	#if( portSTACK_GROWTH < 0 )
	{
		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
 8004db6:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004db8:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8004dba:	687b      	ldr	r3, [r7, #4]
 8004dbc:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
 8004dc0:	3b01      	subs	r3, #1
 8004dc2:	009b      	lsls	r3, r3, #2
 8004dc4:	4413      	add	r3, r2
 8004dc6:	61bb      	str	r3, [r7, #24]
		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
 8004dc8:	69bb      	ldr	r3, [r7, #24]
 8004dca:	f023 0307 	bic.w	r3, r3, #7
 8004dce:	61bb      	str	r3, [r7, #24]

		/* Check the alignment of the calculated top of stack is correct. */
		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
 8004dd0:	69bb      	ldr	r3, [r7, #24]
 8004dd2:	f003 0307 	and.w	r3, r3, #7
 8004dd6:	2b00      	cmp	r3, #0
 8004dd8:	d00a      	beq.n	8004df0 <prvInitialiseNewTask+0x58>
	__asm volatile
 8004dda:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004dde:	f383 8811 	msr	BASEPRI, r3
 8004de2:	f3bf 8f6f 	isb	sy
 8004de6:	f3bf 8f4f 	dsb	sy
 8004dea:	617b      	str	r3, [r7, #20]
}
 8004dec:	bf00      	nop
 8004dee:	e7fe      	b.n	8004dee <prvInitialiseNewTask+0x56>
		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
	}
	#endif /* portSTACK_GROWTH */

	/* Store the task name in the TCB. */
	if( pcName != NULL )
 8004df0:	68bb      	ldr	r3, [r7, #8]
 8004df2:	2b00      	cmp	r3, #0
 8004df4:	d01f      	beq.n	8004e36 <prvInitialiseNewTask+0x9e>
	{
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 8004df6:	2300      	movs	r3, #0
 8004df8:	61fb      	str	r3, [r7, #28]
 8004dfa:	e012      	b.n	8004e22 <prvInitialiseNewTask+0x8a>
		{
			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
 8004dfc:	68ba      	ldr	r2, [r7, #8]
 8004dfe:	69fb      	ldr	r3, [r7, #28]
 8004e00:	4413      	add	r3, r2
 8004e02:	7819      	ldrb	r1, [r3, #0]
 8004e04:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 8004e06:	69fb      	ldr	r3, [r7, #28]
 8004e08:	4413      	add	r3, r2
 8004e0a:	3334      	adds	r3, #52	; 0x34
 8004e0c:	460a      	mov	r2, r1
 8004e0e:	701a      	strb	r2, [r3, #0]

			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
			configMAX_TASK_NAME_LEN characters just in case the memory after the
			string is not accessible (extremely unlikely). */
			if( pcName[ x ] == ( char ) 0x00 )
 8004e10:	68ba      	ldr	r2, [r7, #8]
 8004e12:	69fb      	ldr	r3, [r7, #28]
 8004e14:	4413      	add	r3, r2
 8004e16:	781b      	ldrb	r3, [r3, #0]
 8004e18:	2b00      	cmp	r3, #0
 8004e1a:	d006      	beq.n	8004e2a <prvInitialiseNewTask+0x92>
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 8004e1c:	69fb      	ldr	r3, [r7, #28]
 8004e1e:	3301      	adds	r3, #1
 8004e20:	61fb      	str	r3, [r7, #28]
 8004e22:	69fb      	ldr	r3, [r7, #28]
 8004e24:	2b0f      	cmp	r3, #15
 8004e26:	d9e9      	bls.n	8004dfc <prvInitialiseNewTask+0x64>
 8004e28:	e000      	b.n	8004e2c <prvInitialiseNewTask+0x94>
			{
				break;
 8004e2a:	bf00      	nop
			}
		}

		/* Ensure the name string is terminated in the case that the string length
		was greater or equal to configMAX_TASK_NAME_LEN. */
		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
 8004e2c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e2e:	2200      	movs	r2, #0
 8004e30:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
 8004e34:	e003      	b.n	8004e3e <prvInitialiseNewTask+0xa6>
	}
	else
	{
		/* The task has not been given a name, so just ensure there is a NULL
		terminator when it is read out. */
		pxNewTCB->pcTaskName[ 0 ] = 0x00;
 8004e36:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e38:	2200      	movs	r2, #0
 8004e3a:	f883 2034 	strb.w	r2, [r3, #52]	; 0x34
	}

	/* This is used as an array index so must ensure it's not too large.  First
	remove the privilege bit if one is present. */
	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
 8004e3e:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8004e40:	2b37      	cmp	r3, #55	; 0x37
 8004e42:	d901      	bls.n	8004e48 <prvInitialiseNewTask+0xb0>
	{
		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
 8004e44:	2337      	movs	r3, #55	; 0x37
 8004e46:	62bb      	str	r3, [r7, #40]	; 0x28
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxNewTCB->uxPriority = uxPriority;
 8004e48:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e4a:	6aba      	ldr	r2, [r7, #40]	; 0x28
 8004e4c:	62da      	str	r2, [r3, #44]	; 0x2c
	#if ( configUSE_MUTEXES == 1 )
	{
		pxNewTCB->uxBasePriority = uxPriority;
 8004e4e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e50:	6aba      	ldr	r2, [r7, #40]	; 0x28
 8004e52:	64da      	str	r2, [r3, #76]	; 0x4c
		pxNewTCB->uxMutexesHeld = 0;
 8004e54:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e56:	2200      	movs	r2, #0
 8004e58:	651a      	str	r2, [r3, #80]	; 0x50
	}
	#endif /* configUSE_MUTEXES */

	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
 8004e5a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e5c:	3304      	adds	r3, #4
 8004e5e:	4618      	mov	r0, r3
 8004e60:	f7ff f978 	bl	8004154 <vListInitialiseItem>
	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
 8004e64:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e66:	3318      	adds	r3, #24
 8004e68:	4618      	mov	r0, r3
 8004e6a:	f7ff f973 	bl	8004154 <vListInitialiseItem>

	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
	back to	the containing TCB from a generic item in a list. */
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
 8004e6e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e70:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 8004e72:	611a      	str	r2, [r3, #16]

	/* Event lists are always in priority order. */
	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8004e74:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8004e76:	f1c3 0238 	rsb	r2, r3, #56	; 0x38
 8004e7a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e7c:	619a      	str	r2, [r3, #24]
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
 8004e7e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e80:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 8004e82:	625a      	str	r2, [r3, #36]	; 0x24
	}
	#endif

	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
	{
		pxNewTCB->ulNotifiedValue = 0;
 8004e84:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e86:	2200      	movs	r2, #0
 8004e88:	f8c3 20b4 	str.w	r2, [r3, #180]	; 0xb4
		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 8004e8c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e8e:	2200      	movs	r2, #0
 8004e90:	f883 20b8 	strb.w	r2, [r3, #184]	; 0xb8
	#if ( configUSE_NEWLIB_REENTRANT == 1 )
	{
		/* Initialise this task's Newlib reent structure.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
 8004e94:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004e96:	3354      	adds	r3, #84	; 0x54
 8004e98:	2260      	movs	r2, #96	; 0x60
 8004e9a:	2100      	movs	r1, #0
 8004e9c:	4618      	mov	r0, r3
 8004e9e:	f001 fe09 	bl	8006ab4 <memset>
 8004ea2:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004ea4:	4a0c      	ldr	r2, [pc, #48]	; (8004ed8 <prvInitialiseNewTask+0x140>)
 8004ea6:	659a      	str	r2, [r3, #88]	; 0x58
 8004ea8:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004eaa:	4a0c      	ldr	r2, [pc, #48]	; (8004edc <prvInitialiseNewTask+0x144>)
 8004eac:	65da      	str	r2, [r3, #92]	; 0x5c
 8004eae:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004eb0:	4a0b      	ldr	r2, [pc, #44]	; (8004ee0 <prvInitialiseNewTask+0x148>)
 8004eb2:	661a      	str	r2, [r3, #96]	; 0x60
			}
			#endif /* portSTACK_GROWTH */
		}
		#else /* portHAS_STACK_OVERFLOW_CHECKING */
		{
			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
 8004eb4:	683a      	ldr	r2, [r7, #0]
 8004eb6:	68f9      	ldr	r1, [r7, #12]
 8004eb8:	69b8      	ldr	r0, [r7, #24]
 8004eba:	f001 f94b 	bl	8006154 <pxPortInitialiseStack>
 8004ebe:	4602      	mov	r2, r0
 8004ec0:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004ec2:	601a      	str	r2, [r3, #0]
		}
		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
	}
	#endif /* portUSING_MPU_WRAPPERS */

	if( pxCreatedTask != NULL )
 8004ec4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8004ec6:	2b00      	cmp	r3, #0
 8004ec8:	d002      	beq.n	8004ed0 <prvInitialiseNewTask+0x138>
	{
		/* Pass the handle out in an anonymous way.  The handle can be used to
		change the created task's priority, delete the created task, etc.*/
		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
 8004eca:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8004ecc:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 8004ece:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 8004ed0:	bf00      	nop
 8004ed2:	3720      	adds	r7, #32
 8004ed4:	46bd      	mov	sp, r7
 8004ed6:	bd80      	pop	{r7, pc}
 8004ed8:	08006d40 	.word	0x08006d40
 8004edc:	08006d60 	.word	0x08006d60
 8004ee0:	08006d20 	.word	0x08006d20

08004ee4 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/

static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
 8004ee4:	b580      	push	{r7, lr}
 8004ee6:	b082      	sub	sp, #8
 8004ee8:	af00      	add	r7, sp, #0
 8004eea:	6078      	str	r0, [r7, #4]
	/* Ensure interrupts don't access the task lists while the lists are being
	updated. */
	taskENTER_CRITICAL();
 8004eec:	f001 fa62 	bl	80063b4 <vPortEnterCritical>
	{
		uxCurrentNumberOfTasks++;
 8004ef0:	4b2d      	ldr	r3, [pc, #180]	; (8004fa8 <prvAddNewTaskToReadyList+0xc4>)
 8004ef2:	681b      	ldr	r3, [r3, #0]
 8004ef4:	3301      	adds	r3, #1
 8004ef6:	4a2c      	ldr	r2, [pc, #176]	; (8004fa8 <prvAddNewTaskToReadyList+0xc4>)
 8004ef8:	6013      	str	r3, [r2, #0]
		if( pxCurrentTCB == NULL )
 8004efa:	4b2c      	ldr	r3, [pc, #176]	; (8004fac <prvAddNewTaskToReadyList+0xc8>)
 8004efc:	681b      	ldr	r3, [r3, #0]
 8004efe:	2b00      	cmp	r3, #0
 8004f00:	d109      	bne.n	8004f16 <prvAddNewTaskToReadyList+0x32>
		{
			/* There are no other tasks, or all the other tasks are in
			the suspended state - make this the current task. */
			pxCurrentTCB = pxNewTCB;
 8004f02:	4a2a      	ldr	r2, [pc, #168]	; (8004fac <prvAddNewTaskToReadyList+0xc8>)
 8004f04:	687b      	ldr	r3, [r7, #4]
 8004f06:	6013      	str	r3, [r2, #0]

			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
 8004f08:	4b27      	ldr	r3, [pc, #156]	; (8004fa8 <prvAddNewTaskToReadyList+0xc4>)
 8004f0a:	681b      	ldr	r3, [r3, #0]
 8004f0c:	2b01      	cmp	r3, #1
 8004f0e:	d110      	bne.n	8004f32 <prvAddNewTaskToReadyList+0x4e>
			{
				/* This is the first task to be created so do the preliminary
				initialisation required.  We will not recover if this call
				fails, but we will report the failure. */
				prvInitialiseTaskLists();
 8004f10:	f000 fc30 	bl	8005774 <prvInitialiseTaskLists>
 8004f14:	e00d      	b.n	8004f32 <prvAddNewTaskToReadyList+0x4e>
		else
		{
			/* If the scheduler is not already running, make this task the
			current task if it is the highest priority task to be created
			so far. */
			if( xSchedulerRunning == pdFALSE )
 8004f16:	4b26      	ldr	r3, [pc, #152]	; (8004fb0 <prvAddNewTaskToReadyList+0xcc>)
 8004f18:	681b      	ldr	r3, [r3, #0]
 8004f1a:	2b00      	cmp	r3, #0
 8004f1c:	d109      	bne.n	8004f32 <prvAddNewTaskToReadyList+0x4e>
			{
				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
 8004f1e:	4b23      	ldr	r3, [pc, #140]	; (8004fac <prvAddNewTaskToReadyList+0xc8>)
 8004f20:	681b      	ldr	r3, [r3, #0]
 8004f22:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004f24:	687b      	ldr	r3, [r7, #4]
 8004f26:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004f28:	429a      	cmp	r2, r3
 8004f2a:	d802      	bhi.n	8004f32 <prvAddNewTaskToReadyList+0x4e>
				{
					pxCurrentTCB = pxNewTCB;
 8004f2c:	4a1f      	ldr	r2, [pc, #124]	; (8004fac <prvAddNewTaskToReadyList+0xc8>)
 8004f2e:	687b      	ldr	r3, [r7, #4]
 8004f30:	6013      	str	r3, [r2, #0]
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}

		uxTaskNumber++;
 8004f32:	4b20      	ldr	r3, [pc, #128]	; (8004fb4 <prvAddNewTaskToReadyList+0xd0>)
 8004f34:	681b      	ldr	r3, [r3, #0]
 8004f36:	3301      	adds	r3, #1
 8004f38:	4a1e      	ldr	r2, [pc, #120]	; (8004fb4 <prvAddNewTaskToReadyList+0xd0>)
 8004f3a:	6013      	str	r3, [r2, #0]

		#if ( configUSE_TRACE_FACILITY == 1 )
		{
			/* Add a counter into the TCB for tracing only. */
			pxNewTCB->uxTCBNumber = uxTaskNumber;
 8004f3c:	4b1d      	ldr	r3, [pc, #116]	; (8004fb4 <prvAddNewTaskToReadyList+0xd0>)
 8004f3e:	681a      	ldr	r2, [r3, #0]
 8004f40:	687b      	ldr	r3, [r7, #4]
 8004f42:	645a      	str	r2, [r3, #68]	; 0x44
		}
		#endif /* configUSE_TRACE_FACILITY */
		traceTASK_CREATE( pxNewTCB );

		prvAddTaskToReadyList( pxNewTCB );
 8004f44:	687b      	ldr	r3, [r7, #4]
 8004f46:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004f48:	4b1b      	ldr	r3, [pc, #108]	; (8004fb8 <prvAddNewTaskToReadyList+0xd4>)
 8004f4a:	681b      	ldr	r3, [r3, #0]
 8004f4c:	429a      	cmp	r2, r3
 8004f4e:	d903      	bls.n	8004f58 <prvAddNewTaskToReadyList+0x74>
 8004f50:	687b      	ldr	r3, [r7, #4]
 8004f52:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004f54:	4a18      	ldr	r2, [pc, #96]	; (8004fb8 <prvAddNewTaskToReadyList+0xd4>)
 8004f56:	6013      	str	r3, [r2, #0]
 8004f58:	687b      	ldr	r3, [r7, #4]
 8004f5a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004f5c:	4613      	mov	r3, r2
 8004f5e:	009b      	lsls	r3, r3, #2
 8004f60:	4413      	add	r3, r2
 8004f62:	009b      	lsls	r3, r3, #2
 8004f64:	4a15      	ldr	r2, [pc, #84]	; (8004fbc <prvAddNewTaskToReadyList+0xd8>)
 8004f66:	441a      	add	r2, r3
 8004f68:	687b      	ldr	r3, [r7, #4]
 8004f6a:	3304      	adds	r3, #4
 8004f6c:	4619      	mov	r1, r3
 8004f6e:	4610      	mov	r0, r2
 8004f70:	f7ff f8fd 	bl	800416e <vListInsertEnd>

		portSETUP_TCB( pxNewTCB );
	}
	taskEXIT_CRITICAL();
 8004f74:	f001 fa4e 	bl	8006414 <vPortExitCritical>

	if( xSchedulerRunning != pdFALSE )
 8004f78:	4b0d      	ldr	r3, [pc, #52]	; (8004fb0 <prvAddNewTaskToReadyList+0xcc>)
 8004f7a:	681b      	ldr	r3, [r3, #0]
 8004f7c:	2b00      	cmp	r3, #0
 8004f7e:	d00e      	beq.n	8004f9e <prvAddNewTaskToReadyList+0xba>
	{
		/* If the created task is of a higher priority than the current task
		then it should run now. */
		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
 8004f80:	4b0a      	ldr	r3, [pc, #40]	; (8004fac <prvAddNewTaskToReadyList+0xc8>)
 8004f82:	681b      	ldr	r3, [r3, #0]
 8004f84:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004f86:	687b      	ldr	r3, [r7, #4]
 8004f88:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004f8a:	429a      	cmp	r2, r3
 8004f8c:	d207      	bcs.n	8004f9e <prvAddNewTaskToReadyList+0xba>
		{
			taskYIELD_IF_USING_PREEMPTION();
 8004f8e:	4b0c      	ldr	r3, [pc, #48]	; (8004fc0 <prvAddNewTaskToReadyList+0xdc>)
 8004f90:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8004f94:	601a      	str	r2, [r3, #0]
 8004f96:	f3bf 8f4f 	dsb	sy
 8004f9a:	f3bf 8f6f 	isb	sy
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 8004f9e:	bf00      	nop
 8004fa0:	3708      	adds	r7, #8
 8004fa2:	46bd      	mov	sp, r7
 8004fa4:	bd80      	pop	{r7, pc}
 8004fa6:	bf00      	nop
 8004fa8:	20003db0 	.word	0x20003db0
 8004fac:	200038dc 	.word	0x200038dc
 8004fb0:	20003dbc 	.word	0x20003dbc
 8004fb4:	20003dcc 	.word	0x20003dcc
 8004fb8:	20003db8 	.word	0x20003db8
 8004fbc:	200038e0 	.word	0x200038e0
 8004fc0:	e000ed04 	.word	0xe000ed04

08004fc4 <vTaskDelay>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelay == 1 )

	void vTaskDelay( const TickType_t xTicksToDelay )
	{
 8004fc4:	b580      	push	{r7, lr}
 8004fc6:	b084      	sub	sp, #16
 8004fc8:	af00      	add	r7, sp, #0
 8004fca:	6078      	str	r0, [r7, #4]
	BaseType_t xAlreadyYielded = pdFALSE;
 8004fcc:	2300      	movs	r3, #0
 8004fce:	60fb      	str	r3, [r7, #12]

		/* A delay time of zero just forces a reschedule. */
		if( xTicksToDelay > ( TickType_t ) 0U )
 8004fd0:	687b      	ldr	r3, [r7, #4]
 8004fd2:	2b00      	cmp	r3, #0
 8004fd4:	d017      	beq.n	8005006 <vTaskDelay+0x42>
		{
			configASSERT( uxSchedulerSuspended == 0 );
 8004fd6:	4b13      	ldr	r3, [pc, #76]	; (8005024 <vTaskDelay+0x60>)
 8004fd8:	681b      	ldr	r3, [r3, #0]
 8004fda:	2b00      	cmp	r3, #0
 8004fdc:	d00a      	beq.n	8004ff4 <vTaskDelay+0x30>
	__asm volatile
 8004fde:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004fe2:	f383 8811 	msr	BASEPRI, r3
 8004fe6:	f3bf 8f6f 	isb	sy
 8004fea:	f3bf 8f4f 	dsb	sy
 8004fee:	60bb      	str	r3, [r7, #8]
}
 8004ff0:	bf00      	nop
 8004ff2:	e7fe      	b.n	8004ff2 <vTaskDelay+0x2e>
			vTaskSuspendAll();
 8004ff4:	f000 f88a 	bl	800510c <vTaskSuspendAll>
				list or removed from the blocked list until the scheduler
				is resumed.

				This task cannot be in an event list as it is the currently
				executing task. */
				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
 8004ff8:	2100      	movs	r1, #0
 8004ffa:	6878      	ldr	r0, [r7, #4]
 8004ffc:	f000 fd08 	bl	8005a10 <prvAddCurrentTaskToDelayedList>
			}
			xAlreadyYielded = xTaskResumeAll();
 8005000:	f000 f892 	bl	8005128 <xTaskResumeAll>
 8005004:	60f8      	str	r0, [r7, #12]
			mtCOVERAGE_TEST_MARKER();
		}

		/* Force a reschedule if xTaskResumeAll has not already done so, we may
		have put ourselves to sleep. */
		if( xAlreadyYielded == pdFALSE )
 8005006:	68fb      	ldr	r3, [r7, #12]
 8005008:	2b00      	cmp	r3, #0
 800500a:	d107      	bne.n	800501c <vTaskDelay+0x58>
		{
			portYIELD_WITHIN_API();
 800500c:	4b06      	ldr	r3, [pc, #24]	; (8005028 <vTaskDelay+0x64>)
 800500e:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8005012:	601a      	str	r2, [r3, #0]
 8005014:	f3bf 8f4f 	dsb	sy
 8005018:	f3bf 8f6f 	isb	sy
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
 800501c:	bf00      	nop
 800501e:	3710      	adds	r7, #16
 8005020:	46bd      	mov	sp, r7
 8005022:	bd80      	pop	{r7, pc}
 8005024:	20003dd8 	.word	0x20003dd8
 8005028:	e000ed04 	.word	0xe000ed04

0800502c <vTaskStartScheduler>:

#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/

void vTaskStartScheduler( void )
{
 800502c:	b580      	push	{r7, lr}
 800502e:	b08a      	sub	sp, #40	; 0x28
 8005030:	af04      	add	r7, sp, #16
BaseType_t xReturn;

	/* Add the idle task at the lowest priority. */
	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
	{
		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
 8005032:	2300      	movs	r3, #0
 8005034:	60bb      	str	r3, [r7, #8]
		StackType_t *pxIdleTaskStackBuffer = NULL;
 8005036:	2300      	movs	r3, #0
 8005038:	607b      	str	r3, [r7, #4]
		uint32_t ulIdleTaskStackSize;

		/* The Idle task is created using user provided RAM - obtain the
		address of the RAM then create the idle task. */
		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
 800503a:	463a      	mov	r2, r7
 800503c:	1d39      	adds	r1, r7, #4
 800503e:	f107 0308 	add.w	r3, r7, #8
 8005042:	4618      	mov	r0, r3
 8005044:	f7ff f832 	bl	80040ac <vApplicationGetIdleTaskMemory>
		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
 8005048:	6839      	ldr	r1, [r7, #0]
 800504a:	687b      	ldr	r3, [r7, #4]
 800504c:	68ba      	ldr	r2, [r7, #8]
 800504e:	9202      	str	r2, [sp, #8]
 8005050:	9301      	str	r3, [sp, #4]
 8005052:	2300      	movs	r3, #0
 8005054:	9300      	str	r3, [sp, #0]
 8005056:	2300      	movs	r3, #0
 8005058:	460a      	mov	r2, r1
 800505a:	4924      	ldr	r1, [pc, #144]	; (80050ec <vTaskStartScheduler+0xc0>)
 800505c:	4824      	ldr	r0, [pc, #144]	; (80050f0 <vTaskStartScheduler+0xc4>)
 800505e:	f7ff fdf9 	bl	8004c54 <xTaskCreateStatic>
 8005062:	4603      	mov	r3, r0
 8005064:	4a23      	ldr	r2, [pc, #140]	; (80050f4 <vTaskStartScheduler+0xc8>)
 8005066:	6013      	str	r3, [r2, #0]
												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
												pxIdleTaskStackBuffer,
												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */

		if( xIdleTaskHandle != NULL )
 8005068:	4b22      	ldr	r3, [pc, #136]	; (80050f4 <vTaskStartScheduler+0xc8>)
 800506a:	681b      	ldr	r3, [r3, #0]
 800506c:	2b00      	cmp	r3, #0
 800506e:	d002      	beq.n	8005076 <vTaskStartScheduler+0x4a>
		{
			xReturn = pdPASS;
 8005070:	2301      	movs	r3, #1
 8005072:	617b      	str	r3, [r7, #20]
 8005074:	e001      	b.n	800507a <vTaskStartScheduler+0x4e>
		}
		else
		{
			xReturn = pdFAIL;
 8005076:	2300      	movs	r3, #0
 8005078:	617b      	str	r3, [r7, #20]
	}
	#endif /* configSUPPORT_STATIC_ALLOCATION */

	#if ( configUSE_TIMERS == 1 )
	{
		if( xReturn == pdPASS )
 800507a:	697b      	ldr	r3, [r7, #20]
 800507c:	2b01      	cmp	r3, #1
 800507e:	d102      	bne.n	8005086 <vTaskStartScheduler+0x5a>
		{
			xReturn = xTimerCreateTimerTask();
 8005080:	f000 fd1a 	bl	8005ab8 <xTimerCreateTimerTask>
 8005084:	6178      	str	r0, [r7, #20]
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif /* configUSE_TIMERS */

	if( xReturn == pdPASS )
 8005086:	697b      	ldr	r3, [r7, #20]
 8005088:	2b01      	cmp	r3, #1
 800508a:	d11b      	bne.n	80050c4 <vTaskStartScheduler+0x98>
	__asm volatile
 800508c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005090:	f383 8811 	msr	BASEPRI, r3
 8005094:	f3bf 8f6f 	isb	sy
 8005098:	f3bf 8f4f 	dsb	sy
 800509c:	613b      	str	r3, [r7, #16]
}
 800509e:	bf00      	nop
		{
			/* Switch Newlib's _impure_ptr variable to point to the _reent
			structure specific to the task that will run first.
			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 80050a0:	4b15      	ldr	r3, [pc, #84]	; (80050f8 <vTaskStartScheduler+0xcc>)
 80050a2:	681b      	ldr	r3, [r3, #0]
 80050a4:	3354      	adds	r3, #84	; 0x54
 80050a6:	4a15      	ldr	r2, [pc, #84]	; (80050fc <vTaskStartScheduler+0xd0>)
 80050a8:	6013      	str	r3, [r2, #0]
		}
		#endif /* configUSE_NEWLIB_REENTRANT */

		xNextTaskUnblockTime = portMAX_DELAY;
 80050aa:	4b15      	ldr	r3, [pc, #84]	; (8005100 <vTaskStartScheduler+0xd4>)
 80050ac:	f04f 32ff 	mov.w	r2, #4294967295
 80050b0:	601a      	str	r2, [r3, #0]
		xSchedulerRunning = pdTRUE;
 80050b2:	4b14      	ldr	r3, [pc, #80]	; (8005104 <vTaskStartScheduler+0xd8>)
 80050b4:	2201      	movs	r2, #1
 80050b6:	601a      	str	r2, [r3, #0]
		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
 80050b8:	4b13      	ldr	r3, [pc, #76]	; (8005108 <vTaskStartScheduler+0xdc>)
 80050ba:	2200      	movs	r2, #0
 80050bc:	601a      	str	r2, [r3, #0]

		traceTASK_SWITCHED_IN();

		/* Setting up the timer tick is hardware specific and thus in the
		portable interface. */
		if( xPortStartScheduler() != pdFALSE )
 80050be:	f001 f8d7 	bl	8006270 <xPortStartScheduler>
	}

	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
	meaning xIdleTaskHandle is not used anywhere else. */
	( void ) xIdleTaskHandle;
}
 80050c2:	e00e      	b.n	80050e2 <vTaskStartScheduler+0xb6>
		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
 80050c4:	697b      	ldr	r3, [r7, #20]
 80050c6:	f1b3 3fff 	cmp.w	r3, #4294967295
 80050ca:	d10a      	bne.n	80050e2 <vTaskStartScheduler+0xb6>
	__asm volatile
 80050cc:	f04f 0350 	mov.w	r3, #80	; 0x50
 80050d0:	f383 8811 	msr	BASEPRI, r3
 80050d4:	f3bf 8f6f 	isb	sy
 80050d8:	f3bf 8f4f 	dsb	sy
 80050dc:	60fb      	str	r3, [r7, #12]
}
 80050de:	bf00      	nop
 80050e0:	e7fe      	b.n	80050e0 <vTaskStartScheduler+0xb4>
}
 80050e2:	bf00      	nop
 80050e4:	3718      	adds	r7, #24
 80050e6:	46bd      	mov	sp, r7
 80050e8:	bd80      	pop	{r7, pc}
 80050ea:	bf00      	nop
 80050ec:	08006c78 	.word	0x08006c78
 80050f0:	08005741 	.word	0x08005741
 80050f4:	20003dd4 	.word	0x20003dd4
 80050f8:	200038dc 	.word	0x200038dc
 80050fc:	20000020 	.word	0x20000020
 8005100:	20003dd0 	.word	0x20003dd0
 8005104:	20003dbc 	.word	0x20003dbc
 8005108:	20003db4 	.word	0x20003db4

0800510c <vTaskSuspendAll>:
	vPortEndScheduler();
}
/*----------------------------------------------------------*/

void vTaskSuspendAll( void )
{
 800510c:	b480      	push	{r7}
 800510e:	af00      	add	r7, sp, #0
	do not otherwise exhibit real time behaviour. */
	portSOFTWARE_BARRIER();

	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
	is used to allow calls to vTaskSuspendAll() to nest. */
	++uxSchedulerSuspended;
 8005110:	4b04      	ldr	r3, [pc, #16]	; (8005124 <vTaskSuspendAll+0x18>)
 8005112:	681b      	ldr	r3, [r3, #0]
 8005114:	3301      	adds	r3, #1
 8005116:	4a03      	ldr	r2, [pc, #12]	; (8005124 <vTaskSuspendAll+0x18>)
 8005118:	6013      	str	r3, [r2, #0]

	/* Enforces ordering for ports and optimised compilers that may otherwise place
	the above increment elsewhere. */
	portMEMORY_BARRIER();
}
 800511a:	bf00      	nop
 800511c:	46bd      	mov	sp, r7
 800511e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005122:	4770      	bx	lr
 8005124:	20003dd8 	.word	0x20003dd8

08005128 <xTaskResumeAll>:

#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/

BaseType_t xTaskResumeAll( void )
{
 8005128:	b580      	push	{r7, lr}
 800512a:	b084      	sub	sp, #16
 800512c:	af00      	add	r7, sp, #0
TCB_t *pxTCB = NULL;
 800512e:	2300      	movs	r3, #0
 8005130:	60fb      	str	r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
 8005132:	2300      	movs	r3, #0
 8005134:	60bb      	str	r3, [r7, #8]

	/* If uxSchedulerSuspended is zero then this function does not match a
	previous call to vTaskSuspendAll(). */
	configASSERT( uxSchedulerSuspended );
 8005136:	4b42      	ldr	r3, [pc, #264]	; (8005240 <xTaskResumeAll+0x118>)
 8005138:	681b      	ldr	r3, [r3, #0]
 800513a:	2b00      	cmp	r3, #0
 800513c:	d10a      	bne.n	8005154 <xTaskResumeAll+0x2c>
	__asm volatile
 800513e:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005142:	f383 8811 	msr	BASEPRI, r3
 8005146:	f3bf 8f6f 	isb	sy
 800514a:	f3bf 8f4f 	dsb	sy
 800514e:	603b      	str	r3, [r7, #0]
}
 8005150:	bf00      	nop
 8005152:	e7fe      	b.n	8005152 <xTaskResumeAll+0x2a>
	/* It is possible that an ISR caused a task to be removed from an event
	list while the scheduler was suspended.  If this was the case then the
	removed task will have been added to the xPendingReadyList.  Once the
	scheduler has been resumed it is safe to move all the pending ready
	tasks from this list into their appropriate ready list. */
	taskENTER_CRITICAL();
 8005154:	f001 f92e 	bl	80063b4 <vPortEnterCritical>
	{
		--uxSchedulerSuspended;
 8005158:	4b39      	ldr	r3, [pc, #228]	; (8005240 <xTaskResumeAll+0x118>)
 800515a:	681b      	ldr	r3, [r3, #0]
 800515c:	3b01      	subs	r3, #1
 800515e:	4a38      	ldr	r2, [pc, #224]	; (8005240 <xTaskResumeAll+0x118>)
 8005160:	6013      	str	r3, [r2, #0]

		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8005162:	4b37      	ldr	r3, [pc, #220]	; (8005240 <xTaskResumeAll+0x118>)
 8005164:	681b      	ldr	r3, [r3, #0]
 8005166:	2b00      	cmp	r3, #0
 8005168:	d162      	bne.n	8005230 <xTaskResumeAll+0x108>
		{
			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
 800516a:	4b36      	ldr	r3, [pc, #216]	; (8005244 <xTaskResumeAll+0x11c>)
 800516c:	681b      	ldr	r3, [r3, #0]
 800516e:	2b00      	cmp	r3, #0
 8005170:	d05e      	beq.n	8005230 <xTaskResumeAll+0x108>
			{
				/* Move any readied tasks from the pending list into the
				appropriate ready list. */
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 8005172:	e02f      	b.n	80051d4 <xTaskResumeAll+0xac>
				{
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8005174:	4b34      	ldr	r3, [pc, #208]	; (8005248 <xTaskResumeAll+0x120>)
 8005176:	68db      	ldr	r3, [r3, #12]
 8005178:	68db      	ldr	r3, [r3, #12]
 800517a:	60fb      	str	r3, [r7, #12]
					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 800517c:	68fb      	ldr	r3, [r7, #12]
 800517e:	3318      	adds	r3, #24
 8005180:	4618      	mov	r0, r3
 8005182:	f7ff f851 	bl	8004228 <uxListRemove>
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8005186:	68fb      	ldr	r3, [r7, #12]
 8005188:	3304      	adds	r3, #4
 800518a:	4618      	mov	r0, r3
 800518c:	f7ff f84c 	bl	8004228 <uxListRemove>
					prvAddTaskToReadyList( pxTCB );
 8005190:	68fb      	ldr	r3, [r7, #12]
 8005192:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8005194:	4b2d      	ldr	r3, [pc, #180]	; (800524c <xTaskResumeAll+0x124>)
 8005196:	681b      	ldr	r3, [r3, #0]
 8005198:	429a      	cmp	r2, r3
 800519a:	d903      	bls.n	80051a4 <xTaskResumeAll+0x7c>
 800519c:	68fb      	ldr	r3, [r7, #12]
 800519e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80051a0:	4a2a      	ldr	r2, [pc, #168]	; (800524c <xTaskResumeAll+0x124>)
 80051a2:	6013      	str	r3, [r2, #0]
 80051a4:	68fb      	ldr	r3, [r7, #12]
 80051a6:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 80051a8:	4613      	mov	r3, r2
 80051aa:	009b      	lsls	r3, r3, #2
 80051ac:	4413      	add	r3, r2
 80051ae:	009b      	lsls	r3, r3, #2
 80051b0:	4a27      	ldr	r2, [pc, #156]	; (8005250 <xTaskResumeAll+0x128>)
 80051b2:	441a      	add	r2, r3
 80051b4:	68fb      	ldr	r3, [r7, #12]
 80051b6:	3304      	adds	r3, #4
 80051b8:	4619      	mov	r1, r3
 80051ba:	4610      	mov	r0, r2
 80051bc:	f7fe ffd7 	bl	800416e <vListInsertEnd>

					/* If the moved task has a priority higher than the current
					task then a yield must be performed. */
					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 80051c0:	68fb      	ldr	r3, [r7, #12]
 80051c2:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 80051c4:	4b23      	ldr	r3, [pc, #140]	; (8005254 <xTaskResumeAll+0x12c>)
 80051c6:	681b      	ldr	r3, [r3, #0]
 80051c8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80051ca:	429a      	cmp	r2, r3
 80051cc:	d302      	bcc.n	80051d4 <xTaskResumeAll+0xac>
					{
						xYieldPending = pdTRUE;
 80051ce:	4b22      	ldr	r3, [pc, #136]	; (8005258 <xTaskResumeAll+0x130>)
 80051d0:	2201      	movs	r2, #1
 80051d2:	601a      	str	r2, [r3, #0]
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 80051d4:	4b1c      	ldr	r3, [pc, #112]	; (8005248 <xTaskResumeAll+0x120>)
 80051d6:	681b      	ldr	r3, [r3, #0]
 80051d8:	2b00      	cmp	r3, #0
 80051da:	d1cb      	bne.n	8005174 <xTaskResumeAll+0x4c>
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( pxTCB != NULL )
 80051dc:	68fb      	ldr	r3, [r7, #12]
 80051de:	2b00      	cmp	r3, #0
 80051e0:	d001      	beq.n	80051e6 <xTaskResumeAll+0xbe>
					which may have prevented the next unblock time from being
					re-calculated, in which case re-calculate it now.  Mainly
					important for low power tickless implementations, where
					this can prevent an unnecessary exit from low power
					state. */
					prvResetNextTaskUnblockTime();
 80051e2:	f000 fb69 	bl	80058b8 <prvResetNextTaskUnblockTime>
				/* If any ticks occurred while the scheduler was suspended then
				they should be processed now.  This ensures the tick count does
				not	slip, and that any delayed tasks are resumed at the correct
				time. */
				{
					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
 80051e6:	4b1d      	ldr	r3, [pc, #116]	; (800525c <xTaskResumeAll+0x134>)
 80051e8:	681b      	ldr	r3, [r3, #0]
 80051ea:	607b      	str	r3, [r7, #4]

					if( xPendedCounts > ( TickType_t ) 0U )
 80051ec:	687b      	ldr	r3, [r7, #4]
 80051ee:	2b00      	cmp	r3, #0
 80051f0:	d010      	beq.n	8005214 <xTaskResumeAll+0xec>
					{
						do
						{
							if( xTaskIncrementTick() != pdFALSE )
 80051f2:	f000 f847 	bl	8005284 <xTaskIncrementTick>
 80051f6:	4603      	mov	r3, r0
 80051f8:	2b00      	cmp	r3, #0
 80051fa:	d002      	beq.n	8005202 <xTaskResumeAll+0xda>
							{
								xYieldPending = pdTRUE;
 80051fc:	4b16      	ldr	r3, [pc, #88]	; (8005258 <xTaskResumeAll+0x130>)
 80051fe:	2201      	movs	r2, #1
 8005200:	601a      	str	r2, [r3, #0]
							}
							else
							{
								mtCOVERAGE_TEST_MARKER();
							}
							--xPendedCounts;
 8005202:	687b      	ldr	r3, [r7, #4]
 8005204:	3b01      	subs	r3, #1
 8005206:	607b      	str	r3, [r7, #4]
						} while( xPendedCounts > ( TickType_t ) 0U );
 8005208:	687b      	ldr	r3, [r7, #4]
 800520a:	2b00      	cmp	r3, #0
 800520c:	d1f1      	bne.n	80051f2 <xTaskResumeAll+0xca>

						xPendedTicks = 0;
 800520e:	4b13      	ldr	r3, [pc, #76]	; (800525c <xTaskResumeAll+0x134>)
 8005210:	2200      	movs	r2, #0
 8005212:	601a      	str	r2, [r3, #0]
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( xYieldPending != pdFALSE )
 8005214:	4b10      	ldr	r3, [pc, #64]	; (8005258 <xTaskResumeAll+0x130>)
 8005216:	681b      	ldr	r3, [r3, #0]
 8005218:	2b00      	cmp	r3, #0
 800521a:	d009      	beq.n	8005230 <xTaskResumeAll+0x108>
				{
					#if( configUSE_PREEMPTION != 0 )
					{
						xAlreadyYielded = pdTRUE;
 800521c:	2301      	movs	r3, #1
 800521e:	60bb      	str	r3, [r7, #8]
					}
					#endif
					taskYIELD_IF_USING_PREEMPTION();
 8005220:	4b0f      	ldr	r3, [pc, #60]	; (8005260 <xTaskResumeAll+0x138>)
 8005222:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8005226:	601a      	str	r2, [r3, #0]
 8005228:	f3bf 8f4f 	dsb	sy
 800522c:	f3bf 8f6f 	isb	sy
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 8005230:	f001 f8f0 	bl	8006414 <vPortExitCritical>

	return xAlreadyYielded;
 8005234:	68bb      	ldr	r3, [r7, #8]
}
 8005236:	4618      	mov	r0, r3
 8005238:	3710      	adds	r7, #16
 800523a:	46bd      	mov	sp, r7
 800523c:	bd80      	pop	{r7, pc}
 800523e:	bf00      	nop
 8005240:	20003dd8 	.word	0x20003dd8
 8005244:	20003db0 	.word	0x20003db0
 8005248:	20003d70 	.word	0x20003d70
 800524c:	20003db8 	.word	0x20003db8
 8005250:	200038e0 	.word	0x200038e0
 8005254:	200038dc 	.word	0x200038dc
 8005258:	20003dc4 	.word	0x20003dc4
 800525c:	20003dc0 	.word	0x20003dc0
 8005260:	e000ed04 	.word	0xe000ed04

08005264 <xTaskGetTickCount>:
/*-----------------------------------------------------------*/

TickType_t xTaskGetTickCount( void )
{
 8005264:	b480      	push	{r7}
 8005266:	b083      	sub	sp, #12
 8005268:	af00      	add	r7, sp, #0
TickType_t xTicks;

	/* Critical section required if running on a 16 bit processor. */
	portTICK_TYPE_ENTER_CRITICAL();
	{
		xTicks = xTickCount;
 800526a:	4b05      	ldr	r3, [pc, #20]	; (8005280 <xTaskGetTickCount+0x1c>)
 800526c:	681b      	ldr	r3, [r3, #0]
 800526e:	607b      	str	r3, [r7, #4]
	}
	portTICK_TYPE_EXIT_CRITICAL();

	return xTicks;
 8005270:	687b      	ldr	r3, [r7, #4]
}
 8005272:	4618      	mov	r0, r3
 8005274:	370c      	adds	r7, #12
 8005276:	46bd      	mov	sp, r7
 8005278:	f85d 7b04 	ldr.w	r7, [sp], #4
 800527c:	4770      	bx	lr
 800527e:	bf00      	nop
 8005280:	20003db4 	.word	0x20003db4

08005284 <xTaskIncrementTick>:

#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/

BaseType_t xTaskIncrementTick( void )
{
 8005284:	b580      	push	{r7, lr}
 8005286:	b086      	sub	sp, #24
 8005288:	af00      	add	r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
 800528a:	2300      	movs	r3, #0
 800528c:	617b      	str	r3, [r7, #20]

	/* Called by the portable layer each time a tick interrupt occurs.
	Increments the tick then checks to see if the new tick value will cause any
	tasks to be unblocked. */
	traceTASK_INCREMENT_TICK( xTickCount );
	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 800528e:	4b53      	ldr	r3, [pc, #332]	; (80053dc <xTaskIncrementTick+0x158>)
 8005290:	681b      	ldr	r3, [r3, #0]
 8005292:	2b00      	cmp	r3, #0
 8005294:	f040 8095 	bne.w	80053c2 <xTaskIncrementTick+0x13e>
	{
		/* Minor optimisation.  The tick count cannot change in this
		block. */
		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
 8005298:	4b51      	ldr	r3, [pc, #324]	; (80053e0 <xTaskIncrementTick+0x15c>)
 800529a:	681b      	ldr	r3, [r3, #0]
 800529c:	3301      	adds	r3, #1
 800529e:	613b      	str	r3, [r7, #16]

		/* Increment the RTOS tick, switching the delayed and overflowed
		delayed lists if it wraps to 0. */
		xTickCount = xConstTickCount;
 80052a0:	4a4f      	ldr	r2, [pc, #316]	; (80053e0 <xTaskIncrementTick+0x15c>)
 80052a2:	693b      	ldr	r3, [r7, #16]
 80052a4:	6013      	str	r3, [r2, #0]

		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
 80052a6:	693b      	ldr	r3, [r7, #16]
 80052a8:	2b00      	cmp	r3, #0
 80052aa:	d120      	bne.n	80052ee <xTaskIncrementTick+0x6a>
		{
			taskSWITCH_DELAYED_LISTS();
 80052ac:	4b4d      	ldr	r3, [pc, #308]	; (80053e4 <xTaskIncrementTick+0x160>)
 80052ae:	681b      	ldr	r3, [r3, #0]
 80052b0:	681b      	ldr	r3, [r3, #0]
 80052b2:	2b00      	cmp	r3, #0
 80052b4:	d00a      	beq.n	80052cc <xTaskIncrementTick+0x48>
	__asm volatile
 80052b6:	f04f 0350 	mov.w	r3, #80	; 0x50
 80052ba:	f383 8811 	msr	BASEPRI, r3
 80052be:	f3bf 8f6f 	isb	sy
 80052c2:	f3bf 8f4f 	dsb	sy
 80052c6:	603b      	str	r3, [r7, #0]
}
 80052c8:	bf00      	nop
 80052ca:	e7fe      	b.n	80052ca <xTaskIncrementTick+0x46>
 80052cc:	4b45      	ldr	r3, [pc, #276]	; (80053e4 <xTaskIncrementTick+0x160>)
 80052ce:	681b      	ldr	r3, [r3, #0]
 80052d0:	60fb      	str	r3, [r7, #12]
 80052d2:	4b45      	ldr	r3, [pc, #276]	; (80053e8 <xTaskIncrementTick+0x164>)
 80052d4:	681b      	ldr	r3, [r3, #0]
 80052d6:	4a43      	ldr	r2, [pc, #268]	; (80053e4 <xTaskIncrementTick+0x160>)
 80052d8:	6013      	str	r3, [r2, #0]
 80052da:	4a43      	ldr	r2, [pc, #268]	; (80053e8 <xTaskIncrementTick+0x164>)
 80052dc:	68fb      	ldr	r3, [r7, #12]
 80052de:	6013      	str	r3, [r2, #0]
 80052e0:	4b42      	ldr	r3, [pc, #264]	; (80053ec <xTaskIncrementTick+0x168>)
 80052e2:	681b      	ldr	r3, [r3, #0]
 80052e4:	3301      	adds	r3, #1
 80052e6:	4a41      	ldr	r2, [pc, #260]	; (80053ec <xTaskIncrementTick+0x168>)
 80052e8:	6013      	str	r3, [r2, #0]
 80052ea:	f000 fae5 	bl	80058b8 <prvResetNextTaskUnblockTime>

		/* See if this tick has made a timeout expire.  Tasks are stored in
		the	queue in the order of their wake time - meaning once one task
		has been found whose block time has not expired there is no need to
		look any further down the list. */
		if( xConstTickCount >= xNextTaskUnblockTime )
 80052ee:	4b40      	ldr	r3, [pc, #256]	; (80053f0 <xTaskIncrementTick+0x16c>)
 80052f0:	681b      	ldr	r3, [r3, #0]
 80052f2:	693a      	ldr	r2, [r7, #16]
 80052f4:	429a      	cmp	r2, r3
 80052f6:	d349      	bcc.n	800538c <xTaskIncrementTick+0x108>
		{
			for( ;; )
			{
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 80052f8:	4b3a      	ldr	r3, [pc, #232]	; (80053e4 <xTaskIncrementTick+0x160>)
 80052fa:	681b      	ldr	r3, [r3, #0]
 80052fc:	681b      	ldr	r3, [r3, #0]
 80052fe:	2b00      	cmp	r3, #0
 8005300:	d104      	bne.n	800530c <xTaskIncrementTick+0x88>
					/* The delayed list is empty.  Set xNextTaskUnblockTime
					to the maximum possible value so it is extremely
					unlikely that the
					if( xTickCount >= xNextTaskUnblockTime ) test will pass
					next time through. */
					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8005302:	4b3b      	ldr	r3, [pc, #236]	; (80053f0 <xTaskIncrementTick+0x16c>)
 8005304:	f04f 32ff 	mov.w	r2, #4294967295
 8005308:	601a      	str	r2, [r3, #0]
					break;
 800530a:	e03f      	b.n	800538c <xTaskIncrementTick+0x108>
				{
					/* The delayed list is not empty, get the value of the
					item at the head of the delayed list.  This is the time
					at which the task at the head of the delayed list must
					be removed from the Blocked state. */
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 800530c:	4b35      	ldr	r3, [pc, #212]	; (80053e4 <xTaskIncrementTick+0x160>)
 800530e:	681b      	ldr	r3, [r3, #0]
 8005310:	68db      	ldr	r3, [r3, #12]
 8005312:	68db      	ldr	r3, [r3, #12]
 8005314:	60bb      	str	r3, [r7, #8]
					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
 8005316:	68bb      	ldr	r3, [r7, #8]
 8005318:	685b      	ldr	r3, [r3, #4]
 800531a:	607b      	str	r3, [r7, #4]

					if( xConstTickCount < xItemValue )
 800531c:	693a      	ldr	r2, [r7, #16]
 800531e:	687b      	ldr	r3, [r7, #4]
 8005320:	429a      	cmp	r2, r3
 8005322:	d203      	bcs.n	800532c <xTaskIncrementTick+0xa8>
						/* It is not time to unblock this item yet, but the
						item value is the time at which the task at the head
						of the blocked list must be removed from the Blocked
						state -	so record the item value in
						xNextTaskUnblockTime. */
						xNextTaskUnblockTime = xItemValue;
 8005324:	4a32      	ldr	r2, [pc, #200]	; (80053f0 <xTaskIncrementTick+0x16c>)
 8005326:	687b      	ldr	r3, [r7, #4]
 8005328:	6013      	str	r3, [r2, #0]
						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
 800532a:	e02f      	b.n	800538c <xTaskIncrementTick+0x108>
					{
						mtCOVERAGE_TEST_MARKER();
					}

					/* It is time to remove the item from the Blocked state. */
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 800532c:	68bb      	ldr	r3, [r7, #8]
 800532e:	3304      	adds	r3, #4
 8005330:	4618      	mov	r0, r3
 8005332:	f7fe ff79 	bl	8004228 <uxListRemove>

					/* Is the task waiting on an event also?  If so remove
					it from the event list. */
					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
 8005336:	68bb      	ldr	r3, [r7, #8]
 8005338:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800533a:	2b00      	cmp	r3, #0
 800533c:	d004      	beq.n	8005348 <xTaskIncrementTick+0xc4>
					{
						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 800533e:	68bb      	ldr	r3, [r7, #8]
 8005340:	3318      	adds	r3, #24
 8005342:	4618      	mov	r0, r3
 8005344:	f7fe ff70 	bl	8004228 <uxListRemove>
						mtCOVERAGE_TEST_MARKER();
					}

					/* Place the unblocked task into the appropriate ready
					list. */
					prvAddTaskToReadyList( pxTCB );
 8005348:	68bb      	ldr	r3, [r7, #8]
 800534a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 800534c:	4b29      	ldr	r3, [pc, #164]	; (80053f4 <xTaskIncrementTick+0x170>)
 800534e:	681b      	ldr	r3, [r3, #0]
 8005350:	429a      	cmp	r2, r3
 8005352:	d903      	bls.n	800535c <xTaskIncrementTick+0xd8>
 8005354:	68bb      	ldr	r3, [r7, #8]
 8005356:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8005358:	4a26      	ldr	r2, [pc, #152]	; (80053f4 <xTaskIncrementTick+0x170>)
 800535a:	6013      	str	r3, [r2, #0]
 800535c:	68bb      	ldr	r3, [r7, #8]
 800535e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8005360:	4613      	mov	r3, r2
 8005362:	009b      	lsls	r3, r3, #2
 8005364:	4413      	add	r3, r2
 8005366:	009b      	lsls	r3, r3, #2
 8005368:	4a23      	ldr	r2, [pc, #140]	; (80053f8 <xTaskIncrementTick+0x174>)
 800536a:	441a      	add	r2, r3
 800536c:	68bb      	ldr	r3, [r7, #8]
 800536e:	3304      	adds	r3, #4
 8005370:	4619      	mov	r1, r3
 8005372:	4610      	mov	r0, r2
 8005374:	f7fe fefb 	bl	800416e <vListInsertEnd>
					{
						/* Preemption is on, but a context switch should
						only be performed if the unblocked task has a
						priority that is equal to or higher than the
						currently executing task. */
						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 8005378:	68bb      	ldr	r3, [r7, #8]
 800537a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 800537c:	4b1f      	ldr	r3, [pc, #124]	; (80053fc <xTaskIncrementTick+0x178>)
 800537e:	681b      	ldr	r3, [r3, #0]
 8005380:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8005382:	429a      	cmp	r2, r3
 8005384:	d3b8      	bcc.n	80052f8 <xTaskIncrementTick+0x74>
						{
							xSwitchRequired = pdTRUE;
 8005386:	2301      	movs	r3, #1
 8005388:	617b      	str	r3, [r7, #20]
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 800538a:	e7b5      	b.n	80052f8 <xTaskIncrementTick+0x74>
		/* Tasks of equal priority to the currently running task will share
		processing time (time slice) if preemption is on, and the application
		writer has not explicitly turned time slicing off. */
		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
		{
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
 800538c:	4b1b      	ldr	r3, [pc, #108]	; (80053fc <xTaskIncrementTick+0x178>)
 800538e:	681b      	ldr	r3, [r3, #0]
 8005390:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8005392:	4919      	ldr	r1, [pc, #100]	; (80053f8 <xTaskIncrementTick+0x174>)
 8005394:	4613      	mov	r3, r2
 8005396:	009b      	lsls	r3, r3, #2
 8005398:	4413      	add	r3, r2
 800539a:	009b      	lsls	r3, r3, #2
 800539c:	440b      	add	r3, r1
 800539e:	681b      	ldr	r3, [r3, #0]
 80053a0:	2b01      	cmp	r3, #1
 80053a2:	d901      	bls.n	80053a8 <xTaskIncrementTick+0x124>
			{
				xSwitchRequired = pdTRUE;
 80053a4:	2301      	movs	r3, #1
 80053a6:	617b      	str	r3, [r7, #20]

		#if ( configUSE_TICK_HOOK == 1 )
		{
			/* Guard against the tick hook being called when the pended tick
			count is being unwound (when the scheduler is being unlocked). */
			if( xPendedTicks == ( TickType_t ) 0 )
 80053a8:	4b15      	ldr	r3, [pc, #84]	; (8005400 <xTaskIncrementTick+0x17c>)
 80053aa:	681b      	ldr	r3, [r3, #0]
 80053ac:	2b00      	cmp	r3, #0
 80053ae:	d101      	bne.n	80053b4 <xTaskIncrementTick+0x130>
			{
				vApplicationTickHook();
 80053b0:	f7fb f8bd 	bl	800052e <vApplicationTickHook>
		}
		#endif /* configUSE_TICK_HOOK */

		#if ( configUSE_PREEMPTION == 1 )
		{
			if( xYieldPending != pdFALSE )
 80053b4:	4b13      	ldr	r3, [pc, #76]	; (8005404 <xTaskIncrementTick+0x180>)
 80053b6:	681b      	ldr	r3, [r3, #0]
 80053b8:	2b00      	cmp	r3, #0
 80053ba:	d009      	beq.n	80053d0 <xTaskIncrementTick+0x14c>
			{
				xSwitchRequired = pdTRUE;
 80053bc:	2301      	movs	r3, #1
 80053be:	617b      	str	r3, [r7, #20]
 80053c0:	e006      	b.n	80053d0 <xTaskIncrementTick+0x14c>
		}
		#endif /* configUSE_PREEMPTION */
	}
	else
	{
		++xPendedTicks;
 80053c2:	4b0f      	ldr	r3, [pc, #60]	; (8005400 <xTaskIncrementTick+0x17c>)
 80053c4:	681b      	ldr	r3, [r3, #0]
 80053c6:	3301      	adds	r3, #1
 80053c8:	4a0d      	ldr	r2, [pc, #52]	; (8005400 <xTaskIncrementTick+0x17c>)
 80053ca:	6013      	str	r3, [r2, #0]

		/* The tick hook gets called at regular intervals, even if the
		scheduler is locked. */
		#if ( configUSE_TICK_HOOK == 1 )
		{
			vApplicationTickHook();
 80053cc:	f7fb f8af 	bl	800052e <vApplicationTickHook>
		}
		#endif
	}

	return xSwitchRequired;
 80053d0:	697b      	ldr	r3, [r7, #20]
}
 80053d2:	4618      	mov	r0, r3
 80053d4:	3718      	adds	r7, #24
 80053d6:	46bd      	mov	sp, r7
 80053d8:	bd80      	pop	{r7, pc}
 80053da:	bf00      	nop
 80053dc:	20003dd8 	.word	0x20003dd8
 80053e0:	20003db4 	.word	0x20003db4
 80053e4:	20003d68 	.word	0x20003d68
 80053e8:	20003d6c 	.word	0x20003d6c
 80053ec:	20003dc8 	.word	0x20003dc8
 80053f0:	20003dd0 	.word	0x20003dd0
 80053f4:	20003db8 	.word	0x20003db8
 80053f8:	200038e0 	.word	0x200038e0
 80053fc:	200038dc 	.word	0x200038dc
 8005400:	20003dc0 	.word	0x20003dc0
 8005404:	20003dc4 	.word	0x20003dc4

08005408 <vTaskSwitchContext>:

#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/

void vTaskSwitchContext( void )
{
 8005408:	b480      	push	{r7}
 800540a:	b085      	sub	sp, #20
 800540c:	af00      	add	r7, sp, #0
	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
 800540e:	4b2a      	ldr	r3, [pc, #168]	; (80054b8 <vTaskSwitchContext+0xb0>)
 8005410:	681b      	ldr	r3, [r3, #0]
 8005412:	2b00      	cmp	r3, #0
 8005414:	d003      	beq.n	800541e <vTaskSwitchContext+0x16>
	{
		/* The scheduler is currently suspended - do not allow a context
		switch. */
		xYieldPending = pdTRUE;
 8005416:	4b29      	ldr	r3, [pc, #164]	; (80054bc <vTaskSwitchContext+0xb4>)
 8005418:	2201      	movs	r2, #1
 800541a:	601a      	str	r2, [r3, #0]
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
		}
		#endif /* configUSE_NEWLIB_REENTRANT */
	}
}
 800541c:	e046      	b.n	80054ac <vTaskSwitchContext+0xa4>
		xYieldPending = pdFALSE;
 800541e:	4b27      	ldr	r3, [pc, #156]	; (80054bc <vTaskSwitchContext+0xb4>)
 8005420:	2200      	movs	r2, #0
 8005422:	601a      	str	r2, [r3, #0]
		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8005424:	4b26      	ldr	r3, [pc, #152]	; (80054c0 <vTaskSwitchContext+0xb8>)
 8005426:	681b      	ldr	r3, [r3, #0]
 8005428:	60fb      	str	r3, [r7, #12]
 800542a:	e010      	b.n	800544e <vTaskSwitchContext+0x46>
 800542c:	68fb      	ldr	r3, [r7, #12]
 800542e:	2b00      	cmp	r3, #0
 8005430:	d10a      	bne.n	8005448 <vTaskSwitchContext+0x40>
	__asm volatile
 8005432:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005436:	f383 8811 	msr	BASEPRI, r3
 800543a:	f3bf 8f6f 	isb	sy
 800543e:	f3bf 8f4f 	dsb	sy
 8005442:	607b      	str	r3, [r7, #4]
}
 8005444:	bf00      	nop
 8005446:	e7fe      	b.n	8005446 <vTaskSwitchContext+0x3e>
 8005448:	68fb      	ldr	r3, [r7, #12]
 800544a:	3b01      	subs	r3, #1
 800544c:	60fb      	str	r3, [r7, #12]
 800544e:	491d      	ldr	r1, [pc, #116]	; (80054c4 <vTaskSwitchContext+0xbc>)
 8005450:	68fa      	ldr	r2, [r7, #12]
 8005452:	4613      	mov	r3, r2
 8005454:	009b      	lsls	r3, r3, #2
 8005456:	4413      	add	r3, r2
 8005458:	009b      	lsls	r3, r3, #2
 800545a:	440b      	add	r3, r1
 800545c:	681b      	ldr	r3, [r3, #0]
 800545e:	2b00      	cmp	r3, #0
 8005460:	d0e4      	beq.n	800542c <vTaskSwitchContext+0x24>
 8005462:	68fa      	ldr	r2, [r7, #12]
 8005464:	4613      	mov	r3, r2
 8005466:	009b      	lsls	r3, r3, #2
 8005468:	4413      	add	r3, r2
 800546a:	009b      	lsls	r3, r3, #2
 800546c:	4a15      	ldr	r2, [pc, #84]	; (80054c4 <vTaskSwitchContext+0xbc>)
 800546e:	4413      	add	r3, r2
 8005470:	60bb      	str	r3, [r7, #8]
 8005472:	68bb      	ldr	r3, [r7, #8]
 8005474:	685b      	ldr	r3, [r3, #4]
 8005476:	685a      	ldr	r2, [r3, #4]
 8005478:	68bb      	ldr	r3, [r7, #8]
 800547a:	605a      	str	r2, [r3, #4]
 800547c:	68bb      	ldr	r3, [r7, #8]
 800547e:	685a      	ldr	r2, [r3, #4]
 8005480:	68bb      	ldr	r3, [r7, #8]
 8005482:	3308      	adds	r3, #8
 8005484:	429a      	cmp	r2, r3
 8005486:	d104      	bne.n	8005492 <vTaskSwitchContext+0x8a>
 8005488:	68bb      	ldr	r3, [r7, #8]
 800548a:	685b      	ldr	r3, [r3, #4]
 800548c:	685a      	ldr	r2, [r3, #4]
 800548e:	68bb      	ldr	r3, [r7, #8]
 8005490:	605a      	str	r2, [r3, #4]
 8005492:	68bb      	ldr	r3, [r7, #8]
 8005494:	685b      	ldr	r3, [r3, #4]
 8005496:	68db      	ldr	r3, [r3, #12]
 8005498:	4a0b      	ldr	r2, [pc, #44]	; (80054c8 <vTaskSwitchContext+0xc0>)
 800549a:	6013      	str	r3, [r2, #0]
 800549c:	4a08      	ldr	r2, [pc, #32]	; (80054c0 <vTaskSwitchContext+0xb8>)
 800549e:	68fb      	ldr	r3, [r7, #12]
 80054a0:	6013      	str	r3, [r2, #0]
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 80054a2:	4b09      	ldr	r3, [pc, #36]	; (80054c8 <vTaskSwitchContext+0xc0>)
 80054a4:	681b      	ldr	r3, [r3, #0]
 80054a6:	3354      	adds	r3, #84	; 0x54
 80054a8:	4a08      	ldr	r2, [pc, #32]	; (80054cc <vTaskSwitchContext+0xc4>)
 80054aa:	6013      	str	r3, [r2, #0]
}
 80054ac:	bf00      	nop
 80054ae:	3714      	adds	r7, #20
 80054b0:	46bd      	mov	sp, r7
 80054b2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80054b6:	4770      	bx	lr
 80054b8:	20003dd8 	.word	0x20003dd8
 80054bc:	20003dc4 	.word	0x20003dc4
 80054c0:	20003db8 	.word	0x20003db8
 80054c4:	200038e0 	.word	0x200038e0
 80054c8:	200038dc 	.word	0x200038dc
 80054cc:	20000020 	.word	0x20000020

080054d0 <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/

void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
 80054d0:	b580      	push	{r7, lr}
 80054d2:	b084      	sub	sp, #16
 80054d4:	af00      	add	r7, sp, #0
 80054d6:	6078      	str	r0, [r7, #4]
 80054d8:	6039      	str	r1, [r7, #0]
	configASSERT( pxEventList );
 80054da:	687b      	ldr	r3, [r7, #4]
 80054dc:	2b00      	cmp	r3, #0
 80054de:	d10a      	bne.n	80054f6 <vTaskPlaceOnEventList+0x26>
	__asm volatile
 80054e0:	f04f 0350 	mov.w	r3, #80	; 0x50
 80054e4:	f383 8811 	msr	BASEPRI, r3
 80054e8:	f3bf 8f6f 	isb	sy
 80054ec:	f3bf 8f4f 	dsb	sy
 80054f0:	60fb      	str	r3, [r7, #12]
}
 80054f2:	bf00      	nop
 80054f4:	e7fe      	b.n	80054f4 <vTaskPlaceOnEventList+0x24>

	/* Place the event list item of the TCB in the appropriate event list.
	This is placed in the list in priority order so the highest priority task
	is the first to be woken by the event.  The queue that contains the event
	list is locked, preventing simultaneous access from interrupts. */
	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 80054f6:	4b07      	ldr	r3, [pc, #28]	; (8005514 <vTaskPlaceOnEventList+0x44>)
 80054f8:	681b      	ldr	r3, [r3, #0]
 80054fa:	3318      	adds	r3, #24
 80054fc:	4619      	mov	r1, r3
 80054fe:	6878      	ldr	r0, [r7, #4]
 8005500:	f7fe fe59 	bl	80041b6 <vListInsert>

	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
 8005504:	2101      	movs	r1, #1
 8005506:	6838      	ldr	r0, [r7, #0]
 8005508:	f000 fa82 	bl	8005a10 <prvAddCurrentTaskToDelayedList>
}
 800550c:	bf00      	nop
 800550e:	3710      	adds	r7, #16
 8005510:	46bd      	mov	sp, r7
 8005512:	bd80      	pop	{r7, pc}
 8005514:	200038dc 	.word	0x200038dc

08005518 <vTaskPlaceOnEventListRestricted>:
/*-----------------------------------------------------------*/

#if( configUSE_TIMERS == 1 )

	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 8005518:	b580      	push	{r7, lr}
 800551a:	b086      	sub	sp, #24
 800551c:	af00      	add	r7, sp, #0
 800551e:	60f8      	str	r0, [r7, #12]
 8005520:	60b9      	str	r1, [r7, #8]
 8005522:	607a      	str	r2, [r7, #4]
		configASSERT( pxEventList );
 8005524:	68fb      	ldr	r3, [r7, #12]
 8005526:	2b00      	cmp	r3, #0
 8005528:	d10a      	bne.n	8005540 <vTaskPlaceOnEventListRestricted+0x28>
	__asm volatile
 800552a:	f04f 0350 	mov.w	r3, #80	; 0x50
 800552e:	f383 8811 	msr	BASEPRI, r3
 8005532:	f3bf 8f6f 	isb	sy
 8005536:	f3bf 8f4f 	dsb	sy
 800553a:	617b      	str	r3, [r7, #20]
}
 800553c:	bf00      	nop
 800553e:	e7fe      	b.n	800553e <vTaskPlaceOnEventListRestricted+0x26>

		/* Place the event list item of the TCB in the appropriate event list.
		In this case it is assume that this is the only task that is going to
		be waiting on this event list, so the faster vListInsertEnd() function
		can be used in place of vListInsert. */
		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 8005540:	4b0a      	ldr	r3, [pc, #40]	; (800556c <vTaskPlaceOnEventListRestricted+0x54>)
 8005542:	681b      	ldr	r3, [r3, #0]
 8005544:	3318      	adds	r3, #24
 8005546:	4619      	mov	r1, r3
 8005548:	68f8      	ldr	r0, [r7, #12]
 800554a:	f7fe fe10 	bl	800416e <vListInsertEnd>

		/* If the task should block indefinitely then set the block time to a
		value that will be recognised as an indefinite delay inside the
		prvAddCurrentTaskToDelayedList() function. */
		if( xWaitIndefinitely != pdFALSE )
 800554e:	687b      	ldr	r3, [r7, #4]
 8005550:	2b00      	cmp	r3, #0
 8005552:	d002      	beq.n	800555a <vTaskPlaceOnEventListRestricted+0x42>
		{
			xTicksToWait = portMAX_DELAY;
 8005554:	f04f 33ff 	mov.w	r3, #4294967295
 8005558:	60bb      	str	r3, [r7, #8]
		}

		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
 800555a:	6879      	ldr	r1, [r7, #4]
 800555c:	68b8      	ldr	r0, [r7, #8]
 800555e:	f000 fa57 	bl	8005a10 <prvAddCurrentTaskToDelayedList>
	}
 8005562:	bf00      	nop
 8005564:	3718      	adds	r7, #24
 8005566:	46bd      	mov	sp, r7
 8005568:	bd80      	pop	{r7, pc}
 800556a:	bf00      	nop
 800556c:	200038dc 	.word	0x200038dc

08005570 <xTaskRemoveFromEventList>:

#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/

BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
 8005570:	b580      	push	{r7, lr}
 8005572:	b086      	sub	sp, #24
 8005574:	af00      	add	r7, sp, #0
 8005576:	6078      	str	r0, [r7, #4]
	get called - the lock count on the queue will get modified instead.  This
	means exclusive access to the event list is guaranteed here.

	This function assumes that a check has already been made to ensure that
	pxEventList is not empty. */
	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8005578:	687b      	ldr	r3, [r7, #4]
 800557a:	68db      	ldr	r3, [r3, #12]
 800557c:	68db      	ldr	r3, [r3, #12]
 800557e:	613b      	str	r3, [r7, #16]
	configASSERT( pxUnblockedTCB );
 8005580:	693b      	ldr	r3, [r7, #16]
 8005582:	2b00      	cmp	r3, #0
 8005584:	d10a      	bne.n	800559c <xTaskRemoveFromEventList+0x2c>
	__asm volatile
 8005586:	f04f 0350 	mov.w	r3, #80	; 0x50
 800558a:	f383 8811 	msr	BASEPRI, r3
 800558e:	f3bf 8f6f 	isb	sy
 8005592:	f3bf 8f4f 	dsb	sy
 8005596:	60fb      	str	r3, [r7, #12]
}
 8005598:	bf00      	nop
 800559a:	e7fe      	b.n	800559a <xTaskRemoveFromEventList+0x2a>
	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
 800559c:	693b      	ldr	r3, [r7, #16]
 800559e:	3318      	adds	r3, #24
 80055a0:	4618      	mov	r0, r3
 80055a2:	f7fe fe41 	bl	8004228 <uxListRemove>

	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 80055a6:	4b1e      	ldr	r3, [pc, #120]	; (8005620 <xTaskRemoveFromEventList+0xb0>)
 80055a8:	681b      	ldr	r3, [r3, #0]
 80055aa:	2b00      	cmp	r3, #0
 80055ac:	d11d      	bne.n	80055ea <xTaskRemoveFromEventList+0x7a>
	{
		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
 80055ae:	693b      	ldr	r3, [r7, #16]
 80055b0:	3304      	adds	r3, #4
 80055b2:	4618      	mov	r0, r3
 80055b4:	f7fe fe38 	bl	8004228 <uxListRemove>
		prvAddTaskToReadyList( pxUnblockedTCB );
 80055b8:	693b      	ldr	r3, [r7, #16]
 80055ba:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 80055bc:	4b19      	ldr	r3, [pc, #100]	; (8005624 <xTaskRemoveFromEventList+0xb4>)
 80055be:	681b      	ldr	r3, [r3, #0]
 80055c0:	429a      	cmp	r2, r3
 80055c2:	d903      	bls.n	80055cc <xTaskRemoveFromEventList+0x5c>
 80055c4:	693b      	ldr	r3, [r7, #16]
 80055c6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80055c8:	4a16      	ldr	r2, [pc, #88]	; (8005624 <xTaskRemoveFromEventList+0xb4>)
 80055ca:	6013      	str	r3, [r2, #0]
 80055cc:	693b      	ldr	r3, [r7, #16]
 80055ce:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 80055d0:	4613      	mov	r3, r2
 80055d2:	009b      	lsls	r3, r3, #2
 80055d4:	4413      	add	r3, r2
 80055d6:	009b      	lsls	r3, r3, #2
 80055d8:	4a13      	ldr	r2, [pc, #76]	; (8005628 <xTaskRemoveFromEventList+0xb8>)
 80055da:	441a      	add	r2, r3
 80055dc:	693b      	ldr	r3, [r7, #16]
 80055de:	3304      	adds	r3, #4
 80055e0:	4619      	mov	r1, r3
 80055e2:	4610      	mov	r0, r2
 80055e4:	f7fe fdc3 	bl	800416e <vListInsertEnd>
 80055e8:	e005      	b.n	80055f6 <xTaskRemoveFromEventList+0x86>
	}
	else
	{
		/* The delayed and ready lists cannot be accessed, so hold this task
		pending until the scheduler is resumed. */
		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
 80055ea:	693b      	ldr	r3, [r7, #16]
 80055ec:	3318      	adds	r3, #24
 80055ee:	4619      	mov	r1, r3
 80055f0:	480e      	ldr	r0, [pc, #56]	; (800562c <xTaskRemoveFromEventList+0xbc>)
 80055f2:	f7fe fdbc 	bl	800416e <vListInsertEnd>
	}

	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
 80055f6:	693b      	ldr	r3, [r7, #16]
 80055f8:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 80055fa:	4b0d      	ldr	r3, [pc, #52]	; (8005630 <xTaskRemoveFromEventList+0xc0>)
 80055fc:	681b      	ldr	r3, [r3, #0]
 80055fe:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8005600:	429a      	cmp	r2, r3
 8005602:	d905      	bls.n	8005610 <xTaskRemoveFromEventList+0xa0>
	{
		/* Return true if the task removed from the event list has a higher
		priority than the calling task.  This allows the calling task to know if
		it should force a context switch now. */
		xReturn = pdTRUE;
 8005604:	2301      	movs	r3, #1
 8005606:	617b      	str	r3, [r7, #20]

		/* Mark that a yield is pending in case the user is not using the
		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
		xYieldPending = pdTRUE;
 8005608:	4b0a      	ldr	r3, [pc, #40]	; (8005634 <xTaskRemoveFromEventList+0xc4>)
 800560a:	2201      	movs	r2, #1
 800560c:	601a      	str	r2, [r3, #0]
 800560e:	e001      	b.n	8005614 <xTaskRemoveFromEventList+0xa4>
	}
	else
	{
		xReturn = pdFALSE;
 8005610:	2300      	movs	r3, #0
 8005612:	617b      	str	r3, [r7, #20]
	}

	return xReturn;
 8005614:	697b      	ldr	r3, [r7, #20]
}
 8005616:	4618      	mov	r0, r3
 8005618:	3718      	adds	r7, #24
 800561a:	46bd      	mov	sp, r7
 800561c:	bd80      	pop	{r7, pc}
 800561e:	bf00      	nop
 8005620:	20003dd8 	.word	0x20003dd8
 8005624:	20003db8 	.word	0x20003db8
 8005628:	200038e0 	.word	0x200038e0
 800562c:	20003d70 	.word	0x20003d70
 8005630:	200038dc 	.word	0x200038dc
 8005634:	20003dc4 	.word	0x20003dc4

08005638 <vTaskInternalSetTimeOutState>:
	taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/

void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
 8005638:	b480      	push	{r7}
 800563a:	b083      	sub	sp, #12
 800563c:	af00      	add	r7, sp, #0
 800563e:	6078      	str	r0, [r7, #4]
	/* For internal use only as it does not use a critical section. */
	pxTimeOut->xOverflowCount = xNumOfOverflows;
 8005640:	4b06      	ldr	r3, [pc, #24]	; (800565c <vTaskInternalSetTimeOutState+0x24>)
 8005642:	681a      	ldr	r2, [r3, #0]
 8005644:	687b      	ldr	r3, [r7, #4]
 8005646:	601a      	str	r2, [r3, #0]
	pxTimeOut->xTimeOnEntering = xTickCount;
 8005648:	4b05      	ldr	r3, [pc, #20]	; (8005660 <vTaskInternalSetTimeOutState+0x28>)
 800564a:	681a      	ldr	r2, [r3, #0]
 800564c:	687b      	ldr	r3, [r7, #4]
 800564e:	605a      	str	r2, [r3, #4]
}
 8005650:	bf00      	nop
 8005652:	370c      	adds	r7, #12
 8005654:	46bd      	mov	sp, r7
 8005656:	f85d 7b04 	ldr.w	r7, [sp], #4
 800565a:	4770      	bx	lr
 800565c:	20003dc8 	.word	0x20003dc8
 8005660:	20003db4 	.word	0x20003db4

08005664 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/

BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
 8005664:	b580      	push	{r7, lr}
 8005666:	b088      	sub	sp, #32
 8005668:	af00      	add	r7, sp, #0
 800566a:	6078      	str	r0, [r7, #4]
 800566c:	6039      	str	r1, [r7, #0]
BaseType_t xReturn;

	configASSERT( pxTimeOut );
 800566e:	687b      	ldr	r3, [r7, #4]
 8005670:	2b00      	cmp	r3, #0
 8005672:	d10a      	bne.n	800568a <xTaskCheckForTimeOut+0x26>
	__asm volatile
 8005674:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005678:	f383 8811 	msr	BASEPRI, r3
 800567c:	f3bf 8f6f 	isb	sy
 8005680:	f3bf 8f4f 	dsb	sy
 8005684:	613b      	str	r3, [r7, #16]
}
 8005686:	bf00      	nop
 8005688:	e7fe      	b.n	8005688 <xTaskCheckForTimeOut+0x24>
	configASSERT( pxTicksToWait );
 800568a:	683b      	ldr	r3, [r7, #0]
 800568c:	2b00      	cmp	r3, #0
 800568e:	d10a      	bne.n	80056a6 <xTaskCheckForTimeOut+0x42>
	__asm volatile
 8005690:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005694:	f383 8811 	msr	BASEPRI, r3
 8005698:	f3bf 8f6f 	isb	sy
 800569c:	f3bf 8f4f 	dsb	sy
 80056a0:	60fb      	str	r3, [r7, #12]
}
 80056a2:	bf00      	nop
 80056a4:	e7fe      	b.n	80056a4 <xTaskCheckForTimeOut+0x40>

	taskENTER_CRITICAL();
 80056a6:	f000 fe85 	bl	80063b4 <vPortEnterCritical>
	{
		/* Minor optimisation.  The tick count cannot change in this block. */
		const TickType_t xConstTickCount = xTickCount;
 80056aa:	4b1d      	ldr	r3, [pc, #116]	; (8005720 <xTaskCheckForTimeOut+0xbc>)
 80056ac:	681b      	ldr	r3, [r3, #0]
 80056ae:	61bb      	str	r3, [r7, #24]
		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
 80056b0:	687b      	ldr	r3, [r7, #4]
 80056b2:	685b      	ldr	r3, [r3, #4]
 80056b4:	69ba      	ldr	r2, [r7, #24]
 80056b6:	1ad3      	subs	r3, r2, r3
 80056b8:	617b      	str	r3, [r7, #20]
			}
			else
		#endif

		#if ( INCLUDE_vTaskSuspend == 1 )
			if( *pxTicksToWait == portMAX_DELAY )
 80056ba:	683b      	ldr	r3, [r7, #0]
 80056bc:	681b      	ldr	r3, [r3, #0]
 80056be:	f1b3 3fff 	cmp.w	r3, #4294967295
 80056c2:	d102      	bne.n	80056ca <xTaskCheckForTimeOut+0x66>
			{
				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
				specified is the maximum block time then the task should block
				indefinitely, and therefore never time out. */
				xReturn = pdFALSE;
 80056c4:	2300      	movs	r3, #0
 80056c6:	61fb      	str	r3, [r7, #28]
 80056c8:	e023      	b.n	8005712 <xTaskCheckForTimeOut+0xae>
			}
			else
		#endif

		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
 80056ca:	687b      	ldr	r3, [r7, #4]
 80056cc:	681a      	ldr	r2, [r3, #0]
 80056ce:	4b15      	ldr	r3, [pc, #84]	; (8005724 <xTaskCheckForTimeOut+0xc0>)
 80056d0:	681b      	ldr	r3, [r3, #0]
 80056d2:	429a      	cmp	r2, r3
 80056d4:	d007      	beq.n	80056e6 <xTaskCheckForTimeOut+0x82>
 80056d6:	687b      	ldr	r3, [r7, #4]
 80056d8:	685b      	ldr	r3, [r3, #4]
 80056da:	69ba      	ldr	r2, [r7, #24]
 80056dc:	429a      	cmp	r2, r3
 80056de:	d302      	bcc.n	80056e6 <xTaskCheckForTimeOut+0x82>
			/* The tick count is greater than the time at which
			vTaskSetTimeout() was called, but has also overflowed since
			vTaskSetTimeOut() was called.  It must have wrapped all the way
			around and gone past again. This passed since vTaskSetTimeout()
			was called. */
			xReturn = pdTRUE;
 80056e0:	2301      	movs	r3, #1
 80056e2:	61fb      	str	r3, [r7, #28]
 80056e4:	e015      	b.n	8005712 <xTaskCheckForTimeOut+0xae>
		}
		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
 80056e6:	683b      	ldr	r3, [r7, #0]
 80056e8:	681b      	ldr	r3, [r3, #0]
 80056ea:	697a      	ldr	r2, [r7, #20]
 80056ec:	429a      	cmp	r2, r3
 80056ee:	d20b      	bcs.n	8005708 <xTaskCheckForTimeOut+0xa4>
		{
			/* Not a genuine timeout. Adjust parameters for time remaining. */
			*pxTicksToWait -= xElapsedTime;
 80056f0:	683b      	ldr	r3, [r7, #0]
 80056f2:	681a      	ldr	r2, [r3, #0]
 80056f4:	697b      	ldr	r3, [r7, #20]
 80056f6:	1ad2      	subs	r2, r2, r3
 80056f8:	683b      	ldr	r3, [r7, #0]
 80056fa:	601a      	str	r2, [r3, #0]
			vTaskInternalSetTimeOutState( pxTimeOut );
 80056fc:	6878      	ldr	r0, [r7, #4]
 80056fe:	f7ff ff9b 	bl	8005638 <vTaskInternalSetTimeOutState>
			xReturn = pdFALSE;
 8005702:	2300      	movs	r3, #0
 8005704:	61fb      	str	r3, [r7, #28]
 8005706:	e004      	b.n	8005712 <xTaskCheckForTimeOut+0xae>
		}
		else
		{
			*pxTicksToWait = 0;
 8005708:	683b      	ldr	r3, [r7, #0]
 800570a:	2200      	movs	r2, #0
 800570c:	601a      	str	r2, [r3, #0]
			xReturn = pdTRUE;
 800570e:	2301      	movs	r3, #1
 8005710:	61fb      	str	r3, [r7, #28]
		}
	}
	taskEXIT_CRITICAL();
 8005712:	f000 fe7f 	bl	8006414 <vPortExitCritical>

	return xReturn;
 8005716:	69fb      	ldr	r3, [r7, #28]
}
 8005718:	4618      	mov	r0, r3
 800571a:	3720      	adds	r7, #32
 800571c:	46bd      	mov	sp, r7
 800571e:	bd80      	pop	{r7, pc}
 8005720:	20003db4 	.word	0x20003db4
 8005724:	20003dc8 	.word	0x20003dc8

08005728 <vTaskMissedYield>:
/*-----------------------------------------------------------*/

void vTaskMissedYield( void )
{
 8005728:	b480      	push	{r7}
 800572a:	af00      	add	r7, sp, #0
	xYieldPending = pdTRUE;
 800572c:	4b03      	ldr	r3, [pc, #12]	; (800573c <vTaskMissedYield+0x14>)
 800572e:	2201      	movs	r2, #1
 8005730:	601a      	str	r2, [r3, #0]
}
 8005732:	bf00      	nop
 8005734:	46bd      	mov	sp, r7
 8005736:	f85d 7b04 	ldr.w	r7, [sp], #4
 800573a:	4770      	bx	lr
 800573c:	20003dc4 	.word	0x20003dc4

08005740 <prvIdleTask>:
 *
 * void prvIdleTask( void *pvParameters );
 *
 */
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
 8005740:	b580      	push	{r7, lr}
 8005742:	b082      	sub	sp, #8
 8005744:	af00      	add	r7, sp, #0
 8005746:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* See if any tasks have deleted themselves - if so then the idle task
		is responsible for freeing the deleted task's TCB and stack. */
		prvCheckTasksWaitingTermination();
 8005748:	f000 f854 	bl	80057f4 <prvCheckTasksWaitingTermination>

			A critical region is not required here as we are just reading from
			the list, and an occasional incorrect value will not matter.  If
			the ready list at the idle priority contains more than one task
			then a task other than the idle task is ready to execute. */
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
 800574c:	4b07      	ldr	r3, [pc, #28]	; (800576c <prvIdleTask+0x2c>)
 800574e:	681b      	ldr	r3, [r3, #0]
 8005750:	2b01      	cmp	r3, #1
 8005752:	d907      	bls.n	8005764 <prvIdleTask+0x24>
			{
				taskYIELD();
 8005754:	4b06      	ldr	r3, [pc, #24]	; (8005770 <prvIdleTask+0x30>)
 8005756:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 800575a:	601a      	str	r2, [r3, #0]
 800575c:	f3bf 8f4f 	dsb	sy
 8005760:	f3bf 8f6f 	isb	sy
			/* Call the user defined function from within the idle task.  This
			allows the application designer to add background functionality
			without the overhead of a separate task.
			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
			CALL A FUNCTION THAT MIGHT BLOCK. */
			vApplicationIdleHook();
 8005764:	f7fa fedc 	bl	8000520 <vApplicationIdleHook>
		prvCheckTasksWaitingTermination();
 8005768:	e7ee      	b.n	8005748 <prvIdleTask+0x8>
 800576a:	bf00      	nop
 800576c:	200038e0 	.word	0x200038e0
 8005770:	e000ed04 	.word	0xe000ed04

08005774 <prvInitialiseTaskLists>:

#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/

static void prvInitialiseTaskLists( void )
{
 8005774:	b580      	push	{r7, lr}
 8005776:	b082      	sub	sp, #8
 8005778:	af00      	add	r7, sp, #0
UBaseType_t uxPriority;

	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 800577a:	2300      	movs	r3, #0
 800577c:	607b      	str	r3, [r7, #4]
 800577e:	e00c      	b.n	800579a <prvInitialiseTaskLists+0x26>
	{
		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
 8005780:	687a      	ldr	r2, [r7, #4]
 8005782:	4613      	mov	r3, r2
 8005784:	009b      	lsls	r3, r3, #2
 8005786:	4413      	add	r3, r2
 8005788:	009b      	lsls	r3, r3, #2
 800578a:	4a12      	ldr	r2, [pc, #72]	; (80057d4 <prvInitialiseTaskLists+0x60>)
 800578c:	4413      	add	r3, r2
 800578e:	4618      	mov	r0, r3
 8005790:	f7fe fcc0 	bl	8004114 <vListInitialise>
	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8005794:	687b      	ldr	r3, [r7, #4]
 8005796:	3301      	adds	r3, #1
 8005798:	607b      	str	r3, [r7, #4]
 800579a:	687b      	ldr	r3, [r7, #4]
 800579c:	2b37      	cmp	r3, #55	; 0x37
 800579e:	d9ef      	bls.n	8005780 <prvInitialiseTaskLists+0xc>
	}

	vListInitialise( &xDelayedTaskList1 );
 80057a0:	480d      	ldr	r0, [pc, #52]	; (80057d8 <prvInitialiseTaskLists+0x64>)
 80057a2:	f7fe fcb7 	bl	8004114 <vListInitialise>
	vListInitialise( &xDelayedTaskList2 );
 80057a6:	480d      	ldr	r0, [pc, #52]	; (80057dc <prvInitialiseTaskLists+0x68>)
 80057a8:	f7fe fcb4 	bl	8004114 <vListInitialise>
	vListInitialise( &xPendingReadyList );
 80057ac:	480c      	ldr	r0, [pc, #48]	; (80057e0 <prvInitialiseTaskLists+0x6c>)
 80057ae:	f7fe fcb1 	bl	8004114 <vListInitialise>

	#if ( INCLUDE_vTaskDelete == 1 )
	{
		vListInitialise( &xTasksWaitingTermination );
 80057b2:	480c      	ldr	r0, [pc, #48]	; (80057e4 <prvInitialiseTaskLists+0x70>)
 80057b4:	f7fe fcae 	bl	8004114 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskDelete */

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		vListInitialise( &xSuspendedTaskList );
 80057b8:	480b      	ldr	r0, [pc, #44]	; (80057e8 <prvInitialiseTaskLists+0x74>)
 80057ba:	f7fe fcab 	bl	8004114 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskSuspend */

	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
	using list2. */
	pxDelayedTaskList = &xDelayedTaskList1;
 80057be:	4b0b      	ldr	r3, [pc, #44]	; (80057ec <prvInitialiseTaskLists+0x78>)
 80057c0:	4a05      	ldr	r2, [pc, #20]	; (80057d8 <prvInitialiseTaskLists+0x64>)
 80057c2:	601a      	str	r2, [r3, #0]
	pxOverflowDelayedTaskList = &xDelayedTaskList2;
 80057c4:	4b0a      	ldr	r3, [pc, #40]	; (80057f0 <prvInitialiseTaskLists+0x7c>)
 80057c6:	4a05      	ldr	r2, [pc, #20]	; (80057dc <prvInitialiseTaskLists+0x68>)
 80057c8:	601a      	str	r2, [r3, #0]
}
 80057ca:	bf00      	nop
 80057cc:	3708      	adds	r7, #8
 80057ce:	46bd      	mov	sp, r7
 80057d0:	bd80      	pop	{r7, pc}
 80057d2:	bf00      	nop
 80057d4:	200038e0 	.word	0x200038e0
 80057d8:	20003d40 	.word	0x20003d40
 80057dc:	20003d54 	.word	0x20003d54
 80057e0:	20003d70 	.word	0x20003d70
 80057e4:	20003d84 	.word	0x20003d84
 80057e8:	20003d9c 	.word	0x20003d9c
 80057ec:	20003d68 	.word	0x20003d68
 80057f0:	20003d6c 	.word	0x20003d6c

080057f4 <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/

static void prvCheckTasksWaitingTermination( void )
{
 80057f4:	b580      	push	{r7, lr}
 80057f6:	b082      	sub	sp, #8
 80057f8:	af00      	add	r7, sp, #0
	{
		TCB_t *pxTCB;

		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
		being called too often in the idle task. */
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 80057fa:	e019      	b.n	8005830 <prvCheckTasksWaitingTermination+0x3c>
		{
			taskENTER_CRITICAL();
 80057fc:	f000 fdda 	bl	80063b4 <vPortEnterCritical>
			{
				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8005800:	4b10      	ldr	r3, [pc, #64]	; (8005844 <prvCheckTasksWaitingTermination+0x50>)
 8005802:	68db      	ldr	r3, [r3, #12]
 8005804:	68db      	ldr	r3, [r3, #12]
 8005806:	607b      	str	r3, [r7, #4]
				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8005808:	687b      	ldr	r3, [r7, #4]
 800580a:	3304      	adds	r3, #4
 800580c:	4618      	mov	r0, r3
 800580e:	f7fe fd0b 	bl	8004228 <uxListRemove>
				--uxCurrentNumberOfTasks;
 8005812:	4b0d      	ldr	r3, [pc, #52]	; (8005848 <prvCheckTasksWaitingTermination+0x54>)
 8005814:	681b      	ldr	r3, [r3, #0]
 8005816:	3b01      	subs	r3, #1
 8005818:	4a0b      	ldr	r2, [pc, #44]	; (8005848 <prvCheckTasksWaitingTermination+0x54>)
 800581a:	6013      	str	r3, [r2, #0]
				--uxDeletedTasksWaitingCleanUp;
 800581c:	4b0b      	ldr	r3, [pc, #44]	; (800584c <prvCheckTasksWaitingTermination+0x58>)
 800581e:	681b      	ldr	r3, [r3, #0]
 8005820:	3b01      	subs	r3, #1
 8005822:	4a0a      	ldr	r2, [pc, #40]	; (800584c <prvCheckTasksWaitingTermination+0x58>)
 8005824:	6013      	str	r3, [r2, #0]
			}
			taskEXIT_CRITICAL();
 8005826:	f000 fdf5 	bl	8006414 <vPortExitCritical>

			prvDeleteTCB( pxTCB );
 800582a:	6878      	ldr	r0, [r7, #4]
 800582c:	f000 f810 	bl	8005850 <prvDeleteTCB>
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8005830:	4b06      	ldr	r3, [pc, #24]	; (800584c <prvCheckTasksWaitingTermination+0x58>)
 8005832:	681b      	ldr	r3, [r3, #0]
 8005834:	2b00      	cmp	r3, #0
 8005836:	d1e1      	bne.n	80057fc <prvCheckTasksWaitingTermination+0x8>
		}
	}
	#endif /* INCLUDE_vTaskDelete */
}
 8005838:	bf00      	nop
 800583a:	bf00      	nop
 800583c:	3708      	adds	r7, #8
 800583e:	46bd      	mov	sp, r7
 8005840:	bd80      	pop	{r7, pc}
 8005842:	bf00      	nop
 8005844:	20003d84 	.word	0x20003d84
 8005848:	20003db0 	.word	0x20003db0
 800584c:	20003d98 	.word	0x20003d98

08005850 <prvDeleteTCB>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelete == 1 )

	static void prvDeleteTCB( TCB_t *pxTCB )
	{
 8005850:	b580      	push	{r7, lr}
 8005852:	b084      	sub	sp, #16
 8005854:	af00      	add	r7, sp, #0
 8005856:	6078      	str	r0, [r7, #4]
		to the task to free any memory allocated at the application level.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		#if ( configUSE_NEWLIB_REENTRANT == 1 )
		{
			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
 8005858:	687b      	ldr	r3, [r7, #4]
 800585a:	3354      	adds	r3, #84	; 0x54
 800585c:	4618      	mov	r0, r3
 800585e:	f001 f93f 	bl	8006ae0 <_reclaim_reent>
		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
		{
			/* The task could have been allocated statically or dynamically, so
			check what was statically allocated before trying to free the
			memory. */
			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
 8005862:	687b      	ldr	r3, [r7, #4]
 8005864:	f893 30b9 	ldrb.w	r3, [r3, #185]	; 0xb9
 8005868:	2b00      	cmp	r3, #0
 800586a:	d108      	bne.n	800587e <prvDeleteTCB+0x2e>
			{
				/* Both the stack and TCB were allocated dynamically, so both
				must be freed. */
				vPortFree( pxTCB->pxStack );
 800586c:	687b      	ldr	r3, [r7, #4]
 800586e:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8005870:	4618      	mov	r0, r3
 8005872:	f000 ff65 	bl	8006740 <vPortFree>
				vPortFree( pxTCB );
 8005876:	6878      	ldr	r0, [r7, #4]
 8005878:	f000 ff62 	bl	8006740 <vPortFree>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
	}
 800587c:	e018      	b.n	80058b0 <prvDeleteTCB+0x60>
			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
 800587e:	687b      	ldr	r3, [r7, #4]
 8005880:	f893 30b9 	ldrb.w	r3, [r3, #185]	; 0xb9
 8005884:	2b01      	cmp	r3, #1
 8005886:	d103      	bne.n	8005890 <prvDeleteTCB+0x40>
				vPortFree( pxTCB );
 8005888:	6878      	ldr	r0, [r7, #4]
 800588a:	f000 ff59 	bl	8006740 <vPortFree>
	}
 800588e:	e00f      	b.n	80058b0 <prvDeleteTCB+0x60>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
 8005890:	687b      	ldr	r3, [r7, #4]
 8005892:	f893 30b9 	ldrb.w	r3, [r3, #185]	; 0xb9
 8005896:	2b02      	cmp	r3, #2
 8005898:	d00a      	beq.n	80058b0 <prvDeleteTCB+0x60>
	__asm volatile
 800589a:	f04f 0350 	mov.w	r3, #80	; 0x50
 800589e:	f383 8811 	msr	BASEPRI, r3
 80058a2:	f3bf 8f6f 	isb	sy
 80058a6:	f3bf 8f4f 	dsb	sy
 80058aa:	60fb      	str	r3, [r7, #12]
}
 80058ac:	bf00      	nop
 80058ae:	e7fe      	b.n	80058ae <prvDeleteTCB+0x5e>
	}
 80058b0:	bf00      	nop
 80058b2:	3710      	adds	r7, #16
 80058b4:	46bd      	mov	sp, r7
 80058b6:	bd80      	pop	{r7, pc}

080058b8 <prvResetNextTaskUnblockTime>:

#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/

static void prvResetNextTaskUnblockTime( void )
{
 80058b8:	b480      	push	{r7}
 80058ba:	b083      	sub	sp, #12
 80058bc:	af00      	add	r7, sp, #0
TCB_t *pxTCB;

	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 80058be:	4b0c      	ldr	r3, [pc, #48]	; (80058f0 <prvResetNextTaskUnblockTime+0x38>)
 80058c0:	681b      	ldr	r3, [r3, #0]
 80058c2:	681b      	ldr	r3, [r3, #0]
 80058c4:	2b00      	cmp	r3, #0
 80058c6:	d104      	bne.n	80058d2 <prvResetNextTaskUnblockTime+0x1a>
	{
		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
		the maximum possible value so it is	extremely unlikely that the
		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
		there is an item in the delayed list. */
		xNextTaskUnblockTime = portMAX_DELAY;
 80058c8:	4b0a      	ldr	r3, [pc, #40]	; (80058f4 <prvResetNextTaskUnblockTime+0x3c>)
 80058ca:	f04f 32ff 	mov.w	r2, #4294967295
 80058ce:	601a      	str	r2, [r3, #0]
		which the task at the head of the delayed list should be removed
		from the Blocked state. */
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
	}
}
 80058d0:	e008      	b.n	80058e4 <prvResetNextTaskUnblockTime+0x2c>
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80058d2:	4b07      	ldr	r3, [pc, #28]	; (80058f0 <prvResetNextTaskUnblockTime+0x38>)
 80058d4:	681b      	ldr	r3, [r3, #0]
 80058d6:	68db      	ldr	r3, [r3, #12]
 80058d8:	68db      	ldr	r3, [r3, #12]
 80058da:	607b      	str	r3, [r7, #4]
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
 80058dc:	687b      	ldr	r3, [r7, #4]
 80058de:	685b      	ldr	r3, [r3, #4]
 80058e0:	4a04      	ldr	r2, [pc, #16]	; (80058f4 <prvResetNextTaskUnblockTime+0x3c>)
 80058e2:	6013      	str	r3, [r2, #0]
}
 80058e4:	bf00      	nop
 80058e6:	370c      	adds	r7, #12
 80058e8:	46bd      	mov	sp, r7
 80058ea:	f85d 7b04 	ldr.w	r7, [sp], #4
 80058ee:	4770      	bx	lr
 80058f0:	20003d68 	.word	0x20003d68
 80058f4:	20003dd0 	.word	0x20003dd0

080058f8 <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

	BaseType_t xTaskGetSchedulerState( void )
	{
 80058f8:	b480      	push	{r7}
 80058fa:	b083      	sub	sp, #12
 80058fc:	af00      	add	r7, sp, #0
	BaseType_t xReturn;

		if( xSchedulerRunning == pdFALSE )
 80058fe:	4b0b      	ldr	r3, [pc, #44]	; (800592c <xTaskGetSchedulerState+0x34>)
 8005900:	681b      	ldr	r3, [r3, #0]
 8005902:	2b00      	cmp	r3, #0
 8005904:	d102      	bne.n	800590c <xTaskGetSchedulerState+0x14>
		{
			xReturn = taskSCHEDULER_NOT_STARTED;
 8005906:	2301      	movs	r3, #1
 8005908:	607b      	str	r3, [r7, #4]
 800590a:	e008      	b.n	800591e <xTaskGetSchedulerState+0x26>
		}
		else
		{
			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 800590c:	4b08      	ldr	r3, [pc, #32]	; (8005930 <xTaskGetSchedulerState+0x38>)
 800590e:	681b      	ldr	r3, [r3, #0]
 8005910:	2b00      	cmp	r3, #0
 8005912:	d102      	bne.n	800591a <xTaskGetSchedulerState+0x22>
			{
				xReturn = taskSCHEDULER_RUNNING;
 8005914:	2302      	movs	r3, #2
 8005916:	607b      	str	r3, [r7, #4]
 8005918:	e001      	b.n	800591e <xTaskGetSchedulerState+0x26>
			}
			else
			{
				xReturn = taskSCHEDULER_SUSPENDED;
 800591a:	2300      	movs	r3, #0
 800591c:	607b      	str	r3, [r7, #4]
			}
		}

		return xReturn;
 800591e:	687b      	ldr	r3, [r7, #4]
	}
 8005920:	4618      	mov	r0, r3
 8005922:	370c      	adds	r7, #12
 8005924:	46bd      	mov	sp, r7
 8005926:	f85d 7b04 	ldr.w	r7, [sp], #4
 800592a:	4770      	bx	lr
 800592c:	20003dbc 	.word	0x20003dbc
 8005930:	20003dd8 	.word	0x20003dd8

08005934 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
	{
 8005934:	b580      	push	{r7, lr}
 8005936:	b086      	sub	sp, #24
 8005938:	af00      	add	r7, sp, #0
 800593a:	6078      	str	r0, [r7, #4]
	TCB_t * const pxTCB = pxMutexHolder;
 800593c:	687b      	ldr	r3, [r7, #4]
 800593e:	613b      	str	r3, [r7, #16]
	BaseType_t xReturn = pdFALSE;
 8005940:	2300      	movs	r3, #0
 8005942:	617b      	str	r3, [r7, #20]

		if( pxMutexHolder != NULL )
 8005944:	687b      	ldr	r3, [r7, #4]
 8005946:	2b00      	cmp	r3, #0
 8005948:	d056      	beq.n	80059f8 <xTaskPriorityDisinherit+0xc4>
		{
			/* A task can only have an inherited priority if it holds the mutex.
			If the mutex is held by a task then it cannot be given from an
			interrupt, and if a mutex is given by the holding task then it must
			be the running state task. */
			configASSERT( pxTCB == pxCurrentTCB );
 800594a:	4b2e      	ldr	r3, [pc, #184]	; (8005a04 <xTaskPriorityDisinherit+0xd0>)
 800594c:	681b      	ldr	r3, [r3, #0]
 800594e:	693a      	ldr	r2, [r7, #16]
 8005950:	429a      	cmp	r2, r3
 8005952:	d00a      	beq.n	800596a <xTaskPriorityDisinherit+0x36>
	__asm volatile
 8005954:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005958:	f383 8811 	msr	BASEPRI, r3
 800595c:	f3bf 8f6f 	isb	sy
 8005960:	f3bf 8f4f 	dsb	sy
 8005964:	60fb      	str	r3, [r7, #12]
}
 8005966:	bf00      	nop
 8005968:	e7fe      	b.n	8005968 <xTaskPriorityDisinherit+0x34>
			configASSERT( pxTCB->uxMutexesHeld );
 800596a:	693b      	ldr	r3, [r7, #16]
 800596c:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 800596e:	2b00      	cmp	r3, #0
 8005970:	d10a      	bne.n	8005988 <xTaskPriorityDisinherit+0x54>
	__asm volatile
 8005972:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005976:	f383 8811 	msr	BASEPRI, r3
 800597a:	f3bf 8f6f 	isb	sy
 800597e:	f3bf 8f4f 	dsb	sy
 8005982:	60bb      	str	r3, [r7, #8]
}
 8005984:	bf00      	nop
 8005986:	e7fe      	b.n	8005986 <xTaskPriorityDisinherit+0x52>
			( pxTCB->uxMutexesHeld )--;
 8005988:	693b      	ldr	r3, [r7, #16]
 800598a:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 800598c:	1e5a      	subs	r2, r3, #1
 800598e:	693b      	ldr	r3, [r7, #16]
 8005990:	651a      	str	r2, [r3, #80]	; 0x50

			/* Has the holder of the mutex inherited the priority of another
			task? */
			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
 8005992:	693b      	ldr	r3, [r7, #16]
 8005994:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8005996:	693b      	ldr	r3, [r7, #16]
 8005998:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 800599a:	429a      	cmp	r2, r3
 800599c:	d02c      	beq.n	80059f8 <xTaskPriorityDisinherit+0xc4>
			{
				/* Only disinherit if no other mutexes are held. */
				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
 800599e:	693b      	ldr	r3, [r7, #16]
 80059a0:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 80059a2:	2b00      	cmp	r3, #0
 80059a4:	d128      	bne.n	80059f8 <xTaskPriorityDisinherit+0xc4>
					/* A task can only have an inherited priority if it holds
					the mutex.  If the mutex is held by a task then it cannot be
					given from an interrupt, and if a mutex is given by the
					holding task then it must be the running state task.  Remove
					the holding task from the ready/delayed list. */
					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 80059a6:	693b      	ldr	r3, [r7, #16]
 80059a8:	3304      	adds	r3, #4
 80059aa:	4618      	mov	r0, r3
 80059ac:	f7fe fc3c 	bl	8004228 <uxListRemove>
					}

					/* Disinherit the priority before adding the task into the
					new	ready list. */
					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
					pxTCB->uxPriority = pxTCB->uxBasePriority;
 80059b0:	693b      	ldr	r3, [r7, #16]
 80059b2:	6cda      	ldr	r2, [r3, #76]	; 0x4c
 80059b4:	693b      	ldr	r3, [r7, #16]
 80059b6:	62da      	str	r2, [r3, #44]	; 0x2c

					/* Reset the event list item value.  It cannot be in use for
					any other purpose if this task is running, and it must be
					running to give back the mutex. */
					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80059b8:	693b      	ldr	r3, [r7, #16]
 80059ba:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80059bc:	f1c3 0238 	rsb	r2, r3, #56	; 0x38
 80059c0:	693b      	ldr	r3, [r7, #16]
 80059c2:	619a      	str	r2, [r3, #24]
					prvAddTaskToReadyList( pxTCB );
 80059c4:	693b      	ldr	r3, [r7, #16]
 80059c6:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 80059c8:	4b0f      	ldr	r3, [pc, #60]	; (8005a08 <xTaskPriorityDisinherit+0xd4>)
 80059ca:	681b      	ldr	r3, [r3, #0]
 80059cc:	429a      	cmp	r2, r3
 80059ce:	d903      	bls.n	80059d8 <xTaskPriorityDisinherit+0xa4>
 80059d0:	693b      	ldr	r3, [r7, #16]
 80059d2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80059d4:	4a0c      	ldr	r2, [pc, #48]	; (8005a08 <xTaskPriorityDisinherit+0xd4>)
 80059d6:	6013      	str	r3, [r2, #0]
 80059d8:	693b      	ldr	r3, [r7, #16]
 80059da:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 80059dc:	4613      	mov	r3, r2
 80059de:	009b      	lsls	r3, r3, #2
 80059e0:	4413      	add	r3, r2
 80059e2:	009b      	lsls	r3, r3, #2
 80059e4:	4a09      	ldr	r2, [pc, #36]	; (8005a0c <xTaskPriorityDisinherit+0xd8>)
 80059e6:	441a      	add	r2, r3
 80059e8:	693b      	ldr	r3, [r7, #16]
 80059ea:	3304      	adds	r3, #4
 80059ec:	4619      	mov	r1, r3
 80059ee:	4610      	mov	r0, r2
 80059f0:	f7fe fbbd 	bl	800416e <vListInsertEnd>
					in an order different to that in which they were taken.
					If a context switch did not occur when the first mutex was
					returned, even if a task was waiting on it, then a context
					switch should occur when the last mutex is returned whether
					a task is waiting on it or not. */
					xReturn = pdTRUE;
 80059f4:	2301      	movs	r3, #1
 80059f6:	617b      	str	r3, [r7, #20]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		return xReturn;
 80059f8:	697b      	ldr	r3, [r7, #20]
	}
 80059fa:	4618      	mov	r0, r3
 80059fc:	3718      	adds	r7, #24
 80059fe:	46bd      	mov	sp, r7
 8005a00:	bd80      	pop	{r7, pc}
 8005a02:	bf00      	nop
 8005a04:	200038dc 	.word	0x200038dc
 8005a08:	20003db8 	.word	0x20003db8
 8005a0c:	200038e0 	.word	0x200038e0

08005a10 <prvAddCurrentTaskToDelayedList>:

#endif
/*-----------------------------------------------------------*/

static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
 8005a10:	b580      	push	{r7, lr}
 8005a12:	b084      	sub	sp, #16
 8005a14:	af00      	add	r7, sp, #0
 8005a16:	6078      	str	r0, [r7, #4]
 8005a18:	6039      	str	r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
 8005a1a:	4b21      	ldr	r3, [pc, #132]	; (8005aa0 <prvAddCurrentTaskToDelayedList+0x90>)
 8005a1c:	681b      	ldr	r3, [r3, #0]
 8005a1e:	60fb      	str	r3, [r7, #12]
	}
	#endif

	/* Remove the task from the ready list before adding it to the blocked list
	as the same list item is used for both lists. */
	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 8005a20:	4b20      	ldr	r3, [pc, #128]	; (8005aa4 <prvAddCurrentTaskToDelayedList+0x94>)
 8005a22:	681b      	ldr	r3, [r3, #0]
 8005a24:	3304      	adds	r3, #4
 8005a26:	4618      	mov	r0, r3
 8005a28:	f7fe fbfe 	bl	8004228 <uxListRemove>
		mtCOVERAGE_TEST_MARKER();
	}

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
 8005a2c:	687b      	ldr	r3, [r7, #4]
 8005a2e:	f1b3 3fff 	cmp.w	r3, #4294967295
 8005a32:	d10a      	bne.n	8005a4a <prvAddCurrentTaskToDelayedList+0x3a>
 8005a34:	683b      	ldr	r3, [r7, #0]
 8005a36:	2b00      	cmp	r3, #0
 8005a38:	d007      	beq.n	8005a4a <prvAddCurrentTaskToDelayedList+0x3a>
		{
			/* Add the task to the suspended task list instead of a delayed task
			list to ensure it is not woken by a timing event.  It will block
			indefinitely. */
			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
 8005a3a:	4b1a      	ldr	r3, [pc, #104]	; (8005aa4 <prvAddCurrentTaskToDelayedList+0x94>)
 8005a3c:	681b      	ldr	r3, [r3, #0]
 8005a3e:	3304      	adds	r3, #4
 8005a40:	4619      	mov	r1, r3
 8005a42:	4819      	ldr	r0, [pc, #100]	; (8005aa8 <prvAddCurrentTaskToDelayedList+0x98>)
 8005a44:	f7fe fb93 	bl	800416e <vListInsertEnd>

		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
		( void ) xCanBlockIndefinitely;
	}
	#endif /* INCLUDE_vTaskSuspend */
}
 8005a48:	e026      	b.n	8005a98 <prvAddCurrentTaskToDelayedList+0x88>
			xTimeToWake = xConstTickCount + xTicksToWait;
 8005a4a:	68fa      	ldr	r2, [r7, #12]
 8005a4c:	687b      	ldr	r3, [r7, #4]
 8005a4e:	4413      	add	r3, r2
 8005a50:	60bb      	str	r3, [r7, #8]
			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
 8005a52:	4b14      	ldr	r3, [pc, #80]	; (8005aa4 <prvAddCurrentTaskToDelayedList+0x94>)
 8005a54:	681b      	ldr	r3, [r3, #0]
 8005a56:	68ba      	ldr	r2, [r7, #8]
 8005a58:	605a      	str	r2, [r3, #4]
			if( xTimeToWake < xConstTickCount )
 8005a5a:	68ba      	ldr	r2, [r7, #8]
 8005a5c:	68fb      	ldr	r3, [r7, #12]
 8005a5e:	429a      	cmp	r2, r3
 8005a60:	d209      	bcs.n	8005a76 <prvAddCurrentTaskToDelayedList+0x66>
				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 8005a62:	4b12      	ldr	r3, [pc, #72]	; (8005aac <prvAddCurrentTaskToDelayedList+0x9c>)
 8005a64:	681a      	ldr	r2, [r3, #0]
 8005a66:	4b0f      	ldr	r3, [pc, #60]	; (8005aa4 <prvAddCurrentTaskToDelayedList+0x94>)
 8005a68:	681b      	ldr	r3, [r3, #0]
 8005a6a:	3304      	adds	r3, #4
 8005a6c:	4619      	mov	r1, r3
 8005a6e:	4610      	mov	r0, r2
 8005a70:	f7fe fba1 	bl	80041b6 <vListInsert>
}
 8005a74:	e010      	b.n	8005a98 <prvAddCurrentTaskToDelayedList+0x88>
				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 8005a76:	4b0e      	ldr	r3, [pc, #56]	; (8005ab0 <prvAddCurrentTaskToDelayedList+0xa0>)
 8005a78:	681a      	ldr	r2, [r3, #0]
 8005a7a:	4b0a      	ldr	r3, [pc, #40]	; (8005aa4 <prvAddCurrentTaskToDelayedList+0x94>)
 8005a7c:	681b      	ldr	r3, [r3, #0]
 8005a7e:	3304      	adds	r3, #4
 8005a80:	4619      	mov	r1, r3
 8005a82:	4610      	mov	r0, r2
 8005a84:	f7fe fb97 	bl	80041b6 <vListInsert>
				if( xTimeToWake < xNextTaskUnblockTime )
 8005a88:	4b0a      	ldr	r3, [pc, #40]	; (8005ab4 <prvAddCurrentTaskToDelayedList+0xa4>)
 8005a8a:	681b      	ldr	r3, [r3, #0]
 8005a8c:	68ba      	ldr	r2, [r7, #8]
 8005a8e:	429a      	cmp	r2, r3
 8005a90:	d202      	bcs.n	8005a98 <prvAddCurrentTaskToDelayedList+0x88>
					xNextTaskUnblockTime = xTimeToWake;
 8005a92:	4a08      	ldr	r2, [pc, #32]	; (8005ab4 <prvAddCurrentTaskToDelayedList+0xa4>)
 8005a94:	68bb      	ldr	r3, [r7, #8]
 8005a96:	6013      	str	r3, [r2, #0]
}
 8005a98:	bf00      	nop
 8005a9a:	3710      	adds	r7, #16
 8005a9c:	46bd      	mov	sp, r7
 8005a9e:	bd80      	pop	{r7, pc}
 8005aa0:	20003db4 	.word	0x20003db4
 8005aa4:	200038dc 	.word	0x200038dc
 8005aa8:	20003d9c 	.word	0x20003d9c
 8005aac:	20003d6c 	.word	0x20003d6c
 8005ab0:	20003d68 	.word	0x20003d68
 8005ab4:	20003dd0 	.word	0x20003dd0

08005ab8 <xTimerCreateTimerTask>:
									TimerCallbackFunction_t pxCallbackFunction,
									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/

BaseType_t xTimerCreateTimerTask( void )
{
 8005ab8:	b580      	push	{r7, lr}
 8005aba:	b08a      	sub	sp, #40	; 0x28
 8005abc:	af04      	add	r7, sp, #16
BaseType_t xReturn = pdFAIL;
 8005abe:	2300      	movs	r3, #0
 8005ac0:	617b      	str	r3, [r7, #20]

	/* This function is called when the scheduler is started if
	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
	timer service task has been created/initialised.  If timers have already
	been created then the initialisation will already have been performed. */
	prvCheckForValidListAndQueue();
 8005ac2:	f000 fb07 	bl	80060d4 <prvCheckForValidListAndQueue>

	if( xTimerQueue != NULL )
 8005ac6:	4b1c      	ldr	r3, [pc, #112]	; (8005b38 <xTimerCreateTimerTask+0x80>)
 8005ac8:	681b      	ldr	r3, [r3, #0]
 8005aca:	2b00      	cmp	r3, #0
 8005acc:	d021      	beq.n	8005b12 <xTimerCreateTimerTask+0x5a>
	{
		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
		{
			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
 8005ace:	2300      	movs	r3, #0
 8005ad0:	60fb      	str	r3, [r7, #12]
			StackType_t *pxTimerTaskStackBuffer = NULL;
 8005ad2:	2300      	movs	r3, #0
 8005ad4:	60bb      	str	r3, [r7, #8]
			uint32_t ulTimerTaskStackSize;

			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
 8005ad6:	1d3a      	adds	r2, r7, #4
 8005ad8:	f107 0108 	add.w	r1, r7, #8
 8005adc:	f107 030c 	add.w	r3, r7, #12
 8005ae0:	4618      	mov	r0, r3
 8005ae2:	f7fe fafd 	bl	80040e0 <vApplicationGetTimerTaskMemory>
			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
 8005ae6:	6879      	ldr	r1, [r7, #4]
 8005ae8:	68bb      	ldr	r3, [r7, #8]
 8005aea:	68fa      	ldr	r2, [r7, #12]
 8005aec:	9202      	str	r2, [sp, #8]
 8005aee:	9301      	str	r3, [sp, #4]
 8005af0:	2302      	movs	r3, #2
 8005af2:	9300      	str	r3, [sp, #0]
 8005af4:	2300      	movs	r3, #0
 8005af6:	460a      	mov	r2, r1
 8005af8:	4910      	ldr	r1, [pc, #64]	; (8005b3c <xTimerCreateTimerTask+0x84>)
 8005afa:	4811      	ldr	r0, [pc, #68]	; (8005b40 <xTimerCreateTimerTask+0x88>)
 8005afc:	f7ff f8aa 	bl	8004c54 <xTaskCreateStatic>
 8005b00:	4603      	mov	r3, r0
 8005b02:	4a10      	ldr	r2, [pc, #64]	; (8005b44 <xTimerCreateTimerTask+0x8c>)
 8005b04:	6013      	str	r3, [r2, #0]
													NULL,
													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
													pxTimerTaskStackBuffer,
													pxTimerTaskTCBBuffer );

			if( xTimerTaskHandle != NULL )
 8005b06:	4b0f      	ldr	r3, [pc, #60]	; (8005b44 <xTimerCreateTimerTask+0x8c>)
 8005b08:	681b      	ldr	r3, [r3, #0]
 8005b0a:	2b00      	cmp	r3, #0
 8005b0c:	d001      	beq.n	8005b12 <xTimerCreateTimerTask+0x5a>
			{
				xReturn = pdPASS;
 8005b0e:	2301      	movs	r3, #1
 8005b10:	617b      	str	r3, [r7, #20]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	configASSERT( xReturn );
 8005b12:	697b      	ldr	r3, [r7, #20]
 8005b14:	2b00      	cmp	r3, #0
 8005b16:	d10a      	bne.n	8005b2e <xTimerCreateTimerTask+0x76>
	__asm volatile
 8005b18:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005b1c:	f383 8811 	msr	BASEPRI, r3
 8005b20:	f3bf 8f6f 	isb	sy
 8005b24:	f3bf 8f4f 	dsb	sy
 8005b28:	613b      	str	r3, [r7, #16]
}
 8005b2a:	bf00      	nop
 8005b2c:	e7fe      	b.n	8005b2c <xTimerCreateTimerTask+0x74>
	return xReturn;
 8005b2e:	697b      	ldr	r3, [r7, #20]
}
 8005b30:	4618      	mov	r0, r3
 8005b32:	3718      	adds	r7, #24
 8005b34:	46bd      	mov	sp, r7
 8005b36:	bd80      	pop	{r7, pc}
 8005b38:	20003e0c 	.word	0x20003e0c
 8005b3c:	08006c80 	.word	0x08006c80
 8005b40:	08005c7d 	.word	0x08005c7d
 8005b44:	20003e10 	.word	0x20003e10

08005b48 <xTimerGenericCommand>:
	}
}
/*-----------------------------------------------------------*/

BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
{
 8005b48:	b580      	push	{r7, lr}
 8005b4a:	b08a      	sub	sp, #40	; 0x28
 8005b4c:	af00      	add	r7, sp, #0
 8005b4e:	60f8      	str	r0, [r7, #12]
 8005b50:	60b9      	str	r1, [r7, #8]
 8005b52:	607a      	str	r2, [r7, #4]
 8005b54:	603b      	str	r3, [r7, #0]
BaseType_t xReturn = pdFAIL;
 8005b56:	2300      	movs	r3, #0
 8005b58:	627b      	str	r3, [r7, #36]	; 0x24
DaemonTaskMessage_t xMessage;

	configASSERT( xTimer );
 8005b5a:	68fb      	ldr	r3, [r7, #12]
 8005b5c:	2b00      	cmp	r3, #0
 8005b5e:	d10a      	bne.n	8005b76 <xTimerGenericCommand+0x2e>
	__asm volatile
 8005b60:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005b64:	f383 8811 	msr	BASEPRI, r3
 8005b68:	f3bf 8f6f 	isb	sy
 8005b6c:	f3bf 8f4f 	dsb	sy
 8005b70:	623b      	str	r3, [r7, #32]
}
 8005b72:	bf00      	nop
 8005b74:	e7fe      	b.n	8005b74 <xTimerGenericCommand+0x2c>

	/* Send a message to the timer service task to perform a particular action
	on a particular timer definition. */
	if( xTimerQueue != NULL )
 8005b76:	4b1a      	ldr	r3, [pc, #104]	; (8005be0 <xTimerGenericCommand+0x98>)
 8005b78:	681b      	ldr	r3, [r3, #0]
 8005b7a:	2b00      	cmp	r3, #0
 8005b7c:	d02a      	beq.n	8005bd4 <xTimerGenericCommand+0x8c>
	{
		/* Send a command to the timer service task to start the xTimer timer. */
		xMessage.xMessageID = xCommandID;
 8005b7e:	68bb      	ldr	r3, [r7, #8]
 8005b80:	613b      	str	r3, [r7, #16]
		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
 8005b82:	687b      	ldr	r3, [r7, #4]
 8005b84:	617b      	str	r3, [r7, #20]
		xMessage.u.xTimerParameters.pxTimer = xTimer;
 8005b86:	68fb      	ldr	r3, [r7, #12]
 8005b88:	61bb      	str	r3, [r7, #24]

		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
 8005b8a:	68bb      	ldr	r3, [r7, #8]
 8005b8c:	2b05      	cmp	r3, #5
 8005b8e:	dc18      	bgt.n	8005bc2 <xTimerGenericCommand+0x7a>
		{
			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
 8005b90:	f7ff feb2 	bl	80058f8 <xTaskGetSchedulerState>
 8005b94:	4603      	mov	r3, r0
 8005b96:	2b02      	cmp	r3, #2
 8005b98:	d109      	bne.n	8005bae <xTimerGenericCommand+0x66>
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
 8005b9a:	4b11      	ldr	r3, [pc, #68]	; (8005be0 <xTimerGenericCommand+0x98>)
 8005b9c:	6818      	ldr	r0, [r3, #0]
 8005b9e:	f107 0110 	add.w	r1, r7, #16
 8005ba2:	2300      	movs	r3, #0
 8005ba4:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 8005ba6:	f7fe fc6d 	bl	8004484 <xQueueGenericSend>
 8005baa:	6278      	str	r0, [r7, #36]	; 0x24
 8005bac:	e012      	b.n	8005bd4 <xTimerGenericCommand+0x8c>
			}
			else
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
 8005bae:	4b0c      	ldr	r3, [pc, #48]	; (8005be0 <xTimerGenericCommand+0x98>)
 8005bb0:	6818      	ldr	r0, [r3, #0]
 8005bb2:	f107 0110 	add.w	r1, r7, #16
 8005bb6:	2300      	movs	r3, #0
 8005bb8:	2200      	movs	r2, #0
 8005bba:	f7fe fc63 	bl	8004484 <xQueueGenericSend>
 8005bbe:	6278      	str	r0, [r7, #36]	; 0x24
 8005bc0:	e008      	b.n	8005bd4 <xTimerGenericCommand+0x8c>
			}
		}
		else
		{
			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
 8005bc2:	4b07      	ldr	r3, [pc, #28]	; (8005be0 <xTimerGenericCommand+0x98>)
 8005bc4:	6818      	ldr	r0, [r3, #0]
 8005bc6:	f107 0110 	add.w	r1, r7, #16
 8005bca:	2300      	movs	r3, #0
 8005bcc:	683a      	ldr	r2, [r7, #0]
 8005bce:	f7fe fd57 	bl	8004680 <xQueueGenericSendFromISR>
 8005bd2:	6278      	str	r0, [r7, #36]	; 0x24
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	return xReturn;
 8005bd4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
}
 8005bd6:	4618      	mov	r0, r3
 8005bd8:	3728      	adds	r7, #40	; 0x28
 8005bda:	46bd      	mov	sp, r7
 8005bdc:	bd80      	pop	{r7, pc}
 8005bde:	bf00      	nop
 8005be0:	20003e0c 	.word	0x20003e0c

08005be4 <prvProcessExpiredTimer>:
	return pxTimer->pcTimerName;
}
/*-----------------------------------------------------------*/

static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
{
 8005be4:	b580      	push	{r7, lr}
 8005be6:	b088      	sub	sp, #32
 8005be8:	af02      	add	r7, sp, #8
 8005bea:	6078      	str	r0, [r7, #4]
 8005bec:	6039      	str	r1, [r7, #0]
BaseType_t xResult;
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8005bee:	4b22      	ldr	r3, [pc, #136]	; (8005c78 <prvProcessExpiredTimer+0x94>)
 8005bf0:	681b      	ldr	r3, [r3, #0]
 8005bf2:	68db      	ldr	r3, [r3, #12]
 8005bf4:	68db      	ldr	r3, [r3, #12]
 8005bf6:	617b      	str	r3, [r7, #20]

	/* Remove the timer from the list of active timers.  A check has already
	been performed to ensure the list is not empty. */
	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8005bf8:	697b      	ldr	r3, [r7, #20]
 8005bfa:	3304      	adds	r3, #4
 8005bfc:	4618      	mov	r0, r3
 8005bfe:	f7fe fb13 	bl	8004228 <uxListRemove>
	traceTIMER_EXPIRED( pxTimer );

	/* If the timer is an auto-reload timer then calculate the next
	expiry time and re-insert the timer in the list of active timers. */
	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 8005c02:	697b      	ldr	r3, [r7, #20]
 8005c04:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8005c08:	f003 0304 	and.w	r3, r3, #4
 8005c0c:	2b00      	cmp	r3, #0
 8005c0e:	d022      	beq.n	8005c56 <prvProcessExpiredTimer+0x72>
	{
		/* The timer is inserted into a list using a time relative to anything
		other than the current time.  It will therefore be inserted into the
		correct list relative to the time this task thinks it is now. */
		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
 8005c10:	697b      	ldr	r3, [r7, #20]
 8005c12:	699a      	ldr	r2, [r3, #24]
 8005c14:	687b      	ldr	r3, [r7, #4]
 8005c16:	18d1      	adds	r1, r2, r3
 8005c18:	687b      	ldr	r3, [r7, #4]
 8005c1a:	683a      	ldr	r2, [r7, #0]
 8005c1c:	6978      	ldr	r0, [r7, #20]
 8005c1e:	f000 f8d1 	bl	8005dc4 <prvInsertTimerInActiveList>
 8005c22:	4603      	mov	r3, r0
 8005c24:	2b00      	cmp	r3, #0
 8005c26:	d01f      	beq.n	8005c68 <prvProcessExpiredTimer+0x84>
		{
			/* The timer expired before it was added to the active timer
			list.  Reload it now.  */
			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 8005c28:	2300      	movs	r3, #0
 8005c2a:	9300      	str	r3, [sp, #0]
 8005c2c:	2300      	movs	r3, #0
 8005c2e:	687a      	ldr	r2, [r7, #4]
 8005c30:	2100      	movs	r1, #0
 8005c32:	6978      	ldr	r0, [r7, #20]
 8005c34:	f7ff ff88 	bl	8005b48 <xTimerGenericCommand>
 8005c38:	6138      	str	r0, [r7, #16]
			configASSERT( xResult );
 8005c3a:	693b      	ldr	r3, [r7, #16]
 8005c3c:	2b00      	cmp	r3, #0
 8005c3e:	d113      	bne.n	8005c68 <prvProcessExpiredTimer+0x84>
	__asm volatile
 8005c40:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005c44:	f383 8811 	msr	BASEPRI, r3
 8005c48:	f3bf 8f6f 	isb	sy
 8005c4c:	f3bf 8f4f 	dsb	sy
 8005c50:	60fb      	str	r3, [r7, #12]
}
 8005c52:	bf00      	nop
 8005c54:	e7fe      	b.n	8005c54 <prvProcessExpiredTimer+0x70>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8005c56:	697b      	ldr	r3, [r7, #20]
 8005c58:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8005c5c:	f023 0301 	bic.w	r3, r3, #1
 8005c60:	b2da      	uxtb	r2, r3
 8005c62:	697b      	ldr	r3, [r7, #20]
 8005c64:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
		mtCOVERAGE_TEST_MARKER();
	}

	/* Call the timer callback. */
	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8005c68:	697b      	ldr	r3, [r7, #20]
 8005c6a:	6a1b      	ldr	r3, [r3, #32]
 8005c6c:	6978      	ldr	r0, [r7, #20]
 8005c6e:	4798      	blx	r3
}
 8005c70:	bf00      	nop
 8005c72:	3718      	adds	r7, #24
 8005c74:	46bd      	mov	sp, r7
 8005c76:	bd80      	pop	{r7, pc}
 8005c78:	20003e04 	.word	0x20003e04

08005c7c <prvTimerTask>:
/*-----------------------------------------------------------*/

static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
 8005c7c:	b580      	push	{r7, lr}
 8005c7e:	b084      	sub	sp, #16
 8005c80:	af00      	add	r7, sp, #0
 8005c82:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* Query the timers list to see if it contains any timers, and if so,
		obtain the time at which the next timer will expire. */
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 8005c84:	f107 0308 	add.w	r3, r7, #8
 8005c88:	4618      	mov	r0, r3
 8005c8a:	f000 f857 	bl	8005d3c <prvGetNextExpireTime>
 8005c8e:	60f8      	str	r0, [r7, #12]

		/* If a timer has expired, process it.  Otherwise, block this task
		until either a timer does expire, or a command is received. */
		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
 8005c90:	68bb      	ldr	r3, [r7, #8]
 8005c92:	4619      	mov	r1, r3
 8005c94:	68f8      	ldr	r0, [r7, #12]
 8005c96:	f000 f803 	bl	8005ca0 <prvProcessTimerOrBlockTask>

		/* Empty the command queue. */
		prvProcessReceivedCommands();
 8005c9a:	f000 f8d5 	bl	8005e48 <prvProcessReceivedCommands>
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 8005c9e:	e7f1      	b.n	8005c84 <prvTimerTask+0x8>

08005ca0 <prvProcessTimerOrBlockTask>:
	}
}
/*-----------------------------------------------------------*/

static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
{
 8005ca0:	b580      	push	{r7, lr}
 8005ca2:	b084      	sub	sp, #16
 8005ca4:	af00      	add	r7, sp, #0
 8005ca6:	6078      	str	r0, [r7, #4]
 8005ca8:	6039      	str	r1, [r7, #0]
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;

	vTaskSuspendAll();
 8005caa:	f7ff fa2f 	bl	800510c <vTaskSuspendAll>
		/* Obtain the time now to make an assessment as to whether the timer
		has expired or not.  If obtaining the time causes the lists to switch
		then don't process this timer as any timers that remained in the list
		when the lists were switched will have been processed within the
		prvSampleTimeNow() function. */
		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 8005cae:	f107 0308 	add.w	r3, r7, #8
 8005cb2:	4618      	mov	r0, r3
 8005cb4:	f000 f866 	bl	8005d84 <prvSampleTimeNow>
 8005cb8:	60f8      	str	r0, [r7, #12]
		if( xTimerListsWereSwitched == pdFALSE )
 8005cba:	68bb      	ldr	r3, [r7, #8]
 8005cbc:	2b00      	cmp	r3, #0
 8005cbe:	d130      	bne.n	8005d22 <prvProcessTimerOrBlockTask+0x82>
		{
			/* The tick count has not overflowed, has the timer expired? */
			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
 8005cc0:	683b      	ldr	r3, [r7, #0]
 8005cc2:	2b00      	cmp	r3, #0
 8005cc4:	d10a      	bne.n	8005cdc <prvProcessTimerOrBlockTask+0x3c>
 8005cc6:	687a      	ldr	r2, [r7, #4]
 8005cc8:	68fb      	ldr	r3, [r7, #12]
 8005cca:	429a      	cmp	r2, r3
 8005ccc:	d806      	bhi.n	8005cdc <prvProcessTimerOrBlockTask+0x3c>
			{
				( void ) xTaskResumeAll();
 8005cce:	f7ff fa2b 	bl	8005128 <xTaskResumeAll>
				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
 8005cd2:	68f9      	ldr	r1, [r7, #12]
 8005cd4:	6878      	ldr	r0, [r7, #4]
 8005cd6:	f7ff ff85 	bl	8005be4 <prvProcessExpiredTimer>
		else
		{
			( void ) xTaskResumeAll();
		}
	}
}
 8005cda:	e024      	b.n	8005d26 <prvProcessTimerOrBlockTask+0x86>
				if( xListWasEmpty != pdFALSE )
 8005cdc:	683b      	ldr	r3, [r7, #0]
 8005cde:	2b00      	cmp	r3, #0
 8005ce0:	d008      	beq.n	8005cf4 <prvProcessTimerOrBlockTask+0x54>
					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
 8005ce2:	4b13      	ldr	r3, [pc, #76]	; (8005d30 <prvProcessTimerOrBlockTask+0x90>)
 8005ce4:	681b      	ldr	r3, [r3, #0]
 8005ce6:	681b      	ldr	r3, [r3, #0]
 8005ce8:	2b00      	cmp	r3, #0
 8005cea:	d101      	bne.n	8005cf0 <prvProcessTimerOrBlockTask+0x50>
 8005cec:	2301      	movs	r3, #1
 8005cee:	e000      	b.n	8005cf2 <prvProcessTimerOrBlockTask+0x52>
 8005cf0:	2300      	movs	r3, #0
 8005cf2:	603b      	str	r3, [r7, #0]
				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
 8005cf4:	4b0f      	ldr	r3, [pc, #60]	; (8005d34 <prvProcessTimerOrBlockTask+0x94>)
 8005cf6:	6818      	ldr	r0, [r3, #0]
 8005cf8:	687a      	ldr	r2, [r7, #4]
 8005cfa:	68fb      	ldr	r3, [r7, #12]
 8005cfc:	1ad3      	subs	r3, r2, r3
 8005cfe:	683a      	ldr	r2, [r7, #0]
 8005d00:	4619      	mov	r1, r3
 8005d02:	f7fe ff73 	bl	8004bec <vQueueWaitForMessageRestricted>
				if( xTaskResumeAll() == pdFALSE )
 8005d06:	f7ff fa0f 	bl	8005128 <xTaskResumeAll>
 8005d0a:	4603      	mov	r3, r0
 8005d0c:	2b00      	cmp	r3, #0
 8005d0e:	d10a      	bne.n	8005d26 <prvProcessTimerOrBlockTask+0x86>
					portYIELD_WITHIN_API();
 8005d10:	4b09      	ldr	r3, [pc, #36]	; (8005d38 <prvProcessTimerOrBlockTask+0x98>)
 8005d12:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8005d16:	601a      	str	r2, [r3, #0]
 8005d18:	f3bf 8f4f 	dsb	sy
 8005d1c:	f3bf 8f6f 	isb	sy
}
 8005d20:	e001      	b.n	8005d26 <prvProcessTimerOrBlockTask+0x86>
			( void ) xTaskResumeAll();
 8005d22:	f7ff fa01 	bl	8005128 <xTaskResumeAll>
}
 8005d26:	bf00      	nop
 8005d28:	3710      	adds	r7, #16
 8005d2a:	46bd      	mov	sp, r7
 8005d2c:	bd80      	pop	{r7, pc}
 8005d2e:	bf00      	nop
 8005d30:	20003e08 	.word	0x20003e08
 8005d34:	20003e0c 	.word	0x20003e0c
 8005d38:	e000ed04 	.word	0xe000ed04

08005d3c <prvGetNextExpireTime>:
/*-----------------------------------------------------------*/

static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
{
 8005d3c:	b480      	push	{r7}
 8005d3e:	b085      	sub	sp, #20
 8005d40:	af00      	add	r7, sp, #0
 8005d42:	6078      	str	r0, [r7, #4]
	the timer with the nearest expiry time will expire.  If there are no
	active timers then just set the next expire time to 0.  That will cause
	this task to unblock when the tick count overflows, at which point the
	timer lists will be switched and the next expiry time can be
	re-assessed.  */
	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
 8005d44:	4b0e      	ldr	r3, [pc, #56]	; (8005d80 <prvGetNextExpireTime+0x44>)
 8005d46:	681b      	ldr	r3, [r3, #0]
 8005d48:	681b      	ldr	r3, [r3, #0]
 8005d4a:	2b00      	cmp	r3, #0
 8005d4c:	d101      	bne.n	8005d52 <prvGetNextExpireTime+0x16>
 8005d4e:	2201      	movs	r2, #1
 8005d50:	e000      	b.n	8005d54 <prvGetNextExpireTime+0x18>
 8005d52:	2200      	movs	r2, #0
 8005d54:	687b      	ldr	r3, [r7, #4]
 8005d56:	601a      	str	r2, [r3, #0]
	if( *pxListWasEmpty == pdFALSE )
 8005d58:	687b      	ldr	r3, [r7, #4]
 8005d5a:	681b      	ldr	r3, [r3, #0]
 8005d5c:	2b00      	cmp	r3, #0
 8005d5e:	d105      	bne.n	8005d6c <prvGetNextExpireTime+0x30>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 8005d60:	4b07      	ldr	r3, [pc, #28]	; (8005d80 <prvGetNextExpireTime+0x44>)
 8005d62:	681b      	ldr	r3, [r3, #0]
 8005d64:	68db      	ldr	r3, [r3, #12]
 8005d66:	681b      	ldr	r3, [r3, #0]
 8005d68:	60fb      	str	r3, [r7, #12]
 8005d6a:	e001      	b.n	8005d70 <prvGetNextExpireTime+0x34>
	}
	else
	{
		/* Ensure the task unblocks when the tick count rolls over. */
		xNextExpireTime = ( TickType_t ) 0U;
 8005d6c:	2300      	movs	r3, #0
 8005d6e:	60fb      	str	r3, [r7, #12]
	}

	return xNextExpireTime;
 8005d70:	68fb      	ldr	r3, [r7, #12]
}
 8005d72:	4618      	mov	r0, r3
 8005d74:	3714      	adds	r7, #20
 8005d76:	46bd      	mov	sp, r7
 8005d78:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005d7c:	4770      	bx	lr
 8005d7e:	bf00      	nop
 8005d80:	20003e04 	.word	0x20003e04

08005d84 <prvSampleTimeNow>:
/*-----------------------------------------------------------*/

static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
 8005d84:	b580      	push	{r7, lr}
 8005d86:	b084      	sub	sp, #16
 8005d88:	af00      	add	r7, sp, #0
 8005d8a:	6078      	str	r0, [r7, #4]
TickType_t xTimeNow;
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */

	xTimeNow = xTaskGetTickCount();
 8005d8c:	f7ff fa6a 	bl	8005264 <xTaskGetTickCount>
 8005d90:	60f8      	str	r0, [r7, #12]

	if( xTimeNow < xLastTime )
 8005d92:	4b0b      	ldr	r3, [pc, #44]	; (8005dc0 <prvSampleTimeNow+0x3c>)
 8005d94:	681b      	ldr	r3, [r3, #0]
 8005d96:	68fa      	ldr	r2, [r7, #12]
 8005d98:	429a      	cmp	r2, r3
 8005d9a:	d205      	bcs.n	8005da8 <prvSampleTimeNow+0x24>
	{
		prvSwitchTimerLists();
 8005d9c:	f000 f936 	bl	800600c <prvSwitchTimerLists>
		*pxTimerListsWereSwitched = pdTRUE;
 8005da0:	687b      	ldr	r3, [r7, #4]
 8005da2:	2201      	movs	r2, #1
 8005da4:	601a      	str	r2, [r3, #0]
 8005da6:	e002      	b.n	8005dae <prvSampleTimeNow+0x2a>
	}
	else
	{
		*pxTimerListsWereSwitched = pdFALSE;
 8005da8:	687b      	ldr	r3, [r7, #4]
 8005daa:	2200      	movs	r2, #0
 8005dac:	601a      	str	r2, [r3, #0]
	}

	xLastTime = xTimeNow;
 8005dae:	4a04      	ldr	r2, [pc, #16]	; (8005dc0 <prvSampleTimeNow+0x3c>)
 8005db0:	68fb      	ldr	r3, [r7, #12]
 8005db2:	6013      	str	r3, [r2, #0]

	return xTimeNow;
 8005db4:	68fb      	ldr	r3, [r7, #12]
}
 8005db6:	4618      	mov	r0, r3
 8005db8:	3710      	adds	r7, #16
 8005dba:	46bd      	mov	sp, r7
 8005dbc:	bd80      	pop	{r7, pc}
 8005dbe:	bf00      	nop
 8005dc0:	20003e14 	.word	0x20003e14

08005dc4 <prvInsertTimerInActiveList>:
/*-----------------------------------------------------------*/

static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
{
 8005dc4:	b580      	push	{r7, lr}
 8005dc6:	b086      	sub	sp, #24
 8005dc8:	af00      	add	r7, sp, #0
 8005dca:	60f8      	str	r0, [r7, #12]
 8005dcc:	60b9      	str	r1, [r7, #8]
 8005dce:	607a      	str	r2, [r7, #4]
 8005dd0:	603b      	str	r3, [r7, #0]
BaseType_t xProcessTimerNow = pdFALSE;
 8005dd2:	2300      	movs	r3, #0
 8005dd4:	617b      	str	r3, [r7, #20]

	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
 8005dd6:	68fb      	ldr	r3, [r7, #12]
 8005dd8:	68ba      	ldr	r2, [r7, #8]
 8005dda:	605a      	str	r2, [r3, #4]
	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 8005ddc:	68fb      	ldr	r3, [r7, #12]
 8005dde:	68fa      	ldr	r2, [r7, #12]
 8005de0:	611a      	str	r2, [r3, #16]

	if( xNextExpiryTime <= xTimeNow )
 8005de2:	68ba      	ldr	r2, [r7, #8]
 8005de4:	687b      	ldr	r3, [r7, #4]
 8005de6:	429a      	cmp	r2, r3
 8005de8:	d812      	bhi.n	8005e10 <prvInsertTimerInActiveList+0x4c>
	{
		/* Has the expiry time elapsed between the command to start/reset a
		timer was issued, and the time the command was processed? */
		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8005dea:	687a      	ldr	r2, [r7, #4]
 8005dec:	683b      	ldr	r3, [r7, #0]
 8005dee:	1ad2      	subs	r2, r2, r3
 8005df0:	68fb      	ldr	r3, [r7, #12]
 8005df2:	699b      	ldr	r3, [r3, #24]
 8005df4:	429a      	cmp	r2, r3
 8005df6:	d302      	bcc.n	8005dfe <prvInsertTimerInActiveList+0x3a>
		{
			/* The time between a command being issued and the command being
			processed actually exceeds the timers period.  */
			xProcessTimerNow = pdTRUE;
 8005df8:	2301      	movs	r3, #1
 8005dfa:	617b      	str	r3, [r7, #20]
 8005dfc:	e01b      	b.n	8005e36 <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
 8005dfe:	4b10      	ldr	r3, [pc, #64]	; (8005e40 <prvInsertTimerInActiveList+0x7c>)
 8005e00:	681a      	ldr	r2, [r3, #0]
 8005e02:	68fb      	ldr	r3, [r7, #12]
 8005e04:	3304      	adds	r3, #4
 8005e06:	4619      	mov	r1, r3
 8005e08:	4610      	mov	r0, r2
 8005e0a:	f7fe f9d4 	bl	80041b6 <vListInsert>
 8005e0e:	e012      	b.n	8005e36 <prvInsertTimerInActiveList+0x72>
		}
	}
	else
	{
		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
 8005e10:	687a      	ldr	r2, [r7, #4]
 8005e12:	683b      	ldr	r3, [r7, #0]
 8005e14:	429a      	cmp	r2, r3
 8005e16:	d206      	bcs.n	8005e26 <prvInsertTimerInActiveList+0x62>
 8005e18:	68ba      	ldr	r2, [r7, #8]
 8005e1a:	683b      	ldr	r3, [r7, #0]
 8005e1c:	429a      	cmp	r2, r3
 8005e1e:	d302      	bcc.n	8005e26 <prvInsertTimerInActiveList+0x62>
		{
			/* If, since the command was issued, the tick count has overflowed
			but the expiry time has not, then the timer must have already passed
			its expiry time and should be processed immediately. */
			xProcessTimerNow = pdTRUE;
 8005e20:	2301      	movs	r3, #1
 8005e22:	617b      	str	r3, [r7, #20]
 8005e24:	e007      	b.n	8005e36 <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 8005e26:	4b07      	ldr	r3, [pc, #28]	; (8005e44 <prvInsertTimerInActiveList+0x80>)
 8005e28:	681a      	ldr	r2, [r3, #0]
 8005e2a:	68fb      	ldr	r3, [r7, #12]
 8005e2c:	3304      	adds	r3, #4
 8005e2e:	4619      	mov	r1, r3
 8005e30:	4610      	mov	r0, r2
 8005e32:	f7fe f9c0 	bl	80041b6 <vListInsert>
		}
	}

	return xProcessTimerNow;
 8005e36:	697b      	ldr	r3, [r7, #20]
}
 8005e38:	4618      	mov	r0, r3
 8005e3a:	3718      	adds	r7, #24
 8005e3c:	46bd      	mov	sp, r7
 8005e3e:	bd80      	pop	{r7, pc}
 8005e40:	20003e08 	.word	0x20003e08
 8005e44:	20003e04 	.word	0x20003e04

08005e48 <prvProcessReceivedCommands>:
/*-----------------------------------------------------------*/

static void	prvProcessReceivedCommands( void )
{
 8005e48:	b580      	push	{r7, lr}
 8005e4a:	b08e      	sub	sp, #56	; 0x38
 8005e4c:	af02      	add	r7, sp, #8
DaemonTaskMessage_t xMessage;
Timer_t *pxTimer;
BaseType_t xTimerListsWereSwitched, xResult;
TickType_t xTimeNow;

	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 8005e4e:	e0ca      	b.n	8005fe6 <prvProcessReceivedCommands+0x19e>
	{
		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
		{
			/* Negative commands are pended function calls rather than timer
			commands. */
			if( xMessage.xMessageID < ( BaseType_t ) 0 )
 8005e50:	687b      	ldr	r3, [r7, #4]
 8005e52:	2b00      	cmp	r3, #0
 8005e54:	da18      	bge.n	8005e88 <prvProcessReceivedCommands+0x40>
			{
				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
 8005e56:	1d3b      	adds	r3, r7, #4
 8005e58:	3304      	adds	r3, #4
 8005e5a:	62fb      	str	r3, [r7, #44]	; 0x2c

				/* The timer uses the xCallbackParameters member to request a
				callback be executed.  Check the callback is not NULL. */
				configASSERT( pxCallback );
 8005e5c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8005e5e:	2b00      	cmp	r3, #0
 8005e60:	d10a      	bne.n	8005e78 <prvProcessReceivedCommands+0x30>
	__asm volatile
 8005e62:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005e66:	f383 8811 	msr	BASEPRI, r3
 8005e6a:	f3bf 8f6f 	isb	sy
 8005e6e:	f3bf 8f4f 	dsb	sy
 8005e72:	61fb      	str	r3, [r7, #28]
}
 8005e74:	bf00      	nop
 8005e76:	e7fe      	b.n	8005e76 <prvProcessReceivedCommands+0x2e>

				/* Call the function. */
				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
 8005e78:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8005e7a:	681b      	ldr	r3, [r3, #0]
 8005e7c:	6afa      	ldr	r2, [r7, #44]	; 0x2c
 8005e7e:	6850      	ldr	r0, [r2, #4]
 8005e80:	6afa      	ldr	r2, [r7, #44]	; 0x2c
 8005e82:	6892      	ldr	r2, [r2, #8]
 8005e84:	4611      	mov	r1, r2
 8005e86:	4798      	blx	r3
		}
		#endif /* INCLUDE_xTimerPendFunctionCall */

		/* Commands that are positive are timer commands rather than pended
		function calls. */
		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
 8005e88:	687b      	ldr	r3, [r7, #4]
 8005e8a:	2b00      	cmp	r3, #0
 8005e8c:	f2c0 80aa 	blt.w	8005fe4 <prvProcessReceivedCommands+0x19c>
		{
			/* The messages uses the xTimerParameters member to work on a
			software timer. */
			pxTimer = xMessage.u.xTimerParameters.pxTimer;
 8005e90:	68fb      	ldr	r3, [r7, #12]
 8005e92:	62bb      	str	r3, [r7, #40]	; 0x28

			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
 8005e94:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005e96:	695b      	ldr	r3, [r3, #20]
 8005e98:	2b00      	cmp	r3, #0
 8005e9a:	d004      	beq.n	8005ea6 <prvProcessReceivedCommands+0x5e>
			{
				/* The timer is in a list, remove it. */
				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8005e9c:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005e9e:	3304      	adds	r3, #4
 8005ea0:	4618      	mov	r0, r3
 8005ea2:	f7fe f9c1 	bl	8004228 <uxListRemove>
			it must be present in the function call.  prvSampleTimeNow() must be
			called after the message is received from xTimerQueue so there is no
			possibility of a higher priority task adding a message to the message
			queue with a time that is ahead of the timer daemon task (because it
			pre-empted the timer daemon task after the xTimeNow value was set). */
			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 8005ea6:	463b      	mov	r3, r7
 8005ea8:	4618      	mov	r0, r3
 8005eaa:	f7ff ff6b 	bl	8005d84 <prvSampleTimeNow>
 8005eae:	6278      	str	r0, [r7, #36]	; 0x24

			switch( xMessage.xMessageID )
 8005eb0:	687b      	ldr	r3, [r7, #4]
 8005eb2:	2b09      	cmp	r3, #9
 8005eb4:	f200 8097 	bhi.w	8005fe6 <prvProcessReceivedCommands+0x19e>
 8005eb8:	a201      	add	r2, pc, #4	; (adr r2, 8005ec0 <prvProcessReceivedCommands+0x78>)
 8005eba:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8005ebe:	bf00      	nop
 8005ec0:	08005ee9 	.word	0x08005ee9
 8005ec4:	08005ee9 	.word	0x08005ee9
 8005ec8:	08005ee9 	.word	0x08005ee9
 8005ecc:	08005f5d 	.word	0x08005f5d
 8005ed0:	08005f71 	.word	0x08005f71
 8005ed4:	08005fbb 	.word	0x08005fbb
 8005ed8:	08005ee9 	.word	0x08005ee9
 8005edc:	08005ee9 	.word	0x08005ee9
 8005ee0:	08005f5d 	.word	0x08005f5d
 8005ee4:	08005f71 	.word	0x08005f71
				case tmrCOMMAND_START_FROM_ISR :
				case tmrCOMMAND_RESET :
				case tmrCOMMAND_RESET_FROM_ISR :
				case tmrCOMMAND_START_DONT_TRACE :
					/* Start or restart a timer. */
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 8005ee8:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005eea:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8005eee:	f043 0301 	orr.w	r3, r3, #1
 8005ef2:	b2da      	uxtb	r2, r3
 8005ef4:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005ef6:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
 8005efa:	68ba      	ldr	r2, [r7, #8]
 8005efc:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005efe:	699b      	ldr	r3, [r3, #24]
 8005f00:	18d1      	adds	r1, r2, r3
 8005f02:	68bb      	ldr	r3, [r7, #8]
 8005f04:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 8005f06:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8005f08:	f7ff ff5c 	bl	8005dc4 <prvInsertTimerInActiveList>
 8005f0c:	4603      	mov	r3, r0
 8005f0e:	2b00      	cmp	r3, #0
 8005f10:	d069      	beq.n	8005fe6 <prvProcessReceivedCommands+0x19e>
					{
						/* The timer expired before it was added to the active
						timer list.  Process it now. */
						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8005f12:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005f14:	6a1b      	ldr	r3, [r3, #32]
 8005f16:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8005f18:	4798      	blx	r3
						traceTIMER_EXPIRED( pxTimer );

						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 8005f1a:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005f1c:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8005f20:	f003 0304 	and.w	r3, r3, #4
 8005f24:	2b00      	cmp	r3, #0
 8005f26:	d05e      	beq.n	8005fe6 <prvProcessReceivedCommands+0x19e>
						{
							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
 8005f28:	68ba      	ldr	r2, [r7, #8]
 8005f2a:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005f2c:	699b      	ldr	r3, [r3, #24]
 8005f2e:	441a      	add	r2, r3
 8005f30:	2300      	movs	r3, #0
 8005f32:	9300      	str	r3, [sp, #0]
 8005f34:	2300      	movs	r3, #0
 8005f36:	2100      	movs	r1, #0
 8005f38:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8005f3a:	f7ff fe05 	bl	8005b48 <xTimerGenericCommand>
 8005f3e:	6238      	str	r0, [r7, #32]
							configASSERT( xResult );
 8005f40:	6a3b      	ldr	r3, [r7, #32]
 8005f42:	2b00      	cmp	r3, #0
 8005f44:	d14f      	bne.n	8005fe6 <prvProcessReceivedCommands+0x19e>
	__asm volatile
 8005f46:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005f4a:	f383 8811 	msr	BASEPRI, r3
 8005f4e:	f3bf 8f6f 	isb	sy
 8005f52:	f3bf 8f4f 	dsb	sy
 8005f56:	61bb      	str	r3, [r7, #24]
}
 8005f58:	bf00      	nop
 8005f5a:	e7fe      	b.n	8005f5a <prvProcessReceivedCommands+0x112>
					break;

				case tmrCOMMAND_STOP :
				case tmrCOMMAND_STOP_FROM_ISR :
					/* The timer has already been removed from the active list. */
					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8005f5c:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005f5e:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8005f62:	f023 0301 	bic.w	r3, r3, #1
 8005f66:	b2da      	uxtb	r2, r3
 8005f68:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005f6a:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
					break;
 8005f6e:	e03a      	b.n	8005fe6 <prvProcessReceivedCommands+0x19e>

				case tmrCOMMAND_CHANGE_PERIOD :
				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 8005f70:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005f72:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8005f76:	f043 0301 	orr.w	r3, r3, #1
 8005f7a:	b2da      	uxtb	r2, r3
 8005f7c:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005f7e:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
 8005f82:	68ba      	ldr	r2, [r7, #8]
 8005f84:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005f86:	619a      	str	r2, [r3, #24]
					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
 8005f88:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005f8a:	699b      	ldr	r3, [r3, #24]
 8005f8c:	2b00      	cmp	r3, #0
 8005f8e:	d10a      	bne.n	8005fa6 <prvProcessReceivedCommands+0x15e>
	__asm volatile
 8005f90:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005f94:	f383 8811 	msr	BASEPRI, r3
 8005f98:	f3bf 8f6f 	isb	sy
 8005f9c:	f3bf 8f4f 	dsb	sy
 8005fa0:	617b      	str	r3, [r7, #20]
}
 8005fa2:	bf00      	nop
 8005fa4:	e7fe      	b.n	8005fa4 <prvProcessReceivedCommands+0x15c>
					be longer or shorter than the old one.  The command time is
					therefore set to the current time, and as the period cannot
					be zero the next expiry time can only be in the future,
					meaning (unlike for the xTimerStart() case above) there is
					no fail case that needs to be handled here. */
					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
 8005fa6:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005fa8:	699a      	ldr	r2, [r3, #24]
 8005faa:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005fac:	18d1      	adds	r1, r2, r3
 8005fae:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005fb0:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 8005fb2:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8005fb4:	f7ff ff06 	bl	8005dc4 <prvInsertTimerInActiveList>
					break;
 8005fb8:	e015      	b.n	8005fe6 <prvProcessReceivedCommands+0x19e>
					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
					{
						/* The timer has already been removed from the active list,
						just free up the memory if the memory was dynamically
						allocated. */
						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
 8005fba:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005fbc:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8005fc0:	f003 0302 	and.w	r3, r3, #2
 8005fc4:	2b00      	cmp	r3, #0
 8005fc6:	d103      	bne.n	8005fd0 <prvProcessReceivedCommands+0x188>
						{
							vPortFree( pxTimer );
 8005fc8:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8005fca:	f000 fbb9 	bl	8006740 <vPortFree>
 8005fce:	e00a      	b.n	8005fe6 <prvProcessReceivedCommands+0x19e>
						}
						else
						{
							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8005fd0:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005fd2:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8005fd6:	f023 0301 	bic.w	r3, r3, #1
 8005fda:	b2da      	uxtb	r2, r3
 8005fdc:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005fde:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
						no need to free the memory - just mark the timer as
						"not active". */
						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
					}
					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
					break;
 8005fe2:	e000      	b.n	8005fe6 <prvProcessReceivedCommands+0x19e>

				default	:
					/* Don't expect to get here. */
					break;
			}
		}
 8005fe4:	bf00      	nop
	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 8005fe6:	4b08      	ldr	r3, [pc, #32]	; (8006008 <prvProcessReceivedCommands+0x1c0>)
 8005fe8:	681b      	ldr	r3, [r3, #0]
 8005fea:	1d39      	adds	r1, r7, #4
 8005fec:	2200      	movs	r2, #0
 8005fee:	4618      	mov	r0, r3
 8005ff0:	f7fe fbe2 	bl	80047b8 <xQueueReceive>
 8005ff4:	4603      	mov	r3, r0
 8005ff6:	2b00      	cmp	r3, #0
 8005ff8:	f47f af2a 	bne.w	8005e50 <prvProcessReceivedCommands+0x8>
	}
}
 8005ffc:	bf00      	nop
 8005ffe:	bf00      	nop
 8006000:	3730      	adds	r7, #48	; 0x30
 8006002:	46bd      	mov	sp, r7
 8006004:	bd80      	pop	{r7, pc}
 8006006:	bf00      	nop
 8006008:	20003e0c 	.word	0x20003e0c

0800600c <prvSwitchTimerLists>:
/*-----------------------------------------------------------*/

static void prvSwitchTimerLists( void )
{
 800600c:	b580      	push	{r7, lr}
 800600e:	b088      	sub	sp, #32
 8006010:	af02      	add	r7, sp, #8

	/* The tick count has overflowed.  The timer lists must be switched.
	If there are any timers still referenced from the current timer list
	then they must have expired and should be processed before the lists
	are switched. */
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 8006012:	e048      	b.n	80060a6 <prvSwitchTimerLists+0x9a>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 8006014:	4b2d      	ldr	r3, [pc, #180]	; (80060cc <prvSwitchTimerLists+0xc0>)
 8006016:	681b      	ldr	r3, [r3, #0]
 8006018:	68db      	ldr	r3, [r3, #12]
 800601a:	681b      	ldr	r3, [r3, #0]
 800601c:	613b      	str	r3, [r7, #16]

		/* Remove the timer from the list. */
		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 800601e:	4b2b      	ldr	r3, [pc, #172]	; (80060cc <prvSwitchTimerLists+0xc0>)
 8006020:	681b      	ldr	r3, [r3, #0]
 8006022:	68db      	ldr	r3, [r3, #12]
 8006024:	68db      	ldr	r3, [r3, #12]
 8006026:	60fb      	str	r3, [r7, #12]
		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8006028:	68fb      	ldr	r3, [r7, #12]
 800602a:	3304      	adds	r3, #4
 800602c:	4618      	mov	r0, r3
 800602e:	f7fe f8fb 	bl	8004228 <uxListRemove>
		traceTIMER_EXPIRED( pxTimer );

		/* Execute its callback, then send a command to restart the timer if
		it is an auto-reload timer.  It cannot be restarted here as the lists
		have not yet been switched. */
		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8006032:	68fb      	ldr	r3, [r7, #12]
 8006034:	6a1b      	ldr	r3, [r3, #32]
 8006036:	68f8      	ldr	r0, [r7, #12]
 8006038:	4798      	blx	r3

		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 800603a:	68fb      	ldr	r3, [r7, #12]
 800603c:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8006040:	f003 0304 	and.w	r3, r3, #4
 8006044:	2b00      	cmp	r3, #0
 8006046:	d02e      	beq.n	80060a6 <prvSwitchTimerLists+0x9a>
			the timer going into the same timer list then it has already expired
			and the timer should be re-inserted into the current list so it is
			processed again within this loop.  Otherwise a command should be sent
			to restart the timer to ensure it is only inserted into a list after
			the lists have been swapped. */
			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
 8006048:	68fb      	ldr	r3, [r7, #12]
 800604a:	699b      	ldr	r3, [r3, #24]
 800604c:	693a      	ldr	r2, [r7, #16]
 800604e:	4413      	add	r3, r2
 8006050:	60bb      	str	r3, [r7, #8]
			if( xReloadTime > xNextExpireTime )
 8006052:	68ba      	ldr	r2, [r7, #8]
 8006054:	693b      	ldr	r3, [r7, #16]
 8006056:	429a      	cmp	r2, r3
 8006058:	d90e      	bls.n	8006078 <prvSwitchTimerLists+0x6c>
			{
				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
 800605a:	68fb      	ldr	r3, [r7, #12]
 800605c:	68ba      	ldr	r2, [r7, #8]
 800605e:	605a      	str	r2, [r3, #4]
				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 8006060:	68fb      	ldr	r3, [r7, #12]
 8006062:	68fa      	ldr	r2, [r7, #12]
 8006064:	611a      	str	r2, [r3, #16]
				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 8006066:	4b19      	ldr	r3, [pc, #100]	; (80060cc <prvSwitchTimerLists+0xc0>)
 8006068:	681a      	ldr	r2, [r3, #0]
 800606a:	68fb      	ldr	r3, [r7, #12]
 800606c:	3304      	adds	r3, #4
 800606e:	4619      	mov	r1, r3
 8006070:	4610      	mov	r0, r2
 8006072:	f7fe f8a0 	bl	80041b6 <vListInsert>
 8006076:	e016      	b.n	80060a6 <prvSwitchTimerLists+0x9a>
			}
			else
			{
				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 8006078:	2300      	movs	r3, #0
 800607a:	9300      	str	r3, [sp, #0]
 800607c:	2300      	movs	r3, #0
 800607e:	693a      	ldr	r2, [r7, #16]
 8006080:	2100      	movs	r1, #0
 8006082:	68f8      	ldr	r0, [r7, #12]
 8006084:	f7ff fd60 	bl	8005b48 <xTimerGenericCommand>
 8006088:	6078      	str	r0, [r7, #4]
				configASSERT( xResult );
 800608a:	687b      	ldr	r3, [r7, #4]
 800608c:	2b00      	cmp	r3, #0
 800608e:	d10a      	bne.n	80060a6 <prvSwitchTimerLists+0x9a>
	__asm volatile
 8006090:	f04f 0350 	mov.w	r3, #80	; 0x50
 8006094:	f383 8811 	msr	BASEPRI, r3
 8006098:	f3bf 8f6f 	isb	sy
 800609c:	f3bf 8f4f 	dsb	sy
 80060a0:	603b      	str	r3, [r7, #0]
}
 80060a2:	bf00      	nop
 80060a4:	e7fe      	b.n	80060a4 <prvSwitchTimerLists+0x98>
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 80060a6:	4b09      	ldr	r3, [pc, #36]	; (80060cc <prvSwitchTimerLists+0xc0>)
 80060a8:	681b      	ldr	r3, [r3, #0]
 80060aa:	681b      	ldr	r3, [r3, #0]
 80060ac:	2b00      	cmp	r3, #0
 80060ae:	d1b1      	bne.n	8006014 <prvSwitchTimerLists+0x8>
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxTemp = pxCurrentTimerList;
 80060b0:	4b06      	ldr	r3, [pc, #24]	; (80060cc <prvSwitchTimerLists+0xc0>)
 80060b2:	681b      	ldr	r3, [r3, #0]
 80060b4:	617b      	str	r3, [r7, #20]
	pxCurrentTimerList = pxOverflowTimerList;
 80060b6:	4b06      	ldr	r3, [pc, #24]	; (80060d0 <prvSwitchTimerLists+0xc4>)
 80060b8:	681b      	ldr	r3, [r3, #0]
 80060ba:	4a04      	ldr	r2, [pc, #16]	; (80060cc <prvSwitchTimerLists+0xc0>)
 80060bc:	6013      	str	r3, [r2, #0]
	pxOverflowTimerList = pxTemp;
 80060be:	4a04      	ldr	r2, [pc, #16]	; (80060d0 <prvSwitchTimerLists+0xc4>)
 80060c0:	697b      	ldr	r3, [r7, #20]
 80060c2:	6013      	str	r3, [r2, #0]
}
 80060c4:	bf00      	nop
 80060c6:	3718      	adds	r7, #24
 80060c8:	46bd      	mov	sp, r7
 80060ca:	bd80      	pop	{r7, pc}
 80060cc:	20003e04 	.word	0x20003e04
 80060d0:	20003e08 	.word	0x20003e08

080060d4 <prvCheckForValidListAndQueue>:
/*-----------------------------------------------------------*/

static void prvCheckForValidListAndQueue( void )
{
 80060d4:	b580      	push	{r7, lr}
 80060d6:	b082      	sub	sp, #8
 80060d8:	af02      	add	r7, sp, #8
	/* Check that the list from which active timers are referenced, and the
	queue used to communicate with the timer service, have been
	initialised. */
	taskENTER_CRITICAL();
 80060da:	f000 f96b 	bl	80063b4 <vPortEnterCritical>
	{
		if( xTimerQueue == NULL )
 80060de:	4b15      	ldr	r3, [pc, #84]	; (8006134 <prvCheckForValidListAndQueue+0x60>)
 80060e0:	681b      	ldr	r3, [r3, #0]
 80060e2:	2b00      	cmp	r3, #0
 80060e4:	d120      	bne.n	8006128 <prvCheckForValidListAndQueue+0x54>
		{
			vListInitialise( &xActiveTimerList1 );
 80060e6:	4814      	ldr	r0, [pc, #80]	; (8006138 <prvCheckForValidListAndQueue+0x64>)
 80060e8:	f7fe f814 	bl	8004114 <vListInitialise>
			vListInitialise( &xActiveTimerList2 );
 80060ec:	4813      	ldr	r0, [pc, #76]	; (800613c <prvCheckForValidListAndQueue+0x68>)
 80060ee:	f7fe f811 	bl	8004114 <vListInitialise>
			pxCurrentTimerList = &xActiveTimerList1;
 80060f2:	4b13      	ldr	r3, [pc, #76]	; (8006140 <prvCheckForValidListAndQueue+0x6c>)
 80060f4:	4a10      	ldr	r2, [pc, #64]	; (8006138 <prvCheckForValidListAndQueue+0x64>)
 80060f6:	601a      	str	r2, [r3, #0]
			pxOverflowTimerList = &xActiveTimerList2;
 80060f8:	4b12      	ldr	r3, [pc, #72]	; (8006144 <prvCheckForValidListAndQueue+0x70>)
 80060fa:	4a10      	ldr	r2, [pc, #64]	; (800613c <prvCheckForValidListAndQueue+0x68>)
 80060fc:	601a      	str	r2, [r3, #0]
				/* The timer queue is allocated statically in case
				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */

				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
 80060fe:	2300      	movs	r3, #0
 8006100:	9300      	str	r3, [sp, #0]
 8006102:	4b11      	ldr	r3, [pc, #68]	; (8006148 <prvCheckForValidListAndQueue+0x74>)
 8006104:	4a11      	ldr	r2, [pc, #68]	; (800614c <prvCheckForValidListAndQueue+0x78>)
 8006106:	2110      	movs	r1, #16
 8006108:	200a      	movs	r0, #10
 800610a:	f7fe f91f 	bl	800434c <xQueueGenericCreateStatic>
 800610e:	4603      	mov	r3, r0
 8006110:	4a08      	ldr	r2, [pc, #32]	; (8006134 <prvCheckForValidListAndQueue+0x60>)
 8006112:	6013      	str	r3, [r2, #0]
			}
			#endif

			#if ( configQUEUE_REGISTRY_SIZE > 0 )
			{
				if( xTimerQueue != NULL )
 8006114:	4b07      	ldr	r3, [pc, #28]	; (8006134 <prvCheckForValidListAndQueue+0x60>)
 8006116:	681b      	ldr	r3, [r3, #0]
 8006118:	2b00      	cmp	r3, #0
 800611a:	d005      	beq.n	8006128 <prvCheckForValidListAndQueue+0x54>
				{
					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
 800611c:	4b05      	ldr	r3, [pc, #20]	; (8006134 <prvCheckForValidListAndQueue+0x60>)
 800611e:	681b      	ldr	r3, [r3, #0]
 8006120:	490b      	ldr	r1, [pc, #44]	; (8006150 <prvCheckForValidListAndQueue+0x7c>)
 8006122:	4618      	mov	r0, r3
 8006124:	f7fe fd38 	bl	8004b98 <vQueueAddToRegistry>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 8006128:	f000 f974 	bl	8006414 <vPortExitCritical>
}
 800612c:	bf00      	nop
 800612e:	46bd      	mov	sp, r7
 8006130:	bd80      	pop	{r7, pc}
 8006132:	bf00      	nop
 8006134:	20003e0c 	.word	0x20003e0c
 8006138:	20003ddc 	.word	0x20003ddc
 800613c:	20003df0 	.word	0x20003df0
 8006140:	20003e04 	.word	0x20003e04
 8006144:	20003e08 	.word	0x20003e08
 8006148:	20003eb8 	.word	0x20003eb8
 800614c:	20003e18 	.word	0x20003e18
 8006150:	08006c88 	.word	0x08006c88

08006154 <pxPortInitialiseStack>:

/*
 * See header file for description.
 */
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
 8006154:	b480      	push	{r7}
 8006156:	b085      	sub	sp, #20
 8006158:	af00      	add	r7, sp, #0
 800615a:	60f8      	str	r0, [r7, #12]
 800615c:	60b9      	str	r1, [r7, #8]
 800615e:	607a      	str	r2, [r7, #4]
	/* Simulate the stack frame as it would be created by a context switch
	interrupt. */

	/* Offset added to account for the way the MCU uses the stack on entry/exit
	of interrupts, and to ensure alignment. */
	pxTopOfStack--;
 8006160:	68fb      	ldr	r3, [r7, #12]
 8006162:	3b04      	subs	r3, #4
 8006164:	60fb      	str	r3, [r7, #12]

	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
 8006166:	68fb      	ldr	r3, [r7, #12]
 8006168:	f04f 7280 	mov.w	r2, #16777216	; 0x1000000
 800616c:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 800616e:	68fb      	ldr	r3, [r7, #12]
 8006170:	3b04      	subs	r3, #4
 8006172:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
 8006174:	68bb      	ldr	r3, [r7, #8]
 8006176:	f023 0201 	bic.w	r2, r3, #1
 800617a:	68fb      	ldr	r3, [r7, #12]
 800617c:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 800617e:	68fb      	ldr	r3, [r7, #12]
 8006180:	3b04      	subs	r3, #4
 8006182:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
 8006184:	4a0c      	ldr	r2, [pc, #48]	; (80061b8 <pxPortInitialiseStack+0x64>)
 8006186:	68fb      	ldr	r3, [r7, #12]
 8006188:	601a      	str	r2, [r3, #0]

	/* Save code space by skipping register initialisation. */
	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
 800618a:	68fb      	ldr	r3, [r7, #12]
 800618c:	3b14      	subs	r3, #20
 800618e:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
 8006190:	687a      	ldr	r2, [r7, #4]
 8006192:	68fb      	ldr	r3, [r7, #12]
 8006194:	601a      	str	r2, [r3, #0]

	/* A save method is being used that requires each task to maintain its
	own exec return value. */
	pxTopOfStack--;
 8006196:	68fb      	ldr	r3, [r7, #12]
 8006198:	3b04      	subs	r3, #4
 800619a:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = portINITIAL_EXC_RETURN;
 800619c:	68fb      	ldr	r3, [r7, #12]
 800619e:	f06f 0202 	mvn.w	r2, #2
 80061a2:	601a      	str	r2, [r3, #0]

	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
 80061a4:	68fb      	ldr	r3, [r7, #12]
 80061a6:	3b20      	subs	r3, #32
 80061a8:	60fb      	str	r3, [r7, #12]

	return pxTopOfStack;
 80061aa:	68fb      	ldr	r3, [r7, #12]
}
 80061ac:	4618      	mov	r0, r3
 80061ae:	3714      	adds	r7, #20
 80061b0:	46bd      	mov	sp, r7
 80061b2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80061b6:	4770      	bx	lr
 80061b8:	080061bd 	.word	0x080061bd

080061bc <prvTaskExitError>:
/*-----------------------------------------------------------*/

static void prvTaskExitError( void )
{
 80061bc:	b480      	push	{r7}
 80061be:	b085      	sub	sp, #20
 80061c0:	af00      	add	r7, sp, #0
volatile uint32_t ulDummy = 0;
 80061c2:	2300      	movs	r3, #0
 80061c4:	607b      	str	r3, [r7, #4]
	its caller as there is nothing to return to.  If a task wants to exit it
	should instead call vTaskDelete( NULL ).

	Artificially force an assert() to be triggered if configASSERT() is
	defined, then stop here so application writers can catch the error. */
	configASSERT( uxCriticalNesting == ~0UL );
 80061c6:	4b12      	ldr	r3, [pc, #72]	; (8006210 <prvTaskExitError+0x54>)
 80061c8:	681b      	ldr	r3, [r3, #0]
 80061ca:	f1b3 3fff 	cmp.w	r3, #4294967295
 80061ce:	d00a      	beq.n	80061e6 <prvTaskExitError+0x2a>
	__asm volatile
 80061d0:	f04f 0350 	mov.w	r3, #80	; 0x50
 80061d4:	f383 8811 	msr	BASEPRI, r3
 80061d8:	f3bf 8f6f 	isb	sy
 80061dc:	f3bf 8f4f 	dsb	sy
 80061e0:	60fb      	str	r3, [r7, #12]
}
 80061e2:	bf00      	nop
 80061e4:	e7fe      	b.n	80061e4 <prvTaskExitError+0x28>
	__asm volatile
 80061e6:	f04f 0350 	mov.w	r3, #80	; 0x50
 80061ea:	f383 8811 	msr	BASEPRI, r3
 80061ee:	f3bf 8f6f 	isb	sy
 80061f2:	f3bf 8f4f 	dsb	sy
 80061f6:	60bb      	str	r3, [r7, #8]
}
 80061f8:	bf00      	nop
	portDISABLE_INTERRUPTS();
	while( ulDummy == 0 )
 80061fa:	bf00      	nop
 80061fc:	687b      	ldr	r3, [r7, #4]
 80061fe:	2b00      	cmp	r3, #0
 8006200:	d0fc      	beq.n	80061fc <prvTaskExitError+0x40>
		about code appearing after this function is called - making ulDummy
		volatile makes the compiler think the function could return and
		therefore not output an 'unreachable code' warning for code that appears
		after it. */
	}
}
 8006202:	bf00      	nop
 8006204:	bf00      	nop
 8006206:	3714      	adds	r7, #20
 8006208:	46bd      	mov	sp, r7
 800620a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800620e:	4770      	bx	lr
 8006210:	2000001c 	.word	0x2000001c
	...

08006220 <SVC_Handler>:
/*-----------------------------------------------------------*/

void vPortSVCHandler( void )
{
	__asm volatile (
 8006220:	4b07      	ldr	r3, [pc, #28]	; (8006240 <pxCurrentTCBConst2>)
 8006222:	6819      	ldr	r1, [r3, #0]
 8006224:	6808      	ldr	r0, [r1, #0]
 8006226:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 800622a:	f380 8809 	msr	PSP, r0
 800622e:	f3bf 8f6f 	isb	sy
 8006232:	f04f 0000 	mov.w	r0, #0
 8006236:	f380 8811 	msr	BASEPRI, r0
 800623a:	4770      	bx	lr
 800623c:	f3af 8000 	nop.w

08006240 <pxCurrentTCBConst2>:
 8006240:	200038dc 	.word	0x200038dc
					"	bx r14							\n"
					"									\n"
					"	.align 4						\n"
					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
				);
}
 8006244:	bf00      	nop
 8006246:	bf00      	nop

08006248 <prvPortStartFirstTask>:
{
	/* Start the first task.  This also clears the bit that indicates the FPU is
	in use in case the FPU was used before the scheduler was started - which
	would otherwise result in the unnecessary leaving of space in the SVC stack
	for lazy saving of FPU registers. */
	__asm volatile(
 8006248:	4808      	ldr	r0, [pc, #32]	; (800626c <prvPortStartFirstTask+0x24>)
 800624a:	6800      	ldr	r0, [r0, #0]
 800624c:	6800      	ldr	r0, [r0, #0]
 800624e:	f380 8808 	msr	MSP, r0
 8006252:	f04f 0000 	mov.w	r0, #0
 8006256:	f380 8814 	msr	CONTROL, r0
 800625a:	b662      	cpsie	i
 800625c:	b661      	cpsie	f
 800625e:	f3bf 8f4f 	dsb	sy
 8006262:	f3bf 8f6f 	isb	sy
 8006266:	df00      	svc	0
 8006268:	bf00      	nop
					" dsb					\n"
					" isb					\n"
					" svc 0					\n" /* System call to start first task. */
					" nop					\n"
				);
}
 800626a:	bf00      	nop
 800626c:	e000ed08 	.word	0xe000ed08

08006270 <xPortStartScheduler>:

/*
 * See header file for description.
 */
BaseType_t xPortStartScheduler( void )
{
 8006270:	b580      	push	{r7, lr}
 8006272:	b086      	sub	sp, #24
 8006274:	af00      	add	r7, sp, #0
	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );

	/* This port can be used on all revisions of the Cortex-M7 core other than
	the r0p1 parts.  r0p1 parts should use the port from the
	/source/portable/GCC/ARM_CM7/r0p1 directory. */
	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
 8006276:	4b46      	ldr	r3, [pc, #280]	; (8006390 <xPortStartScheduler+0x120>)
 8006278:	681b      	ldr	r3, [r3, #0]
 800627a:	4a46      	ldr	r2, [pc, #280]	; (8006394 <xPortStartScheduler+0x124>)
 800627c:	4293      	cmp	r3, r2
 800627e:	d10a      	bne.n	8006296 <xPortStartScheduler+0x26>
	__asm volatile
 8006280:	f04f 0350 	mov.w	r3, #80	; 0x50
 8006284:	f383 8811 	msr	BASEPRI, r3
 8006288:	f3bf 8f6f 	isb	sy
 800628c:	f3bf 8f4f 	dsb	sy
 8006290:	613b      	str	r3, [r7, #16]
}
 8006292:	bf00      	nop
 8006294:	e7fe      	b.n	8006294 <xPortStartScheduler+0x24>
	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 8006296:	4b3e      	ldr	r3, [pc, #248]	; (8006390 <xPortStartScheduler+0x120>)
 8006298:	681b      	ldr	r3, [r3, #0]
 800629a:	4a3f      	ldr	r2, [pc, #252]	; (8006398 <xPortStartScheduler+0x128>)
 800629c:	4293      	cmp	r3, r2
 800629e:	d10a      	bne.n	80062b6 <xPortStartScheduler+0x46>
	__asm volatile
 80062a0:	f04f 0350 	mov.w	r3, #80	; 0x50
 80062a4:	f383 8811 	msr	BASEPRI, r3
 80062a8:	f3bf 8f6f 	isb	sy
 80062ac:	f3bf 8f4f 	dsb	sy
 80062b0:	60fb      	str	r3, [r7, #12]
}
 80062b2:	bf00      	nop
 80062b4:	e7fe      	b.n	80062b4 <xPortStartScheduler+0x44>

	#if( configASSERT_DEFINED == 1 )
	{
		volatile uint32_t ulOriginalPriority;
		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
 80062b6:	4b39      	ldr	r3, [pc, #228]	; (800639c <xPortStartScheduler+0x12c>)
 80062b8:	617b      	str	r3, [r7, #20]
		functions can be called.  ISR safe functions are those that end in
		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
		ensure interrupt entry is as fast and simple as possible.

		Save the interrupt priority value that is about to be clobbered. */
		ulOriginalPriority = *pucFirstUserPriorityRegister;
 80062ba:	697b      	ldr	r3, [r7, #20]
 80062bc:	781b      	ldrb	r3, [r3, #0]
 80062be:	b2db      	uxtb	r3, r3
 80062c0:	607b      	str	r3, [r7, #4]

		/* Determine the number of priority bits available.  First write to all
		possible bits. */
		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 80062c2:	697b      	ldr	r3, [r7, #20]
 80062c4:	22ff      	movs	r2, #255	; 0xff
 80062c6:	701a      	strb	r2, [r3, #0]

		/* Read the value back to see how many bits stuck. */
		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
 80062c8:	697b      	ldr	r3, [r7, #20]
 80062ca:	781b      	ldrb	r3, [r3, #0]
 80062cc:	b2db      	uxtb	r3, r3
 80062ce:	70fb      	strb	r3, [r7, #3]

		/* Use the same mask on the maximum system call priority. */
		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 80062d0:	78fb      	ldrb	r3, [r7, #3]
 80062d2:	b2db      	uxtb	r3, r3
 80062d4:	f003 0350 	and.w	r3, r3, #80	; 0x50
 80062d8:	b2da      	uxtb	r2, r3
 80062da:	4b31      	ldr	r3, [pc, #196]	; (80063a0 <xPortStartScheduler+0x130>)
 80062dc:	701a      	strb	r2, [r3, #0]

		/* Calculate the maximum acceptable priority group value for the number
		of bits read back. */
		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
 80062de:	4b31      	ldr	r3, [pc, #196]	; (80063a4 <xPortStartScheduler+0x134>)
 80062e0:	2207      	movs	r2, #7
 80062e2:	601a      	str	r2, [r3, #0]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 80062e4:	e009      	b.n	80062fa <xPortStartScheduler+0x8a>
		{
			ulMaxPRIGROUPValue--;
 80062e6:	4b2f      	ldr	r3, [pc, #188]	; (80063a4 <xPortStartScheduler+0x134>)
 80062e8:	681b      	ldr	r3, [r3, #0]
 80062ea:	3b01      	subs	r3, #1
 80062ec:	4a2d      	ldr	r2, [pc, #180]	; (80063a4 <xPortStartScheduler+0x134>)
 80062ee:	6013      	str	r3, [r2, #0]
			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
 80062f0:	78fb      	ldrb	r3, [r7, #3]
 80062f2:	b2db      	uxtb	r3, r3
 80062f4:	005b      	lsls	r3, r3, #1
 80062f6:	b2db      	uxtb	r3, r3
 80062f8:	70fb      	strb	r3, [r7, #3]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 80062fa:	78fb      	ldrb	r3, [r7, #3]
 80062fc:	b2db      	uxtb	r3, r3
 80062fe:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8006302:	2b80      	cmp	r3, #128	; 0x80
 8006304:	d0ef      	beq.n	80062e6 <xPortStartScheduler+0x76>
		#ifdef configPRIO_BITS
		{
			/* Check the FreeRTOS configuration that defines the number of
			priority bits matches the number of priority bits actually queried
			from the hardware. */
			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
 8006306:	4b27      	ldr	r3, [pc, #156]	; (80063a4 <xPortStartScheduler+0x134>)
 8006308:	681b      	ldr	r3, [r3, #0]
 800630a:	f1c3 0307 	rsb	r3, r3, #7
 800630e:	2b04      	cmp	r3, #4
 8006310:	d00a      	beq.n	8006328 <xPortStartScheduler+0xb8>
	__asm volatile
 8006312:	f04f 0350 	mov.w	r3, #80	; 0x50
 8006316:	f383 8811 	msr	BASEPRI, r3
 800631a:	f3bf 8f6f 	isb	sy
 800631e:	f3bf 8f4f 	dsb	sy
 8006322:	60bb      	str	r3, [r7, #8]
}
 8006324:	bf00      	nop
 8006326:	e7fe      	b.n	8006326 <xPortStartScheduler+0xb6>
		}
		#endif

		/* Shift the priority group value back to its position within the AIRCR
		register. */
		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
 8006328:	4b1e      	ldr	r3, [pc, #120]	; (80063a4 <xPortStartScheduler+0x134>)
 800632a:	681b      	ldr	r3, [r3, #0]
 800632c:	021b      	lsls	r3, r3, #8
 800632e:	4a1d      	ldr	r2, [pc, #116]	; (80063a4 <xPortStartScheduler+0x134>)
 8006330:	6013      	str	r3, [r2, #0]
		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
 8006332:	4b1c      	ldr	r3, [pc, #112]	; (80063a4 <xPortStartScheduler+0x134>)
 8006334:	681b      	ldr	r3, [r3, #0]
 8006336:	f403 63e0 	and.w	r3, r3, #1792	; 0x700
 800633a:	4a1a      	ldr	r2, [pc, #104]	; (80063a4 <xPortStartScheduler+0x134>)
 800633c:	6013      	str	r3, [r2, #0]

		/* Restore the clobbered interrupt priority register to its original
		value. */
		*pucFirstUserPriorityRegister = ulOriginalPriority;
 800633e:	687b      	ldr	r3, [r7, #4]
 8006340:	b2da      	uxtb	r2, r3
 8006342:	697b      	ldr	r3, [r7, #20]
 8006344:	701a      	strb	r2, [r3, #0]
	}
	#endif /* conifgASSERT_DEFINED */

	/* Make PendSV and SysTick the lowest priority interrupts. */
	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
 8006346:	4b18      	ldr	r3, [pc, #96]	; (80063a8 <xPortStartScheduler+0x138>)
 8006348:	681b      	ldr	r3, [r3, #0]
 800634a:	4a17      	ldr	r2, [pc, #92]	; (80063a8 <xPortStartScheduler+0x138>)
 800634c:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
 8006350:	6013      	str	r3, [r2, #0]
	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
 8006352:	4b15      	ldr	r3, [pc, #84]	; (80063a8 <xPortStartScheduler+0x138>)
 8006354:	681b      	ldr	r3, [r3, #0]
 8006356:	4a14      	ldr	r2, [pc, #80]	; (80063a8 <xPortStartScheduler+0x138>)
 8006358:	f043 4370 	orr.w	r3, r3, #4026531840	; 0xf0000000
 800635c:	6013      	str	r3, [r2, #0]

	/* Start the timer that generates the tick ISR.  Interrupts are disabled
	here already. */
	vPortSetupTimerInterrupt();
 800635e:	f000 f8dd 	bl	800651c <vPortSetupTimerInterrupt>

	/* Initialise the critical nesting count ready for the first task. */
	uxCriticalNesting = 0;
 8006362:	4b12      	ldr	r3, [pc, #72]	; (80063ac <xPortStartScheduler+0x13c>)
 8006364:	2200      	movs	r2, #0
 8006366:	601a      	str	r2, [r3, #0]

	/* Ensure the VFP is enabled - it should be anyway. */
	vPortEnableVFP();
 8006368:	f000 f8fc 	bl	8006564 <vPortEnableVFP>

	/* Lazy save always. */
	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
 800636c:	4b10      	ldr	r3, [pc, #64]	; (80063b0 <xPortStartScheduler+0x140>)
 800636e:	681b      	ldr	r3, [r3, #0]
 8006370:	4a0f      	ldr	r2, [pc, #60]	; (80063b0 <xPortStartScheduler+0x140>)
 8006372:	f043 4340 	orr.w	r3, r3, #3221225472	; 0xc0000000
 8006376:	6013      	str	r3, [r2, #0]

	/* Start the first task. */
	prvPortStartFirstTask();
 8006378:	f7ff ff66 	bl	8006248 <prvPortStartFirstTask>
	exit error function to prevent compiler warnings about a static function
	not being called in the case that the application writer overrides this
	functionality by defining configTASK_RETURN_ADDRESS.  Call
	vTaskSwitchContext() so link time optimisation does not remove the
	symbol. */
	vTaskSwitchContext();
 800637c:	f7ff f844 	bl	8005408 <vTaskSwitchContext>
	prvTaskExitError();
 8006380:	f7ff ff1c 	bl	80061bc <prvTaskExitError>

	/* Should not get here! */
	return 0;
 8006384:	2300      	movs	r3, #0
}
 8006386:	4618      	mov	r0, r3
 8006388:	3718      	adds	r7, #24
 800638a:	46bd      	mov	sp, r7
 800638c:	bd80      	pop	{r7, pc}
 800638e:	bf00      	nop
 8006390:	e000ed00 	.word	0xe000ed00
 8006394:	410fc271 	.word	0x410fc271
 8006398:	410fc270 	.word	0x410fc270
 800639c:	e000e400 	.word	0xe000e400
 80063a0:	20003f08 	.word	0x20003f08
 80063a4:	20003f0c 	.word	0x20003f0c
 80063a8:	e000ed20 	.word	0xe000ed20
 80063ac:	2000001c 	.word	0x2000001c
 80063b0:	e000ef34 	.word	0xe000ef34

080063b4 <vPortEnterCritical>:
	configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/

void vPortEnterCritical( void )
{
 80063b4:	b480      	push	{r7}
 80063b6:	b083      	sub	sp, #12
 80063b8:	af00      	add	r7, sp, #0
	__asm volatile
 80063ba:	f04f 0350 	mov.w	r3, #80	; 0x50
 80063be:	f383 8811 	msr	BASEPRI, r3
 80063c2:	f3bf 8f6f 	isb	sy
 80063c6:	f3bf 8f4f 	dsb	sy
 80063ca:	607b      	str	r3, [r7, #4]
}
 80063cc:	bf00      	nop
	portDISABLE_INTERRUPTS();
	uxCriticalNesting++;
 80063ce:	4b0f      	ldr	r3, [pc, #60]	; (800640c <vPortEnterCritical+0x58>)
 80063d0:	681b      	ldr	r3, [r3, #0]
 80063d2:	3301      	adds	r3, #1
 80063d4:	4a0d      	ldr	r2, [pc, #52]	; (800640c <vPortEnterCritical+0x58>)
 80063d6:	6013      	str	r3, [r2, #0]
	/* This is not the interrupt safe version of the enter critical function so
	assert() if it is being called from an interrupt context.  Only API
	functions that end in "FromISR" can be used in an interrupt.  Only assert if
	the critical nesting count is 1 to protect against recursive calls if the
	assert function also uses a critical section. */
	if( uxCriticalNesting == 1 )
 80063d8:	4b0c      	ldr	r3, [pc, #48]	; (800640c <vPortEnterCritical+0x58>)
 80063da:	681b      	ldr	r3, [r3, #0]
 80063dc:	2b01      	cmp	r3, #1
 80063de:	d10f      	bne.n	8006400 <vPortEnterCritical+0x4c>
	{
		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
 80063e0:	4b0b      	ldr	r3, [pc, #44]	; (8006410 <vPortEnterCritical+0x5c>)
 80063e2:	681b      	ldr	r3, [r3, #0]
 80063e4:	b2db      	uxtb	r3, r3
 80063e6:	2b00      	cmp	r3, #0
 80063e8:	d00a      	beq.n	8006400 <vPortEnterCritical+0x4c>
	__asm volatile
 80063ea:	f04f 0350 	mov.w	r3, #80	; 0x50
 80063ee:	f383 8811 	msr	BASEPRI, r3
 80063f2:	f3bf 8f6f 	isb	sy
 80063f6:	f3bf 8f4f 	dsb	sy
 80063fa:	603b      	str	r3, [r7, #0]
}
 80063fc:	bf00      	nop
 80063fe:	e7fe      	b.n	80063fe <vPortEnterCritical+0x4a>
	}
}
 8006400:	bf00      	nop
 8006402:	370c      	adds	r7, #12
 8006404:	46bd      	mov	sp, r7
 8006406:	f85d 7b04 	ldr.w	r7, [sp], #4
 800640a:	4770      	bx	lr
 800640c:	2000001c 	.word	0x2000001c
 8006410:	e000ed04 	.word	0xe000ed04

08006414 <vPortExitCritical>:
/*-----------------------------------------------------------*/

void vPortExitCritical( void )
{
 8006414:	b480      	push	{r7}
 8006416:	b083      	sub	sp, #12
 8006418:	af00      	add	r7, sp, #0
	configASSERT( uxCriticalNesting );
 800641a:	4b12      	ldr	r3, [pc, #72]	; (8006464 <vPortExitCritical+0x50>)
 800641c:	681b      	ldr	r3, [r3, #0]
 800641e:	2b00      	cmp	r3, #0
 8006420:	d10a      	bne.n	8006438 <vPortExitCritical+0x24>
	__asm volatile
 8006422:	f04f 0350 	mov.w	r3, #80	; 0x50
 8006426:	f383 8811 	msr	BASEPRI, r3
 800642a:	f3bf 8f6f 	isb	sy
 800642e:	f3bf 8f4f 	dsb	sy
 8006432:	607b      	str	r3, [r7, #4]
}
 8006434:	bf00      	nop
 8006436:	e7fe      	b.n	8006436 <vPortExitCritical+0x22>
	uxCriticalNesting--;
 8006438:	4b0a      	ldr	r3, [pc, #40]	; (8006464 <vPortExitCritical+0x50>)
 800643a:	681b      	ldr	r3, [r3, #0]
 800643c:	3b01      	subs	r3, #1
 800643e:	4a09      	ldr	r2, [pc, #36]	; (8006464 <vPortExitCritical+0x50>)
 8006440:	6013      	str	r3, [r2, #0]
	if( uxCriticalNesting == 0 )
 8006442:	4b08      	ldr	r3, [pc, #32]	; (8006464 <vPortExitCritical+0x50>)
 8006444:	681b      	ldr	r3, [r3, #0]
 8006446:	2b00      	cmp	r3, #0
 8006448:	d105      	bne.n	8006456 <vPortExitCritical+0x42>
 800644a:	2300      	movs	r3, #0
 800644c:	603b      	str	r3, [r7, #0]
	__asm volatile
 800644e:	683b      	ldr	r3, [r7, #0]
 8006450:	f383 8811 	msr	BASEPRI, r3
}
 8006454:	bf00      	nop
	{
		portENABLE_INTERRUPTS();
	}
}
 8006456:	bf00      	nop
 8006458:	370c      	adds	r7, #12
 800645a:	46bd      	mov	sp, r7
 800645c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006460:	4770      	bx	lr
 8006462:	bf00      	nop
 8006464:	2000001c 	.word	0x2000001c
	...

08006470 <PendSV_Handler>:

void xPortPendSVHandler( void )
{
	/* This is a naked function. */

	__asm volatile
 8006470:	f3ef 8009 	mrs	r0, PSP
 8006474:	f3bf 8f6f 	isb	sy
 8006478:	4b15      	ldr	r3, [pc, #84]	; (80064d0 <pxCurrentTCBConst>)
 800647a:	681a      	ldr	r2, [r3, #0]
 800647c:	f01e 0f10 	tst.w	lr, #16
 8006480:	bf08      	it	eq
 8006482:	ed20 8a10 	vstmdbeq	r0!, {s16-s31}
 8006486:	e920 4ff0 	stmdb	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 800648a:	6010      	str	r0, [r2, #0]
 800648c:	e92d 0009 	stmdb	sp!, {r0, r3}
 8006490:	f04f 0050 	mov.w	r0, #80	; 0x50
 8006494:	f380 8811 	msr	BASEPRI, r0
 8006498:	f3bf 8f4f 	dsb	sy
 800649c:	f3bf 8f6f 	isb	sy
 80064a0:	f7fe ffb2 	bl	8005408 <vTaskSwitchContext>
 80064a4:	f04f 0000 	mov.w	r0, #0
 80064a8:	f380 8811 	msr	BASEPRI, r0
 80064ac:	bc09      	pop	{r0, r3}
 80064ae:	6819      	ldr	r1, [r3, #0]
 80064b0:	6808      	ldr	r0, [r1, #0]
 80064b2:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80064b6:	f01e 0f10 	tst.w	lr, #16
 80064ba:	bf08      	it	eq
 80064bc:	ecb0 8a10 	vldmiaeq	r0!, {s16-s31}
 80064c0:	f380 8809 	msr	PSP, r0
 80064c4:	f3bf 8f6f 	isb	sy
 80064c8:	4770      	bx	lr
 80064ca:	bf00      	nop
 80064cc:	f3af 8000 	nop.w

080064d0 <pxCurrentTCBConst>:
 80064d0:	200038dc 	.word	0x200038dc
	"										\n"
	"	.align 4							\n"
	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
	);
}
 80064d4:	bf00      	nop
 80064d6:	bf00      	nop

080064d8 <xPortSysTickHandler>:
/*-----------------------------------------------------------*/

void xPortSysTickHandler( void )
{
 80064d8:	b580      	push	{r7, lr}
 80064da:	b082      	sub	sp, #8
 80064dc:	af00      	add	r7, sp, #0
	__asm volatile
 80064de:	f04f 0350 	mov.w	r3, #80	; 0x50
 80064e2:	f383 8811 	msr	BASEPRI, r3
 80064e6:	f3bf 8f6f 	isb	sy
 80064ea:	f3bf 8f4f 	dsb	sy
 80064ee:	607b      	str	r3, [r7, #4]
}
 80064f0:	bf00      	nop
	save and then restore the interrupt mask value as its value is already
	known. */
	portDISABLE_INTERRUPTS();
	{
		/* Increment the RTOS tick. */
		if( xTaskIncrementTick() != pdFALSE )
 80064f2:	f7fe fec7 	bl	8005284 <xTaskIncrementTick>
 80064f6:	4603      	mov	r3, r0
 80064f8:	2b00      	cmp	r3, #0
 80064fa:	d003      	beq.n	8006504 <xPortSysTickHandler+0x2c>
		{
			/* A context switch is required.  Context switching is performed in
			the PendSV interrupt.  Pend the PendSV interrupt. */
			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
 80064fc:	4b06      	ldr	r3, [pc, #24]	; (8006518 <xPortSysTickHandler+0x40>)
 80064fe:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8006502:	601a      	str	r2, [r3, #0]
 8006504:	2300      	movs	r3, #0
 8006506:	603b      	str	r3, [r7, #0]
	__asm volatile
 8006508:	683b      	ldr	r3, [r7, #0]
 800650a:	f383 8811 	msr	BASEPRI, r3
}
 800650e:	bf00      	nop
		}
	}
	portENABLE_INTERRUPTS();
}
 8006510:	bf00      	nop
 8006512:	3708      	adds	r7, #8
 8006514:	46bd      	mov	sp, r7
 8006516:	bd80      	pop	{r7, pc}
 8006518:	e000ed04 	.word	0xe000ed04

0800651c <vPortSetupTimerInterrupt>:
/*
 * Setup the systick timer to generate the tick interrupts at the required
 * frequency.
 */
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
 800651c:	b480      	push	{r7}
 800651e:	af00      	add	r7, sp, #0
		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
	}
	#endif /* configUSE_TICKLESS_IDLE */

	/* Stop and clear the SysTick. */
	portNVIC_SYSTICK_CTRL_REG = 0UL;
 8006520:	4b0b      	ldr	r3, [pc, #44]	; (8006550 <vPortSetupTimerInterrupt+0x34>)
 8006522:	2200      	movs	r2, #0
 8006524:	601a      	str	r2, [r3, #0]
	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 8006526:	4b0b      	ldr	r3, [pc, #44]	; (8006554 <vPortSetupTimerInterrupt+0x38>)
 8006528:	2200      	movs	r2, #0
 800652a:	601a      	str	r2, [r3, #0]

	/* Configure SysTick to interrupt at the requested rate. */
	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
 800652c:	4b0a      	ldr	r3, [pc, #40]	; (8006558 <vPortSetupTimerInterrupt+0x3c>)
 800652e:	681b      	ldr	r3, [r3, #0]
 8006530:	4a0a      	ldr	r2, [pc, #40]	; (800655c <vPortSetupTimerInterrupt+0x40>)
 8006532:	fba2 2303 	umull	r2, r3, r2, r3
 8006536:	099b      	lsrs	r3, r3, #6
 8006538:	4a09      	ldr	r2, [pc, #36]	; (8006560 <vPortSetupTimerInterrupt+0x44>)
 800653a:	3b01      	subs	r3, #1
 800653c:	6013      	str	r3, [r2, #0]
	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
 800653e:	4b04      	ldr	r3, [pc, #16]	; (8006550 <vPortSetupTimerInterrupt+0x34>)
 8006540:	2207      	movs	r2, #7
 8006542:	601a      	str	r2, [r3, #0]
}
 8006544:	bf00      	nop
 8006546:	46bd      	mov	sp, r7
 8006548:	f85d 7b04 	ldr.w	r7, [sp], #4
 800654c:	4770      	bx	lr
 800654e:	bf00      	nop
 8006550:	e000e010 	.word	0xe000e010
 8006554:	e000e018 	.word	0xe000e018
 8006558:	20000000 	.word	0x20000000
 800655c:	10624dd3 	.word	0x10624dd3
 8006560:	e000e014 	.word	0xe000e014

08006564 <vPortEnableVFP>:
/*-----------------------------------------------------------*/

/* This is a naked function. */
static void vPortEnableVFP( void )
{
	__asm volatile
 8006564:	f8df 000c 	ldr.w	r0, [pc, #12]	; 8006574 <vPortEnableVFP+0x10>
 8006568:	6801      	ldr	r1, [r0, #0]
 800656a:	f441 0170 	orr.w	r1, r1, #15728640	; 0xf00000
 800656e:	6001      	str	r1, [r0, #0]
 8006570:	4770      	bx	lr
		"								\n"
		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
		"	str r1, [r0]				\n"
		"	bx r14						"
	);
}
 8006572:	bf00      	nop
 8006574:	e000ed88 	.word	0xe000ed88

08006578 <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/

#if( configASSERT_DEFINED == 1 )

	void vPortValidateInterruptPriority( void )
	{
 8006578:	b480      	push	{r7}
 800657a:	b085      	sub	sp, #20
 800657c:	af00      	add	r7, sp, #0
	uint32_t ulCurrentInterrupt;
	uint8_t ucCurrentPriority;

		/* Obtain the number of the currently executing interrupt. */
		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
 800657e:	f3ef 8305 	mrs	r3, IPSR
 8006582:	60fb      	str	r3, [r7, #12]

		/* Is the interrupt number a user defined interrupt? */
		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
 8006584:	68fb      	ldr	r3, [r7, #12]
 8006586:	2b0f      	cmp	r3, #15
 8006588:	d914      	bls.n	80065b4 <vPortValidateInterruptPriority+0x3c>
		{
			/* Look up the interrupt's priority. */
			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
 800658a:	4a17      	ldr	r2, [pc, #92]	; (80065e8 <vPortValidateInterruptPriority+0x70>)
 800658c:	68fb      	ldr	r3, [r7, #12]
 800658e:	4413      	add	r3, r2
 8006590:	781b      	ldrb	r3, [r3, #0]
 8006592:	72fb      	strb	r3, [r7, #11]
			interrupt entry is as fast and simple as possible.

			The following links provide detailed information:
			http://www.freertos.org/RTOS-Cortex-M3-M4.html
			http://www.freertos.org/FAQHelp.html */
			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
 8006594:	4b15      	ldr	r3, [pc, #84]	; (80065ec <vPortValidateInterruptPriority+0x74>)
 8006596:	781b      	ldrb	r3, [r3, #0]
 8006598:	7afa      	ldrb	r2, [r7, #11]
 800659a:	429a      	cmp	r2, r3
 800659c:	d20a      	bcs.n	80065b4 <vPortValidateInterruptPriority+0x3c>
	__asm volatile
 800659e:	f04f 0350 	mov.w	r3, #80	; 0x50
 80065a2:	f383 8811 	msr	BASEPRI, r3
 80065a6:	f3bf 8f6f 	isb	sy
 80065aa:	f3bf 8f4f 	dsb	sy
 80065ae:	607b      	str	r3, [r7, #4]
}
 80065b0:	bf00      	nop
 80065b2:	e7fe      	b.n	80065b2 <vPortValidateInterruptPriority+0x3a>
		configuration then the correct setting can be achieved on all Cortex-M
		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
		scheduler.  Note however that some vendor specific peripheral libraries
		assume a non-zero priority group setting, in which cases using a value
		of zero will result in unpredictable behaviour. */
		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
 80065b4:	4b0e      	ldr	r3, [pc, #56]	; (80065f0 <vPortValidateInterruptPriority+0x78>)
 80065b6:	681b      	ldr	r3, [r3, #0]
 80065b8:	f403 62e0 	and.w	r2, r3, #1792	; 0x700
 80065bc:	4b0d      	ldr	r3, [pc, #52]	; (80065f4 <vPortValidateInterruptPriority+0x7c>)
 80065be:	681b      	ldr	r3, [r3, #0]
 80065c0:	429a      	cmp	r2, r3
 80065c2:	d90a      	bls.n	80065da <vPortValidateInterruptPriority+0x62>
	__asm volatile
 80065c4:	f04f 0350 	mov.w	r3, #80	; 0x50
 80065c8:	f383 8811 	msr	BASEPRI, r3
 80065cc:	f3bf 8f6f 	isb	sy
 80065d0:	f3bf 8f4f 	dsb	sy
 80065d4:	603b      	str	r3, [r7, #0]
}
 80065d6:	bf00      	nop
 80065d8:	e7fe      	b.n	80065d8 <vPortValidateInterruptPriority+0x60>
	}
 80065da:	bf00      	nop
 80065dc:	3714      	adds	r7, #20
 80065de:	46bd      	mov	sp, r7
 80065e0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80065e4:	4770      	bx	lr
 80065e6:	bf00      	nop
 80065e8:	e000e3f0 	.word	0xe000e3f0
 80065ec:	20003f08 	.word	0x20003f08
 80065f0:	e000ed0c 	.word	0xe000ed0c
 80065f4:	20003f0c 	.word	0x20003f0c

080065f8 <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;

/*-----------------------------------------------------------*/

void *pvPortMalloc( size_t xWantedSize )
{
 80065f8:	b580      	push	{r7, lr}
 80065fa:	b088      	sub	sp, #32
 80065fc:	af00      	add	r7, sp, #0
 80065fe:	6078      	str	r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
 8006600:	2300      	movs	r3, #0
 8006602:	617b      	str	r3, [r7, #20]

	/* The heap must be initialised before the first call to
	prvPortMalloc(). */
	configASSERT( pxEnd );
 8006604:	4b48      	ldr	r3, [pc, #288]	; (8006728 <pvPortMalloc+0x130>)
 8006606:	681b      	ldr	r3, [r3, #0]
 8006608:	2b00      	cmp	r3, #0
 800660a:	d10a      	bne.n	8006622 <pvPortMalloc+0x2a>
	__asm volatile
 800660c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8006610:	f383 8811 	msr	BASEPRI, r3
 8006614:	f3bf 8f6f 	isb	sy
 8006618:	f3bf 8f4f 	dsb	sy
 800661c:	60fb      	str	r3, [r7, #12]
}
 800661e:	bf00      	nop
 8006620:	e7fe      	b.n	8006620 <pvPortMalloc+0x28>

	vTaskSuspendAll();
 8006622:	f7fe fd73 	bl	800510c <vTaskSuspendAll>
	{
		/* Check the requested block size is not so large that the top bit is
		set.  The top bit of the block size member of the BlockLink_t structure
		is used to determine who owns the block - the application or the
		kernel, so it must be free. */
		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
 8006626:	4b41      	ldr	r3, [pc, #260]	; (800672c <pvPortMalloc+0x134>)
 8006628:	681a      	ldr	r2, [r3, #0]
 800662a:	687b      	ldr	r3, [r7, #4]
 800662c:	4013      	ands	r3, r2
 800662e:	2b00      	cmp	r3, #0
 8006630:	d172      	bne.n	8006718 <pvPortMalloc+0x120>
		{
			/* The wanted size is increased so it can contain a BlockLink_t
			structure in addition to the requested amount of bytes. */
			if( xWantedSize > 0 )
 8006632:	687b      	ldr	r3, [r7, #4]
 8006634:	2b00      	cmp	r3, #0
 8006636:	d00d      	beq.n	8006654 <pvPortMalloc+0x5c>
			{
				xWantedSize += xHeapStructSize;
 8006638:	2208      	movs	r2, #8
 800663a:	687b      	ldr	r3, [r7, #4]
 800663c:	4413      	add	r3, r2
 800663e:	607b      	str	r3, [r7, #4]

				/* Ensure that blocks are always aligned to the required number
				of bytes. */
				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
 8006640:	687b      	ldr	r3, [r7, #4]
 8006642:	f003 0307 	and.w	r3, r3, #7
 8006646:	2b00      	cmp	r3, #0
 8006648:	d004      	beq.n	8006654 <pvPortMalloc+0x5c>
				{
					/* Byte alignment required. */
					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
 800664a:	687b      	ldr	r3, [r7, #4]
 800664c:	f023 0307 	bic.w	r3, r3, #7
 8006650:	3308      	adds	r3, #8
 8006652:	607b      	str	r3, [r7, #4]
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}

			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
 8006654:	687b      	ldr	r3, [r7, #4]
 8006656:	2b00      	cmp	r3, #0
 8006658:	d05e      	beq.n	8006718 <pvPortMalloc+0x120>
 800665a:	4b35      	ldr	r3, [pc, #212]	; (8006730 <pvPortMalloc+0x138>)
 800665c:	681b      	ldr	r3, [r3, #0]
 800665e:	687a      	ldr	r2, [r7, #4]
 8006660:	429a      	cmp	r2, r3
 8006662:	d859      	bhi.n	8006718 <pvPortMalloc+0x120>
			{
				/* Traverse the list from the start	(lowest address) block until
				one	of adequate size is found. */
				pxPreviousBlock = &xStart;
 8006664:	4b33      	ldr	r3, [pc, #204]	; (8006734 <pvPortMalloc+0x13c>)
 8006666:	61bb      	str	r3, [r7, #24]
				pxBlock = xStart.pxNextFreeBlock;
 8006668:	4b32      	ldr	r3, [pc, #200]	; (8006734 <pvPortMalloc+0x13c>)
 800666a:	681b      	ldr	r3, [r3, #0]
 800666c:	61fb      	str	r3, [r7, #28]
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 800666e:	e004      	b.n	800667a <pvPortMalloc+0x82>
				{
					pxPreviousBlock = pxBlock;
 8006670:	69fb      	ldr	r3, [r7, #28]
 8006672:	61bb      	str	r3, [r7, #24]
					pxBlock = pxBlock->pxNextFreeBlock;
 8006674:	69fb      	ldr	r3, [r7, #28]
 8006676:	681b      	ldr	r3, [r3, #0]
 8006678:	61fb      	str	r3, [r7, #28]
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 800667a:	69fb      	ldr	r3, [r7, #28]
 800667c:	685b      	ldr	r3, [r3, #4]
 800667e:	687a      	ldr	r2, [r7, #4]
 8006680:	429a      	cmp	r2, r3
 8006682:	d903      	bls.n	800668c <pvPortMalloc+0x94>
 8006684:	69fb      	ldr	r3, [r7, #28]
 8006686:	681b      	ldr	r3, [r3, #0]
 8006688:	2b00      	cmp	r3, #0
 800668a:	d1f1      	bne.n	8006670 <pvPortMalloc+0x78>
				}

				/* If the end marker was reached then a block of adequate size
				was	not found. */
				if( pxBlock != pxEnd )
 800668c:	4b26      	ldr	r3, [pc, #152]	; (8006728 <pvPortMalloc+0x130>)
 800668e:	681b      	ldr	r3, [r3, #0]
 8006690:	69fa      	ldr	r2, [r7, #28]
 8006692:	429a      	cmp	r2, r3
 8006694:	d040      	beq.n	8006718 <pvPortMalloc+0x120>
				{
					/* Return the memory space pointed to - jumping over the
					BlockLink_t structure at its start. */
					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
 8006696:	69bb      	ldr	r3, [r7, #24]
 8006698:	681b      	ldr	r3, [r3, #0]
 800669a:	2208      	movs	r2, #8
 800669c:	4413      	add	r3, r2
 800669e:	617b      	str	r3, [r7, #20]

					/* This block is being returned for use so must be taken out
					of the list of free blocks. */
					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
 80066a0:	69fb      	ldr	r3, [r7, #28]
 80066a2:	681a      	ldr	r2, [r3, #0]
 80066a4:	69bb      	ldr	r3, [r7, #24]
 80066a6:	601a      	str	r2, [r3, #0]

					/* If the block is larger than required it can be split into
					two. */
					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
 80066a8:	69fb      	ldr	r3, [r7, #28]
 80066aa:	685a      	ldr	r2, [r3, #4]
 80066ac:	687b      	ldr	r3, [r7, #4]
 80066ae:	1ad2      	subs	r2, r2, r3
 80066b0:	2308      	movs	r3, #8
 80066b2:	005b      	lsls	r3, r3, #1
 80066b4:	429a      	cmp	r2, r3
 80066b6:	d90f      	bls.n	80066d8 <pvPortMalloc+0xe0>
					{
						/* This block is to be split into two.  Create a new
						block following the number of bytes requested. The void
						cast is used to prevent byte alignment warnings from the
						compiler. */
						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
 80066b8:	69fa      	ldr	r2, [r7, #28]
 80066ba:	687b      	ldr	r3, [r7, #4]
 80066bc:	4413      	add	r3, r2
 80066be:	613b      	str	r3, [r7, #16]

						/* Calculate the sizes of two blocks split from the
						single block. */
						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
 80066c0:	69fb      	ldr	r3, [r7, #28]
 80066c2:	685a      	ldr	r2, [r3, #4]
 80066c4:	687b      	ldr	r3, [r7, #4]
 80066c6:	1ad2      	subs	r2, r2, r3
 80066c8:	693b      	ldr	r3, [r7, #16]
 80066ca:	605a      	str	r2, [r3, #4]
						pxBlock->xBlockSize = xWantedSize;
 80066cc:	69fb      	ldr	r3, [r7, #28]
 80066ce:	687a      	ldr	r2, [r7, #4]
 80066d0:	605a      	str	r2, [r3, #4]

						/* Insert the new block into the list of free blocks. */
						prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
 80066d2:	6938      	ldr	r0, [r7, #16]
 80066d4:	f000 f896 	bl	8006804 <prvInsertBlockIntoFreeList>
					else
					{
						mtCOVERAGE_TEST_MARKER();
					}

					xFreeBytesRemaining -= pxBlock->xBlockSize;
 80066d8:	4b15      	ldr	r3, [pc, #84]	; (8006730 <pvPortMalloc+0x138>)
 80066da:	681a      	ldr	r2, [r3, #0]
 80066dc:	69fb      	ldr	r3, [r7, #28]
 80066de:	685b      	ldr	r3, [r3, #4]
 80066e0:	1ad3      	subs	r3, r2, r3
 80066e2:	4a13      	ldr	r2, [pc, #76]	; (8006730 <pvPortMalloc+0x138>)
 80066e4:	6013      	str	r3, [r2, #0]

					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
 80066e6:	4b12      	ldr	r3, [pc, #72]	; (8006730 <pvPortMalloc+0x138>)
 80066e8:	681a      	ldr	r2, [r3, #0]
 80066ea:	4b13      	ldr	r3, [pc, #76]	; (8006738 <pvPortMalloc+0x140>)
 80066ec:	681b      	ldr	r3, [r3, #0]
 80066ee:	429a      	cmp	r2, r3
 80066f0:	d203      	bcs.n	80066fa <pvPortMalloc+0x102>
					{
						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
 80066f2:	4b0f      	ldr	r3, [pc, #60]	; (8006730 <pvPortMalloc+0x138>)
 80066f4:	681b      	ldr	r3, [r3, #0]
 80066f6:	4a10      	ldr	r2, [pc, #64]	; (8006738 <pvPortMalloc+0x140>)
 80066f8:	6013      	str	r3, [r2, #0]
						mtCOVERAGE_TEST_MARKER();
					}

					/* The block is being returned - it is allocated and owned
					by the application and has no "next" block. */
					pxBlock->xBlockSize |= xBlockAllocatedBit;
 80066fa:	69fb      	ldr	r3, [r7, #28]
 80066fc:	685a      	ldr	r2, [r3, #4]
 80066fe:	4b0b      	ldr	r3, [pc, #44]	; (800672c <pvPortMalloc+0x134>)
 8006700:	681b      	ldr	r3, [r3, #0]
 8006702:	431a      	orrs	r2, r3
 8006704:	69fb      	ldr	r3, [r7, #28]
 8006706:	605a      	str	r2, [r3, #4]
					pxBlock->pxNextFreeBlock = NULL;
 8006708:	69fb      	ldr	r3, [r7, #28]
 800670a:	2200      	movs	r2, #0
 800670c:	601a      	str	r2, [r3, #0]
					xNumberOfSuccessfulAllocations++;
 800670e:	4b0b      	ldr	r3, [pc, #44]	; (800673c <pvPortMalloc+0x144>)
 8006710:	681b      	ldr	r3, [r3, #0]
 8006712:	3301      	adds	r3, #1
 8006714:	4a09      	ldr	r2, [pc, #36]	; (800673c <pvPortMalloc+0x144>)
 8006716:	6013      	str	r3, [r2, #0]
			mtCOVERAGE_TEST_MARKER();
		}

		traceMALLOC( pvReturn, xWantedSize );
	}
	( void ) xTaskResumeAll();
 8006718:	f7fe fd06 	bl	8005128 <xTaskResumeAll>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif

	return pvReturn;
 800671c:	697b      	ldr	r3, [r7, #20]
}
 800671e:	4618      	mov	r0, r3
 8006720:	3720      	adds	r7, #32
 8006722:	46bd      	mov	sp, r7
 8006724:	bd80      	pop	{r7, pc}
 8006726:	bf00      	nop
 8006728:	20003f18 	.word	0x20003f18
 800672c:	20003f2c 	.word	0x20003f2c
 8006730:	20003f1c 	.word	0x20003f1c
 8006734:	20003f10 	.word	0x20003f10
 8006738:	20003f20 	.word	0x20003f20
 800673c:	20003f24 	.word	0x20003f24

08006740 <vPortFree>:
/*-----------------------------------------------------------*/

void vPortFree( void *pv )
{
 8006740:	b580      	push	{r7, lr}
 8006742:	b086      	sub	sp, #24
 8006744:	af00      	add	r7, sp, #0
 8006746:	6078      	str	r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
 8006748:	687b      	ldr	r3, [r7, #4]
 800674a:	617b      	str	r3, [r7, #20]
BlockLink_t *pxLink;

	if( pv != NULL )
 800674c:	687b      	ldr	r3, [r7, #4]
 800674e:	2b00      	cmp	r3, #0
 8006750:	d04d      	beq.n	80067ee <vPortFree+0xae>
	{
		/* The memory being freed will have an BlockLink_t structure immediately
		before it. */
		puc -= xHeapStructSize;
 8006752:	2308      	movs	r3, #8
 8006754:	425b      	negs	r3, r3
 8006756:	697a      	ldr	r2, [r7, #20]
 8006758:	4413      	add	r3, r2
 800675a:	617b      	str	r3, [r7, #20]

		/* This casting is to keep the compiler from issuing warnings. */
		pxLink = ( void * ) puc;
 800675c:	697b      	ldr	r3, [r7, #20]
 800675e:	613b      	str	r3, [r7, #16]

		/* Check the block is actually allocated. */
		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
 8006760:	693b      	ldr	r3, [r7, #16]
 8006762:	685a      	ldr	r2, [r3, #4]
 8006764:	4b24      	ldr	r3, [pc, #144]	; (80067f8 <vPortFree+0xb8>)
 8006766:	681b      	ldr	r3, [r3, #0]
 8006768:	4013      	ands	r3, r2
 800676a:	2b00      	cmp	r3, #0
 800676c:	d10a      	bne.n	8006784 <vPortFree+0x44>
	__asm volatile
 800676e:	f04f 0350 	mov.w	r3, #80	; 0x50
 8006772:	f383 8811 	msr	BASEPRI, r3
 8006776:	f3bf 8f6f 	isb	sy
 800677a:	f3bf 8f4f 	dsb	sy
 800677e:	60fb      	str	r3, [r7, #12]
}
 8006780:	bf00      	nop
 8006782:	e7fe      	b.n	8006782 <vPortFree+0x42>
		configASSERT( pxLink->pxNextFreeBlock == NULL );
 8006784:	693b      	ldr	r3, [r7, #16]
 8006786:	681b      	ldr	r3, [r3, #0]
 8006788:	2b00      	cmp	r3, #0
 800678a:	d00a      	beq.n	80067a2 <vPortFree+0x62>
	__asm volatile
 800678c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8006790:	f383 8811 	msr	BASEPRI, r3
 8006794:	f3bf 8f6f 	isb	sy
 8006798:	f3bf 8f4f 	dsb	sy
 800679c:	60bb      	str	r3, [r7, #8]
}
 800679e:	bf00      	nop
 80067a0:	e7fe      	b.n	80067a0 <vPortFree+0x60>

		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
 80067a2:	693b      	ldr	r3, [r7, #16]
 80067a4:	685a      	ldr	r2, [r3, #4]
 80067a6:	4b14      	ldr	r3, [pc, #80]	; (80067f8 <vPortFree+0xb8>)
 80067a8:	681b      	ldr	r3, [r3, #0]
 80067aa:	4013      	ands	r3, r2
 80067ac:	2b00      	cmp	r3, #0
 80067ae:	d01e      	beq.n	80067ee <vPortFree+0xae>
		{
			if( pxLink->pxNextFreeBlock == NULL )
 80067b0:	693b      	ldr	r3, [r7, #16]
 80067b2:	681b      	ldr	r3, [r3, #0]
 80067b4:	2b00      	cmp	r3, #0
 80067b6:	d11a      	bne.n	80067ee <vPortFree+0xae>
			{
				/* The block is being returned to the heap - it is no longer
				allocated. */
				pxLink->xBlockSize &= ~xBlockAllocatedBit;
 80067b8:	693b      	ldr	r3, [r7, #16]
 80067ba:	685a      	ldr	r2, [r3, #4]
 80067bc:	4b0e      	ldr	r3, [pc, #56]	; (80067f8 <vPortFree+0xb8>)
 80067be:	681b      	ldr	r3, [r3, #0]
 80067c0:	43db      	mvns	r3, r3
 80067c2:	401a      	ands	r2, r3
 80067c4:	693b      	ldr	r3, [r7, #16]
 80067c6:	605a      	str	r2, [r3, #4]

				vTaskSuspendAll();
 80067c8:	f7fe fca0 	bl	800510c <vTaskSuspendAll>
				{
					/* Add this block to the list of free blocks. */
					xFreeBytesRemaining += pxLink->xBlockSize;
 80067cc:	693b      	ldr	r3, [r7, #16]
 80067ce:	685a      	ldr	r2, [r3, #4]
 80067d0:	4b0a      	ldr	r3, [pc, #40]	; (80067fc <vPortFree+0xbc>)
 80067d2:	681b      	ldr	r3, [r3, #0]
 80067d4:	4413      	add	r3, r2
 80067d6:	4a09      	ldr	r2, [pc, #36]	; (80067fc <vPortFree+0xbc>)
 80067d8:	6013      	str	r3, [r2, #0]
					traceFREE( pv, pxLink->xBlockSize );
					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
 80067da:	6938      	ldr	r0, [r7, #16]
 80067dc:	f000 f812 	bl	8006804 <prvInsertBlockIntoFreeList>
					xNumberOfSuccessfulFrees++;
 80067e0:	4b07      	ldr	r3, [pc, #28]	; (8006800 <vPortFree+0xc0>)
 80067e2:	681b      	ldr	r3, [r3, #0]
 80067e4:	3301      	adds	r3, #1
 80067e6:	4a06      	ldr	r2, [pc, #24]	; (8006800 <vPortFree+0xc0>)
 80067e8:	6013      	str	r3, [r2, #0]
				}
				( void ) xTaskResumeAll();
 80067ea:	f7fe fc9d 	bl	8005128 <xTaskResumeAll>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
}
 80067ee:	bf00      	nop
 80067f0:	3718      	adds	r7, #24
 80067f2:	46bd      	mov	sp, r7
 80067f4:	bd80      	pop	{r7, pc}
 80067f6:	bf00      	nop
 80067f8:	20003f2c 	.word	0x20003f2c
 80067fc:	20003f1c 	.word	0x20003f1c
 8006800:	20003f28 	.word	0x20003f28

08006804 <prvInsertBlockIntoFreeList>:
	return xMinimumEverFreeBytesRemaining;
}
/*-----------------------------------------------------------*/

static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
 8006804:	b480      	push	{r7}
 8006806:	b085      	sub	sp, #20
 8006808:	af00      	add	r7, sp, #0
 800680a:	6078      	str	r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;

	/* Iterate through the list until a block is found that has a higher address
	than the block being inserted. */
	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
 800680c:	4b28      	ldr	r3, [pc, #160]	; (80068b0 <prvInsertBlockIntoFreeList+0xac>)
 800680e:	60fb      	str	r3, [r7, #12]
 8006810:	e002      	b.n	8006818 <prvInsertBlockIntoFreeList+0x14>
 8006812:	68fb      	ldr	r3, [r7, #12]
 8006814:	681b      	ldr	r3, [r3, #0]
 8006816:	60fb      	str	r3, [r7, #12]
 8006818:	68fb      	ldr	r3, [r7, #12]
 800681a:	681b      	ldr	r3, [r3, #0]
 800681c:	687a      	ldr	r2, [r7, #4]
 800681e:	429a      	cmp	r2, r3
 8006820:	d8f7      	bhi.n	8006812 <prvInsertBlockIntoFreeList+0xe>
		/* Nothing to do here, just iterate to the right position. */
	}

	/* Do the block being inserted, and the block it is being inserted after
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxIterator;
 8006822:	68fb      	ldr	r3, [r7, #12]
 8006824:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
 8006826:	68fb      	ldr	r3, [r7, #12]
 8006828:	685b      	ldr	r3, [r3, #4]
 800682a:	68ba      	ldr	r2, [r7, #8]
 800682c:	4413      	add	r3, r2
 800682e:	687a      	ldr	r2, [r7, #4]
 8006830:	429a      	cmp	r2, r3
 8006832:	d108      	bne.n	8006846 <prvInsertBlockIntoFreeList+0x42>
	{
		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
 8006834:	68fb      	ldr	r3, [r7, #12]
 8006836:	685a      	ldr	r2, [r3, #4]
 8006838:	687b      	ldr	r3, [r7, #4]
 800683a:	685b      	ldr	r3, [r3, #4]
 800683c:	441a      	add	r2, r3
 800683e:	68fb      	ldr	r3, [r7, #12]
 8006840:	605a      	str	r2, [r3, #4]
		pxBlockToInsert = pxIterator;
 8006842:	68fb      	ldr	r3, [r7, #12]
 8006844:	607b      	str	r3, [r7, #4]
		mtCOVERAGE_TEST_MARKER();
	}

	/* Do the block being inserted, and the block it is being inserted before
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxBlockToInsert;
 8006846:	687b      	ldr	r3, [r7, #4]
 8006848:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
 800684a:	687b      	ldr	r3, [r7, #4]
 800684c:	685b      	ldr	r3, [r3, #4]
 800684e:	68ba      	ldr	r2, [r7, #8]
 8006850:	441a      	add	r2, r3
 8006852:	68fb      	ldr	r3, [r7, #12]
 8006854:	681b      	ldr	r3, [r3, #0]
 8006856:	429a      	cmp	r2, r3
 8006858:	d118      	bne.n	800688c <prvInsertBlockIntoFreeList+0x88>
	{
		if( pxIterator->pxNextFreeBlock != pxEnd )
 800685a:	68fb      	ldr	r3, [r7, #12]
 800685c:	681a      	ldr	r2, [r3, #0]
 800685e:	4b15      	ldr	r3, [pc, #84]	; (80068b4 <prvInsertBlockIntoFreeList+0xb0>)
 8006860:	681b      	ldr	r3, [r3, #0]
 8006862:	429a      	cmp	r2, r3
 8006864:	d00d      	beq.n	8006882 <prvInsertBlockIntoFreeList+0x7e>
		{
			/* Form one big block from the two blocks. */
			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
 8006866:	687b      	ldr	r3, [r7, #4]
 8006868:	685a      	ldr	r2, [r3, #4]
 800686a:	68fb      	ldr	r3, [r7, #12]
 800686c:	681b      	ldr	r3, [r3, #0]
 800686e:	685b      	ldr	r3, [r3, #4]
 8006870:	441a      	add	r2, r3
 8006872:	687b      	ldr	r3, [r7, #4]
 8006874:	605a      	str	r2, [r3, #4]
			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
 8006876:	68fb      	ldr	r3, [r7, #12]
 8006878:	681b      	ldr	r3, [r3, #0]
 800687a:	681a      	ldr	r2, [r3, #0]
 800687c:	687b      	ldr	r3, [r7, #4]
 800687e:	601a      	str	r2, [r3, #0]
 8006880:	e008      	b.n	8006894 <prvInsertBlockIntoFreeList+0x90>
		}
		else
		{
			pxBlockToInsert->pxNextFreeBlock = pxEnd;
 8006882:	4b0c      	ldr	r3, [pc, #48]	; (80068b4 <prvInsertBlockIntoFreeList+0xb0>)
 8006884:	681a      	ldr	r2, [r3, #0]
 8006886:	687b      	ldr	r3, [r7, #4]
 8006888:	601a      	str	r2, [r3, #0]
 800688a:	e003      	b.n	8006894 <prvInsertBlockIntoFreeList+0x90>
		}
	}
	else
	{
		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
 800688c:	68fb      	ldr	r3, [r7, #12]
 800688e:	681a      	ldr	r2, [r3, #0]
 8006890:	687b      	ldr	r3, [r7, #4]
 8006892:	601a      	str	r2, [r3, #0]

	/* If the block being inserted plugged a gab, so was merged with the block
	before and the block after, then it's pxNextFreeBlock pointer will have
	already been set, and should not be set here as that would make it point
	to itself. */
	if( pxIterator != pxBlockToInsert )
 8006894:	68fa      	ldr	r2, [r7, #12]
 8006896:	687b      	ldr	r3, [r7, #4]
 8006898:	429a      	cmp	r2, r3
 800689a:	d002      	beq.n	80068a2 <prvInsertBlockIntoFreeList+0x9e>
	{
		pxIterator->pxNextFreeBlock = pxBlockToInsert;
 800689c:	68fb      	ldr	r3, [r7, #12]
 800689e:	687a      	ldr	r2, [r7, #4]
 80068a0:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 80068a2:	bf00      	nop
 80068a4:	3714      	adds	r7, #20
 80068a6:	46bd      	mov	sp, r7
 80068a8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80068ac:	4770      	bx	lr
 80068ae:	bf00      	nop
 80068b0:	20003f10 	.word	0x20003f10
 80068b4:	20003f18 	.word	0x20003f18

080068b8 <vPortDefineHeapRegions>:
/*-----------------------------------------------------------*/

void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
{
 80068b8:	b480      	push	{r7}
 80068ba:	b08f      	sub	sp, #60	; 0x3c
 80068bc:	af00      	add	r7, sp, #0
 80068be:	6078      	str	r0, [r7, #4]
BlockLink_t *pxFirstFreeBlockInRegion = NULL, *pxPreviousFreeBlock;
 80068c0:	2300      	movs	r3, #0
 80068c2:	623b      	str	r3, [r7, #32]
size_t xAlignedHeap;
size_t xTotalRegionSize, xTotalHeapSize = 0;
 80068c4:	2300      	movs	r3, #0
 80068c6:	633b      	str	r3, [r7, #48]	; 0x30
BaseType_t xDefinedRegions = 0;
 80068c8:	2300      	movs	r3, #0
 80068ca:	62fb      	str	r3, [r7, #44]	; 0x2c
size_t xAddress;
const HeapRegion_t *pxHeapRegion;

	/* Can only call once! */
	configASSERT( pxEnd == NULL );
 80068cc:	4b5a      	ldr	r3, [pc, #360]	; (8006a38 <vPortDefineHeapRegions+0x180>)
 80068ce:	681b      	ldr	r3, [r3, #0]
 80068d0:	2b00      	cmp	r3, #0
 80068d2:	d00a      	beq.n	80068ea <vPortDefineHeapRegions+0x32>
	__asm volatile
 80068d4:	f04f 0350 	mov.w	r3, #80	; 0x50
 80068d8:	f383 8811 	msr	BASEPRI, r3
 80068dc:	f3bf 8f6f 	isb	sy
 80068e0:	f3bf 8f4f 	dsb	sy
 80068e4:	617b      	str	r3, [r7, #20]
}
 80068e6:	bf00      	nop
 80068e8:	e7fe      	b.n	80068e8 <vPortDefineHeapRegions+0x30>

	pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
 80068ea:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 80068ec:	00db      	lsls	r3, r3, #3
 80068ee:	687a      	ldr	r2, [r7, #4]
 80068f0:	4413      	add	r3, r2
 80068f2:	627b      	str	r3, [r7, #36]	; 0x24

	while( pxHeapRegion->xSizeInBytes > 0 )
 80068f4:	e07d      	b.n	80069f2 <vPortDefineHeapRegions+0x13a>
	{
		xTotalRegionSize = pxHeapRegion->xSizeInBytes;
 80068f6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80068f8:	685b      	ldr	r3, [r3, #4]
 80068fa:	637b      	str	r3, [r7, #52]	; 0x34

		/* Ensure the heap region starts on a correctly aligned boundary. */
		xAddress = ( size_t ) pxHeapRegion->pucStartAddress;
 80068fc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80068fe:	681b      	ldr	r3, [r3, #0]
 8006900:	62bb      	str	r3, [r7, #40]	; 0x28
		if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
 8006902:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8006904:	f003 0307 	and.w	r3, r3, #7
 8006908:	2b00      	cmp	r3, #0
 800690a:	d00e      	beq.n	800692a <vPortDefineHeapRegions+0x72>
		{
			xAddress += ( portBYTE_ALIGNMENT - 1 );
 800690c:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800690e:	3307      	adds	r3, #7
 8006910:	62bb      	str	r3, [r7, #40]	; 0x28
			xAddress &= ~portBYTE_ALIGNMENT_MASK;
 8006912:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8006914:	f023 0307 	bic.w	r3, r3, #7
 8006918:	62bb      	str	r3, [r7, #40]	; 0x28

			/* Adjust the size for the bytes lost to alignment. */
			xTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress;
 800691a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 800691c:	681b      	ldr	r3, [r3, #0]
 800691e:	461a      	mov	r2, r3
 8006920:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8006922:	1ad3      	subs	r3, r2, r3
 8006924:	6b7a      	ldr	r2, [r7, #52]	; 0x34
 8006926:	4413      	add	r3, r2
 8006928:	637b      	str	r3, [r7, #52]	; 0x34
		}

		xAlignedHeap = xAddress;
 800692a:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800692c:	61fb      	str	r3, [r7, #28]

		/* Set xStart if it has not already been set. */
		if( xDefinedRegions == 0 )
 800692e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8006930:	2b00      	cmp	r3, #0
 8006932:	d106      	bne.n	8006942 <vPortDefineHeapRegions+0x8a>
		{
			/* xStart is used to hold a pointer to the first item in the list of
			free blocks.  The void cast is used to prevent compiler warnings. */
			xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;
 8006934:	69fb      	ldr	r3, [r7, #28]
 8006936:	4a41      	ldr	r2, [pc, #260]	; (8006a3c <vPortDefineHeapRegions+0x184>)
 8006938:	6013      	str	r3, [r2, #0]
			xStart.xBlockSize = ( size_t ) 0;
 800693a:	4b40      	ldr	r3, [pc, #256]	; (8006a3c <vPortDefineHeapRegions+0x184>)
 800693c:	2200      	movs	r2, #0
 800693e:	605a      	str	r2, [r3, #4]
 8006940:	e01f      	b.n	8006982 <vPortDefineHeapRegions+0xca>
		}
		else
		{
			/* Should only get here if one region has already been added to the
			heap. */
			configASSERT( pxEnd != NULL );
 8006942:	4b3d      	ldr	r3, [pc, #244]	; (8006a38 <vPortDefineHeapRegions+0x180>)
 8006944:	681b      	ldr	r3, [r3, #0]
 8006946:	2b00      	cmp	r3, #0
 8006948:	d10a      	bne.n	8006960 <vPortDefineHeapRegions+0xa8>
	__asm volatile
 800694a:	f04f 0350 	mov.w	r3, #80	; 0x50
 800694e:	f383 8811 	msr	BASEPRI, r3
 8006952:	f3bf 8f6f 	isb	sy
 8006956:	f3bf 8f4f 	dsb	sy
 800695a:	613b      	str	r3, [r7, #16]
}
 800695c:	bf00      	nop
 800695e:	e7fe      	b.n	800695e <vPortDefineHeapRegions+0xa6>

			/* Check blocks are passed in with increasing start addresses. */
			configASSERT( xAddress > ( size_t ) pxEnd );
 8006960:	4b35      	ldr	r3, [pc, #212]	; (8006a38 <vPortDefineHeapRegions+0x180>)
 8006962:	681b      	ldr	r3, [r3, #0]
 8006964:	461a      	mov	r2, r3
 8006966:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8006968:	4293      	cmp	r3, r2
 800696a:	d80a      	bhi.n	8006982 <vPortDefineHeapRegions+0xca>
	__asm volatile
 800696c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8006970:	f383 8811 	msr	BASEPRI, r3
 8006974:	f3bf 8f6f 	isb	sy
 8006978:	f3bf 8f4f 	dsb	sy
 800697c:	60fb      	str	r3, [r7, #12]
}
 800697e:	bf00      	nop
 8006980:	e7fe      	b.n	8006980 <vPortDefineHeapRegions+0xc8>
		}

		/* Remember the location of the end marker in the previous region, if
		any. */
		pxPreviousFreeBlock = pxEnd;
 8006982:	4b2d      	ldr	r3, [pc, #180]	; (8006a38 <vPortDefineHeapRegions+0x180>)
 8006984:	681b      	ldr	r3, [r3, #0]
 8006986:	61bb      	str	r3, [r7, #24]

		/* pxEnd is used to mark the end of the list of free blocks and is
		inserted at the end of the region space. */
		xAddress = xAlignedHeap + xTotalRegionSize;
 8006988:	69fa      	ldr	r2, [r7, #28]
 800698a:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 800698c:	4413      	add	r3, r2
 800698e:	62bb      	str	r3, [r7, #40]	; 0x28
		xAddress -= xHeapStructSize;
 8006990:	2208      	movs	r2, #8
 8006992:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8006994:	1a9b      	subs	r3, r3, r2
 8006996:	62bb      	str	r3, [r7, #40]	; 0x28
		xAddress &= ~portBYTE_ALIGNMENT_MASK;
 8006998:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800699a:	f023 0307 	bic.w	r3, r3, #7
 800699e:	62bb      	str	r3, [r7, #40]	; 0x28
		pxEnd = ( BlockLink_t * ) xAddress;
 80069a0:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80069a2:	4a25      	ldr	r2, [pc, #148]	; (8006a38 <vPortDefineHeapRegions+0x180>)
 80069a4:	6013      	str	r3, [r2, #0]
		pxEnd->xBlockSize = 0;
 80069a6:	4b24      	ldr	r3, [pc, #144]	; (8006a38 <vPortDefineHeapRegions+0x180>)
 80069a8:	681b      	ldr	r3, [r3, #0]
 80069aa:	2200      	movs	r2, #0
 80069ac:	605a      	str	r2, [r3, #4]
		pxEnd->pxNextFreeBlock = NULL;
 80069ae:	4b22      	ldr	r3, [pc, #136]	; (8006a38 <vPortDefineHeapRegions+0x180>)
 80069b0:	681b      	ldr	r3, [r3, #0]
 80069b2:	2200      	movs	r2, #0
 80069b4:	601a      	str	r2, [r3, #0]

		/* To start with there is a single free block in this region that is
		sized to take up the entire heap region minus the space taken by the
		free block structure. */
		pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;
 80069b6:	69fb      	ldr	r3, [r7, #28]
 80069b8:	623b      	str	r3, [r7, #32]
		pxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion;
 80069ba:	6a3b      	ldr	r3, [r7, #32]
 80069bc:	6aba      	ldr	r2, [r7, #40]	; 0x28
 80069be:	1ad2      	subs	r2, r2, r3
 80069c0:	6a3b      	ldr	r3, [r7, #32]
 80069c2:	605a      	str	r2, [r3, #4]
		pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
 80069c4:	4b1c      	ldr	r3, [pc, #112]	; (8006a38 <vPortDefineHeapRegions+0x180>)
 80069c6:	681a      	ldr	r2, [r3, #0]
 80069c8:	6a3b      	ldr	r3, [r7, #32]
 80069ca:	601a      	str	r2, [r3, #0]

		/* If this is not the first region that makes up the entire heap space
		then link the previous region to this region. */
		if( pxPreviousFreeBlock != NULL )
 80069cc:	69bb      	ldr	r3, [r7, #24]
 80069ce:	2b00      	cmp	r3, #0
 80069d0:	d002      	beq.n	80069d8 <vPortDefineHeapRegions+0x120>
		{
			pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;
 80069d2:	69bb      	ldr	r3, [r7, #24]
 80069d4:	6a3a      	ldr	r2, [r7, #32]
 80069d6:	601a      	str	r2, [r3, #0]
		}

		xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;
 80069d8:	6a3b      	ldr	r3, [r7, #32]
 80069da:	685b      	ldr	r3, [r3, #4]
 80069dc:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 80069de:	4413      	add	r3, r2
 80069e0:	633b      	str	r3, [r7, #48]	; 0x30

		/* Move onto the next HeapRegion_t structure. */
		xDefinedRegions++;
 80069e2:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 80069e4:	3301      	adds	r3, #1
 80069e6:	62fb      	str	r3, [r7, #44]	; 0x2c
		pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
 80069e8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 80069ea:	00db      	lsls	r3, r3, #3
 80069ec:	687a      	ldr	r2, [r7, #4]
 80069ee:	4413      	add	r3, r2
 80069f0:	627b      	str	r3, [r7, #36]	; 0x24
	while( pxHeapRegion->xSizeInBytes > 0 )
 80069f2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80069f4:	685b      	ldr	r3, [r3, #4]
 80069f6:	2b00      	cmp	r3, #0
 80069f8:	f47f af7d 	bne.w	80068f6 <vPortDefineHeapRegions+0x3e>
	}

	xMinimumEverFreeBytesRemaining = xTotalHeapSize;
 80069fc:	4a10      	ldr	r2, [pc, #64]	; (8006a40 <vPortDefineHeapRegions+0x188>)
 80069fe:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8006a00:	6013      	str	r3, [r2, #0]
	xFreeBytesRemaining = xTotalHeapSize;
 8006a02:	4a10      	ldr	r2, [pc, #64]	; (8006a44 <vPortDefineHeapRegions+0x18c>)
 8006a04:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8006a06:	6013      	str	r3, [r2, #0]

	/* Check something was actually defined before it is accessed. */
	configASSERT( xTotalHeapSize );
 8006a08:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8006a0a:	2b00      	cmp	r3, #0
 8006a0c:	d10a      	bne.n	8006a24 <vPortDefineHeapRegions+0x16c>
	__asm volatile
 8006a0e:	f04f 0350 	mov.w	r3, #80	; 0x50
 8006a12:	f383 8811 	msr	BASEPRI, r3
 8006a16:	f3bf 8f6f 	isb	sy
 8006a1a:	f3bf 8f4f 	dsb	sy
 8006a1e:	60bb      	str	r3, [r7, #8]
}
 8006a20:	bf00      	nop
 8006a22:	e7fe      	b.n	8006a22 <vPortDefineHeapRegions+0x16a>

	/* Work out the position of the top bit in a size_t variable. */
	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
 8006a24:	4b08      	ldr	r3, [pc, #32]	; (8006a48 <vPortDefineHeapRegions+0x190>)
 8006a26:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
 8006a2a:	601a      	str	r2, [r3, #0]
}
 8006a2c:	bf00      	nop
 8006a2e:	373c      	adds	r7, #60	; 0x3c
 8006a30:	46bd      	mov	sp, r7
 8006a32:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006a36:	4770      	bx	lr
 8006a38:	20003f18 	.word	0x20003f18
 8006a3c:	20003f10 	.word	0x20003f10
 8006a40:	20003f20 	.word	0x20003f20
 8006a44:	20003f1c 	.word	0x20003f1c
 8006a48:	20003f2c 	.word	0x20003f2c

08006a4c <__libc_init_array>:
 8006a4c:	b570      	push	{r4, r5, r6, lr}
 8006a4e:	4d0d      	ldr	r5, [pc, #52]	; (8006a84 <__libc_init_array+0x38>)
 8006a50:	4c0d      	ldr	r4, [pc, #52]	; (8006a88 <__libc_init_array+0x3c>)
 8006a52:	1b64      	subs	r4, r4, r5
 8006a54:	10a4      	asrs	r4, r4, #2
 8006a56:	2600      	movs	r6, #0
 8006a58:	42a6      	cmp	r6, r4
 8006a5a:	d109      	bne.n	8006a70 <__libc_init_array+0x24>
 8006a5c:	4d0b      	ldr	r5, [pc, #44]	; (8006a8c <__libc_init_array+0x40>)
 8006a5e:	4c0c      	ldr	r4, [pc, #48]	; (8006a90 <__libc_init_array+0x44>)
 8006a60:	f000 f8f2 	bl	8006c48 <_init>
 8006a64:	1b64      	subs	r4, r4, r5
 8006a66:	10a4      	asrs	r4, r4, #2
 8006a68:	2600      	movs	r6, #0
 8006a6a:	42a6      	cmp	r6, r4
 8006a6c:	d105      	bne.n	8006a7a <__libc_init_array+0x2e>
 8006a6e:	bd70      	pop	{r4, r5, r6, pc}
 8006a70:	f855 3b04 	ldr.w	r3, [r5], #4
 8006a74:	4798      	blx	r3
 8006a76:	3601      	adds	r6, #1
 8006a78:	e7ee      	b.n	8006a58 <__libc_init_array+0xc>
 8006a7a:	f855 3b04 	ldr.w	r3, [r5], #4
 8006a7e:	4798      	blx	r3
 8006a80:	3601      	adds	r6, #1
 8006a82:	e7f2      	b.n	8006a6a <__libc_init_array+0x1e>
 8006a84:	08006d88 	.word	0x08006d88
 8006a88:	08006d88 	.word	0x08006d88
 8006a8c:	08006d88 	.word	0x08006d88
 8006a90:	08006d8c 	.word	0x08006d8c

08006a94 <__retarget_lock_acquire_recursive>:
 8006a94:	4770      	bx	lr

08006a96 <__retarget_lock_release_recursive>:
 8006a96:	4770      	bx	lr

08006a98 <memcpy>:
 8006a98:	440a      	add	r2, r1
 8006a9a:	4291      	cmp	r1, r2
 8006a9c:	f100 33ff 	add.w	r3, r0, #4294967295
 8006aa0:	d100      	bne.n	8006aa4 <memcpy+0xc>
 8006aa2:	4770      	bx	lr
 8006aa4:	b510      	push	{r4, lr}
 8006aa6:	f811 4b01 	ldrb.w	r4, [r1], #1
 8006aaa:	f803 4f01 	strb.w	r4, [r3, #1]!
 8006aae:	4291      	cmp	r1, r2
 8006ab0:	d1f9      	bne.n	8006aa6 <memcpy+0xe>
 8006ab2:	bd10      	pop	{r4, pc}

08006ab4 <memset>:
 8006ab4:	4402      	add	r2, r0
 8006ab6:	4603      	mov	r3, r0
 8006ab8:	4293      	cmp	r3, r2
 8006aba:	d100      	bne.n	8006abe <memset+0xa>
 8006abc:	4770      	bx	lr
 8006abe:	f803 1b01 	strb.w	r1, [r3], #1
 8006ac2:	e7f9      	b.n	8006ab8 <memset+0x4>

08006ac4 <cleanup_glue>:
 8006ac4:	b538      	push	{r3, r4, r5, lr}
 8006ac6:	460c      	mov	r4, r1
 8006ac8:	6809      	ldr	r1, [r1, #0]
 8006aca:	4605      	mov	r5, r0
 8006acc:	b109      	cbz	r1, 8006ad2 <cleanup_glue+0xe>
 8006ace:	f7ff fff9 	bl	8006ac4 <cleanup_glue>
 8006ad2:	4621      	mov	r1, r4
 8006ad4:	4628      	mov	r0, r5
 8006ad6:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8006ada:	f000 b869 	b.w	8006bb0 <_free_r>
	...

08006ae0 <_reclaim_reent>:
 8006ae0:	4b2c      	ldr	r3, [pc, #176]	; (8006b94 <_reclaim_reent+0xb4>)
 8006ae2:	681b      	ldr	r3, [r3, #0]
 8006ae4:	4283      	cmp	r3, r0
 8006ae6:	b570      	push	{r4, r5, r6, lr}
 8006ae8:	4604      	mov	r4, r0
 8006aea:	d051      	beq.n	8006b90 <_reclaim_reent+0xb0>
 8006aec:	6a43      	ldr	r3, [r0, #36]	; 0x24
 8006aee:	b143      	cbz	r3, 8006b02 <_reclaim_reent+0x22>
 8006af0:	68db      	ldr	r3, [r3, #12]
 8006af2:	2b00      	cmp	r3, #0
 8006af4:	d14a      	bne.n	8006b8c <_reclaim_reent+0xac>
 8006af6:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8006af8:	6819      	ldr	r1, [r3, #0]
 8006afa:	b111      	cbz	r1, 8006b02 <_reclaim_reent+0x22>
 8006afc:	4620      	mov	r0, r4
 8006afe:	f000 f857 	bl	8006bb0 <_free_r>
 8006b02:	6961      	ldr	r1, [r4, #20]
 8006b04:	b111      	cbz	r1, 8006b0c <_reclaim_reent+0x2c>
 8006b06:	4620      	mov	r0, r4
 8006b08:	f000 f852 	bl	8006bb0 <_free_r>
 8006b0c:	6a61      	ldr	r1, [r4, #36]	; 0x24
 8006b0e:	b111      	cbz	r1, 8006b16 <_reclaim_reent+0x36>
 8006b10:	4620      	mov	r0, r4
 8006b12:	f000 f84d 	bl	8006bb0 <_free_r>
 8006b16:	6ba1      	ldr	r1, [r4, #56]	; 0x38
 8006b18:	b111      	cbz	r1, 8006b20 <_reclaim_reent+0x40>
 8006b1a:	4620      	mov	r0, r4
 8006b1c:	f000 f848 	bl	8006bb0 <_free_r>
 8006b20:	6be1      	ldr	r1, [r4, #60]	; 0x3c
 8006b22:	b111      	cbz	r1, 8006b2a <_reclaim_reent+0x4a>
 8006b24:	4620      	mov	r0, r4
 8006b26:	f000 f843 	bl	8006bb0 <_free_r>
 8006b2a:	6c21      	ldr	r1, [r4, #64]	; 0x40
 8006b2c:	b111      	cbz	r1, 8006b34 <_reclaim_reent+0x54>
 8006b2e:	4620      	mov	r0, r4
 8006b30:	f000 f83e 	bl	8006bb0 <_free_r>
 8006b34:	6de1      	ldr	r1, [r4, #92]	; 0x5c
 8006b36:	b111      	cbz	r1, 8006b3e <_reclaim_reent+0x5e>
 8006b38:	4620      	mov	r0, r4
 8006b3a:	f000 f839 	bl	8006bb0 <_free_r>
 8006b3e:	6da1      	ldr	r1, [r4, #88]	; 0x58
 8006b40:	b111      	cbz	r1, 8006b48 <_reclaim_reent+0x68>
 8006b42:	4620      	mov	r0, r4
 8006b44:	f000 f834 	bl	8006bb0 <_free_r>
 8006b48:	6b61      	ldr	r1, [r4, #52]	; 0x34
 8006b4a:	b111      	cbz	r1, 8006b52 <_reclaim_reent+0x72>
 8006b4c:	4620      	mov	r0, r4
 8006b4e:	f000 f82f 	bl	8006bb0 <_free_r>
 8006b52:	69a3      	ldr	r3, [r4, #24]
 8006b54:	b1e3      	cbz	r3, 8006b90 <_reclaim_reent+0xb0>
 8006b56:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8006b58:	4620      	mov	r0, r4
 8006b5a:	4798      	blx	r3
 8006b5c:	6ca1      	ldr	r1, [r4, #72]	; 0x48
 8006b5e:	b1b9      	cbz	r1, 8006b90 <_reclaim_reent+0xb0>
 8006b60:	4620      	mov	r0, r4
 8006b62:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
 8006b66:	f7ff bfad 	b.w	8006ac4 <cleanup_glue>
 8006b6a:	5949      	ldr	r1, [r1, r5]
 8006b6c:	b941      	cbnz	r1, 8006b80 <_reclaim_reent+0xa0>
 8006b6e:	3504      	adds	r5, #4
 8006b70:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8006b72:	2d80      	cmp	r5, #128	; 0x80
 8006b74:	68d9      	ldr	r1, [r3, #12]
 8006b76:	d1f8      	bne.n	8006b6a <_reclaim_reent+0x8a>
 8006b78:	4620      	mov	r0, r4
 8006b7a:	f000 f819 	bl	8006bb0 <_free_r>
 8006b7e:	e7ba      	b.n	8006af6 <_reclaim_reent+0x16>
 8006b80:	680e      	ldr	r6, [r1, #0]
 8006b82:	4620      	mov	r0, r4
 8006b84:	f000 f814 	bl	8006bb0 <_free_r>
 8006b88:	4631      	mov	r1, r6
 8006b8a:	e7ef      	b.n	8006b6c <_reclaim_reent+0x8c>
 8006b8c:	2500      	movs	r5, #0
 8006b8e:	e7ef      	b.n	8006b70 <_reclaim_reent+0x90>
 8006b90:	bd70      	pop	{r4, r5, r6, pc}
 8006b92:	bf00      	nop
 8006b94:	20000020 	.word	0x20000020

08006b98 <__malloc_lock>:
 8006b98:	4801      	ldr	r0, [pc, #4]	; (8006ba0 <__malloc_lock+0x8>)
 8006b9a:	f7ff bf7b 	b.w	8006a94 <__retarget_lock_acquire_recursive>
 8006b9e:	bf00      	nop
 8006ba0:	20003f30 	.word	0x20003f30

08006ba4 <__malloc_unlock>:
 8006ba4:	4801      	ldr	r0, [pc, #4]	; (8006bac <__malloc_unlock+0x8>)
 8006ba6:	f7ff bf76 	b.w	8006a96 <__retarget_lock_release_recursive>
 8006baa:	bf00      	nop
 8006bac:	20003f30 	.word	0x20003f30

08006bb0 <_free_r>:
 8006bb0:	b537      	push	{r0, r1, r2, r4, r5, lr}
 8006bb2:	2900      	cmp	r1, #0
 8006bb4:	d044      	beq.n	8006c40 <_free_r+0x90>
 8006bb6:	f851 3c04 	ldr.w	r3, [r1, #-4]
 8006bba:	9001      	str	r0, [sp, #4]
 8006bbc:	2b00      	cmp	r3, #0
 8006bbe:	f1a1 0404 	sub.w	r4, r1, #4
 8006bc2:	bfb8      	it	lt
 8006bc4:	18e4      	addlt	r4, r4, r3
 8006bc6:	f7ff ffe7 	bl	8006b98 <__malloc_lock>
 8006bca:	4a1e      	ldr	r2, [pc, #120]	; (8006c44 <_free_r+0x94>)
 8006bcc:	9801      	ldr	r0, [sp, #4]
 8006bce:	6813      	ldr	r3, [r2, #0]
 8006bd0:	b933      	cbnz	r3, 8006be0 <_free_r+0x30>
 8006bd2:	6063      	str	r3, [r4, #4]
 8006bd4:	6014      	str	r4, [r2, #0]
 8006bd6:	b003      	add	sp, #12
 8006bd8:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
 8006bdc:	f7ff bfe2 	b.w	8006ba4 <__malloc_unlock>
 8006be0:	42a3      	cmp	r3, r4
 8006be2:	d908      	bls.n	8006bf6 <_free_r+0x46>
 8006be4:	6825      	ldr	r5, [r4, #0]
 8006be6:	1961      	adds	r1, r4, r5
 8006be8:	428b      	cmp	r3, r1
 8006bea:	bf01      	itttt	eq
 8006bec:	6819      	ldreq	r1, [r3, #0]
 8006bee:	685b      	ldreq	r3, [r3, #4]
 8006bf0:	1949      	addeq	r1, r1, r5
 8006bf2:	6021      	streq	r1, [r4, #0]
 8006bf4:	e7ed      	b.n	8006bd2 <_free_r+0x22>
 8006bf6:	461a      	mov	r2, r3
 8006bf8:	685b      	ldr	r3, [r3, #4]
 8006bfa:	b10b      	cbz	r3, 8006c00 <_free_r+0x50>
 8006bfc:	42a3      	cmp	r3, r4
 8006bfe:	d9fa      	bls.n	8006bf6 <_free_r+0x46>
 8006c00:	6811      	ldr	r1, [r2, #0]
 8006c02:	1855      	adds	r5, r2, r1
 8006c04:	42a5      	cmp	r5, r4
 8006c06:	d10b      	bne.n	8006c20 <_free_r+0x70>
 8006c08:	6824      	ldr	r4, [r4, #0]
 8006c0a:	4421      	add	r1, r4
 8006c0c:	1854      	adds	r4, r2, r1
 8006c0e:	42a3      	cmp	r3, r4
 8006c10:	6011      	str	r1, [r2, #0]
 8006c12:	d1e0      	bne.n	8006bd6 <_free_r+0x26>
 8006c14:	681c      	ldr	r4, [r3, #0]
 8006c16:	685b      	ldr	r3, [r3, #4]
 8006c18:	6053      	str	r3, [r2, #4]
 8006c1a:	4421      	add	r1, r4
 8006c1c:	6011      	str	r1, [r2, #0]
 8006c1e:	e7da      	b.n	8006bd6 <_free_r+0x26>
 8006c20:	d902      	bls.n	8006c28 <_free_r+0x78>
 8006c22:	230c      	movs	r3, #12
 8006c24:	6003      	str	r3, [r0, #0]
 8006c26:	e7d6      	b.n	8006bd6 <_free_r+0x26>
 8006c28:	6825      	ldr	r5, [r4, #0]
 8006c2a:	1961      	adds	r1, r4, r5
 8006c2c:	428b      	cmp	r3, r1
 8006c2e:	bf04      	itt	eq
 8006c30:	6819      	ldreq	r1, [r3, #0]
 8006c32:	685b      	ldreq	r3, [r3, #4]
 8006c34:	6063      	str	r3, [r4, #4]
 8006c36:	bf04      	itt	eq
 8006c38:	1949      	addeq	r1, r1, r5
 8006c3a:	6021      	streq	r1, [r4, #0]
 8006c3c:	6054      	str	r4, [r2, #4]
 8006c3e:	e7ca      	b.n	8006bd6 <_free_r+0x26>
 8006c40:	b003      	add	sp, #12
 8006c42:	bd30      	pop	{r4, r5, pc}
 8006c44:	20003f34 	.word	0x20003f34

08006c48 <_init>:
 8006c48:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006c4a:	bf00      	nop
 8006c4c:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8006c4e:	bc08      	pop	{r3}
 8006c50:	469e      	mov	lr, r3
 8006c52:	4770      	bx	lr

08006c54 <_fini>:
 8006c54:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006c56:	bf00      	nop
 8006c58:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8006c5a:	bc08      	pop	{r3}
 8006c5c:	469e      	mov	lr, r3
 8006c5e:	4770      	bx	lr
