mirror of
http://zjk.pl:3300/Preacher/STM32L476RG.git
synced 2025-01-22 23:46:33 +01:00
16415 lines
625 KiB
Plaintext
16415 lines
625 KiB
Plaintext
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STM32L476RG.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00005b50 08000190 08000190 00010190 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 000000f0 08005ce0 08005ce0 00015ce0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08005dd0 08005dd0 00020084 2**0
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CONTENTS
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4 .ARM 00000008 08005dd0 08005dd0 00015dd0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 08005dd8 08005dd8 00020084 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08005dd8 08005dd8 00015dd8 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 08005ddc 08005ddc 00015ddc 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 00000084 20000000 08005de0 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00003da0 20000084 08005e64 00020084 2**2
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ALLOC
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10 ._user_heap_stack 00000604 20003e24 08005e64 00023e24 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 00020084 2**0
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CONTENTS, READONLY
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12 .debug_info 0001613d 00000000 00000000 000200b4 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00002f1d 00000000 00000000 000361f1 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00001108 00000000 00000000 00039110 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_ranges 00000fe0 00000000 00000000 0003a218 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00027f41 00000000 00000000 0003b1f8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 00013cc7 00000000 00000000 00063139 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000f33db 00000000 00000000 00076e00 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000050 00000000 00000000 0016a1db 2**0
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CONTENTS, READONLY
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20 .debug_frame 00004848 00000000 00000000 0016a22c 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000190 <__do_global_dtors_aux>:
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8000190: b510 push {r4, lr}
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8000192: 4c05 ldr r4, [pc, #20] ; (80001a8 <__do_global_dtors_aux+0x18>)
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8000194: 7823 ldrb r3, [r4, #0]
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8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16>
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8000198: 4b04 ldr r3, [pc, #16] ; (80001ac <__do_global_dtors_aux+0x1c>)
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800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12>
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800019c: 4804 ldr r0, [pc, #16] ; (80001b0 <__do_global_dtors_aux+0x20>)
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800019e: f3af 8000 nop.w
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80001a2: 2301 movs r3, #1
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80001a4: 7023 strb r3, [r4, #0]
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80001a6: bd10 pop {r4, pc}
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80001a8: 20000084 .word 0x20000084
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80001ac: 00000000 .word 0x00000000
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80001b0: 08005cc8 .word 0x08005cc8
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080001b4 <frame_dummy>:
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80001b4: b508 push {r3, lr}
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80001b6: 4b03 ldr r3, [pc, #12] ; (80001c4 <frame_dummy+0x10>)
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80001b8: b11b cbz r3, 80001c2 <frame_dummy+0xe>
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80001ba: 4903 ldr r1, [pc, #12] ; (80001c8 <frame_dummy+0x14>)
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80001bc: 4803 ldr r0, [pc, #12] ; (80001cc <frame_dummy+0x18>)
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80001be: f3af 8000 nop.w
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80001c2: bd08 pop {r3, pc}
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80001c4: 00000000 .word 0x00000000
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80001c8: 20000088 .word 0x20000088
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80001cc: 08005cc8 .word 0x08005cc8
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080001d0 <__aeabi_uldivmod>:
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80001d0: b953 cbnz r3, 80001e8 <__aeabi_uldivmod+0x18>
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80001d2: b94a cbnz r2, 80001e8 <__aeabi_uldivmod+0x18>
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80001d4: 2900 cmp r1, #0
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80001d6: bf08 it eq
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80001d8: 2800 cmpeq r0, #0
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80001da: bf1c itt ne
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80001dc: f04f 31ff movne.w r1, #4294967295
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80001e0: f04f 30ff movne.w r0, #4294967295
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80001e4: f000 b974 b.w 80004d0 <__aeabi_idiv0>
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80001e8: f1ad 0c08 sub.w ip, sp, #8
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80001ec: e96d ce04 strd ip, lr, [sp, #-16]!
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80001f0: f000 f806 bl 8000200 <__udivmoddi4>
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80001f4: f8dd e004 ldr.w lr, [sp, #4]
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80001f8: e9dd 2302 ldrd r2, r3, [sp, #8]
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80001fc: b004 add sp, #16
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80001fe: 4770 bx lr
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08000200 <__udivmoddi4>:
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8000200: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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8000204: 9d08 ldr r5, [sp, #32]
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8000206: 4604 mov r4, r0
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8000208: 468e mov lr, r1
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800020a: 2b00 cmp r3, #0
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800020c: d14d bne.n 80002aa <__udivmoddi4+0xaa>
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800020e: 428a cmp r2, r1
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8000210: 4694 mov ip, r2
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8000212: d969 bls.n 80002e8 <__udivmoddi4+0xe8>
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8000214: fab2 f282 clz r2, r2
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8000218: b152 cbz r2, 8000230 <__udivmoddi4+0x30>
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800021a: fa01 f302 lsl.w r3, r1, r2
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800021e: f1c2 0120 rsb r1, r2, #32
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8000222: fa20 f101 lsr.w r1, r0, r1
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8000226: fa0c fc02 lsl.w ip, ip, r2
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800022a: ea41 0e03 orr.w lr, r1, r3
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800022e: 4094 lsls r4, r2
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8000230: ea4f 481c mov.w r8, ip, lsr #16
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8000234: 0c21 lsrs r1, r4, #16
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8000236: fbbe f6f8 udiv r6, lr, r8
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800023a: fa1f f78c uxth.w r7, ip
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800023e: fb08 e316 mls r3, r8, r6, lr
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8000242: ea41 4303 orr.w r3, r1, r3, lsl #16
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8000246: fb06 f107 mul.w r1, r6, r7
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800024a: 4299 cmp r1, r3
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800024c: d90a bls.n 8000264 <__udivmoddi4+0x64>
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800024e: eb1c 0303 adds.w r3, ip, r3
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8000252: f106 30ff add.w r0, r6, #4294967295
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8000256: f080 811f bcs.w 8000498 <__udivmoddi4+0x298>
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800025a: 4299 cmp r1, r3
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800025c: f240 811c bls.w 8000498 <__udivmoddi4+0x298>
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8000260: 3e02 subs r6, #2
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8000262: 4463 add r3, ip
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8000264: 1a5b subs r3, r3, r1
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8000266: b2a4 uxth r4, r4
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8000268: fbb3 f0f8 udiv r0, r3, r8
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800026c: fb08 3310 mls r3, r8, r0, r3
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8000270: ea44 4403 orr.w r4, r4, r3, lsl #16
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8000274: fb00 f707 mul.w r7, r0, r7
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8000278: 42a7 cmp r7, r4
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800027a: d90a bls.n 8000292 <__udivmoddi4+0x92>
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800027c: eb1c 0404 adds.w r4, ip, r4
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8000280: f100 33ff add.w r3, r0, #4294967295
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8000284: f080 810a bcs.w 800049c <__udivmoddi4+0x29c>
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8000288: 42a7 cmp r7, r4
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800028a: f240 8107 bls.w 800049c <__udivmoddi4+0x29c>
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800028e: 4464 add r4, ip
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8000290: 3802 subs r0, #2
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8000292: ea40 4006 orr.w r0, r0, r6, lsl #16
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8000296: 1be4 subs r4, r4, r7
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8000298: 2600 movs r6, #0
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800029a: b11d cbz r5, 80002a4 <__udivmoddi4+0xa4>
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800029c: 40d4 lsrs r4, r2
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800029e: 2300 movs r3, #0
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80002a0: e9c5 4300 strd r4, r3, [r5]
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80002a4: 4631 mov r1, r6
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80002a6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002aa: 428b cmp r3, r1
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80002ac: d909 bls.n 80002c2 <__udivmoddi4+0xc2>
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80002ae: 2d00 cmp r5, #0
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80002b0: f000 80ef beq.w 8000492 <__udivmoddi4+0x292>
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80002b4: 2600 movs r6, #0
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80002b6: e9c5 0100 strd r0, r1, [r5]
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80002ba: 4630 mov r0, r6
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80002bc: 4631 mov r1, r6
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80002be: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002c2: fab3 f683 clz r6, r3
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80002c6: 2e00 cmp r6, #0
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80002c8: d14a bne.n 8000360 <__udivmoddi4+0x160>
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80002ca: 428b cmp r3, r1
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80002cc: d302 bcc.n 80002d4 <__udivmoddi4+0xd4>
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80002ce: 4282 cmp r2, r0
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80002d0: f200 80f9 bhi.w 80004c6 <__udivmoddi4+0x2c6>
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80002d4: 1a84 subs r4, r0, r2
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80002d6: eb61 0303 sbc.w r3, r1, r3
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80002da: 2001 movs r0, #1
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80002dc: 469e mov lr, r3
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80002de: 2d00 cmp r5, #0
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80002e0: d0e0 beq.n 80002a4 <__udivmoddi4+0xa4>
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80002e2: e9c5 4e00 strd r4, lr, [r5]
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80002e6: e7dd b.n 80002a4 <__udivmoddi4+0xa4>
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80002e8: b902 cbnz r2, 80002ec <__udivmoddi4+0xec>
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80002ea: deff udf #255 ; 0xff
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80002ec: fab2 f282 clz r2, r2
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80002f0: 2a00 cmp r2, #0
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80002f2: f040 8092 bne.w 800041a <__udivmoddi4+0x21a>
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80002f6: eba1 010c sub.w r1, r1, ip
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80002fa: ea4f 471c mov.w r7, ip, lsr #16
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80002fe: fa1f fe8c uxth.w lr, ip
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8000302: 2601 movs r6, #1
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8000304: 0c20 lsrs r0, r4, #16
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8000306: fbb1 f3f7 udiv r3, r1, r7
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800030a: fb07 1113 mls r1, r7, r3, r1
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800030e: ea40 4101 orr.w r1, r0, r1, lsl #16
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8000312: fb0e f003 mul.w r0, lr, r3
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8000316: 4288 cmp r0, r1
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8000318: d908 bls.n 800032c <__udivmoddi4+0x12c>
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800031a: eb1c 0101 adds.w r1, ip, r1
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800031e: f103 38ff add.w r8, r3, #4294967295
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8000322: d202 bcs.n 800032a <__udivmoddi4+0x12a>
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8000324: 4288 cmp r0, r1
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8000326: f200 80cb bhi.w 80004c0 <__udivmoddi4+0x2c0>
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800032a: 4643 mov r3, r8
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800032c: 1a09 subs r1, r1, r0
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800032e: b2a4 uxth r4, r4
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8000330: fbb1 f0f7 udiv r0, r1, r7
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8000334: fb07 1110 mls r1, r7, r0, r1
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8000338: ea44 4401 orr.w r4, r4, r1, lsl #16
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800033c: fb0e fe00 mul.w lr, lr, r0
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8000340: 45a6 cmp lr, r4
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8000342: d908 bls.n 8000356 <__udivmoddi4+0x156>
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8000344: eb1c 0404 adds.w r4, ip, r4
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8000348: f100 31ff add.w r1, r0, #4294967295
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800034c: d202 bcs.n 8000354 <__udivmoddi4+0x154>
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800034e: 45a6 cmp lr, r4
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8000350: f200 80bb bhi.w 80004ca <__udivmoddi4+0x2ca>
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8000354: 4608 mov r0, r1
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8000356: eba4 040e sub.w r4, r4, lr
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800035a: ea40 4003 orr.w r0, r0, r3, lsl #16
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800035e: e79c b.n 800029a <__udivmoddi4+0x9a>
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8000360: f1c6 0720 rsb r7, r6, #32
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8000364: 40b3 lsls r3, r6
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8000366: fa22 fc07 lsr.w ip, r2, r7
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800036a: ea4c 0c03 orr.w ip, ip, r3
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800036e: fa20 f407 lsr.w r4, r0, r7
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8000372: fa01 f306 lsl.w r3, r1, r6
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8000376: 431c orrs r4, r3
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8000378: 40f9 lsrs r1, r7
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800037a: ea4f 491c mov.w r9, ip, lsr #16
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800037e: fa00 f306 lsl.w r3, r0, r6
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8000382: fbb1 f8f9 udiv r8, r1, r9
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8000386: 0c20 lsrs r0, r4, #16
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8000388: fa1f fe8c uxth.w lr, ip
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800038c: fb09 1118 mls r1, r9, r8, r1
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8000390: ea40 4101 orr.w r1, r0, r1, lsl #16
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8000394: fb08 f00e mul.w r0, r8, lr
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8000398: 4288 cmp r0, r1
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800039a: fa02 f206 lsl.w r2, r2, r6
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800039e: d90b bls.n 80003b8 <__udivmoddi4+0x1b8>
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80003a0: eb1c 0101 adds.w r1, ip, r1
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80003a4: f108 3aff add.w sl, r8, #4294967295
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80003a8: f080 8088 bcs.w 80004bc <__udivmoddi4+0x2bc>
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80003ac: 4288 cmp r0, r1
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80003ae: f240 8085 bls.w 80004bc <__udivmoddi4+0x2bc>
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80003b2: f1a8 0802 sub.w r8, r8, #2
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80003b6: 4461 add r1, ip
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80003b8: 1a09 subs r1, r1, r0
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80003ba: b2a4 uxth r4, r4
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80003bc: fbb1 f0f9 udiv r0, r1, r9
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80003c0: fb09 1110 mls r1, r9, r0, r1
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80003c4: ea44 4101 orr.w r1, r4, r1, lsl #16
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80003c8: fb00 fe0e mul.w lr, r0, lr
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80003cc: 458e cmp lr, r1
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80003ce: d908 bls.n 80003e2 <__udivmoddi4+0x1e2>
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80003d0: eb1c 0101 adds.w r1, ip, r1
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|
|
80003d4: f100 34ff add.w r4, r0, #4294967295
|
||
|
|
80003d8: d26c bcs.n 80004b4 <__udivmoddi4+0x2b4>
|
||
|
|
80003da: 458e cmp lr, r1
|
||
|
|
80003dc: d96a bls.n 80004b4 <__udivmoddi4+0x2b4>
|
||
|
|
80003de: 3802 subs r0, #2
|
||
|
|
80003e0: 4461 add r1, ip
|
||
|
|
80003e2: ea40 4008 orr.w r0, r0, r8, lsl #16
|
||
|
|
80003e6: fba0 9402 umull r9, r4, r0, r2
|
||
|
|
80003ea: eba1 010e sub.w r1, r1, lr
|
||
|
|
80003ee: 42a1 cmp r1, r4
|
||
|
|
80003f0: 46c8 mov r8, r9
|
||
|
|
80003f2: 46a6 mov lr, r4
|
||
|
|
80003f4: d356 bcc.n 80004a4 <__udivmoddi4+0x2a4>
|
||
|
|
80003f6: d053 beq.n 80004a0 <__udivmoddi4+0x2a0>
|
||
|
|
80003f8: b15d cbz r5, 8000412 <__udivmoddi4+0x212>
|
||
|
|
80003fa: ebb3 0208 subs.w r2, r3, r8
|
||
|
|
80003fe: eb61 010e sbc.w r1, r1, lr
|
||
|
|
8000402: fa01 f707 lsl.w r7, r1, r7
|
||
|
|
8000406: fa22 f306 lsr.w r3, r2, r6
|
||
|
|
800040a: 40f1 lsrs r1, r6
|
||
|
|
800040c: 431f orrs r7, r3
|
||
|
|
800040e: e9c5 7100 strd r7, r1, [r5]
|
||
|
|
8000412: 2600 movs r6, #0
|
||
|
|
8000414: 4631 mov r1, r6
|
||
|
|
8000416: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
||
|
|
800041a: f1c2 0320 rsb r3, r2, #32
|
||
|
|
800041e: 40d8 lsrs r0, r3
|
||
|
|
8000420: fa0c fc02 lsl.w ip, ip, r2
|
||
|
|
8000424: fa21 f303 lsr.w r3, r1, r3
|
||
|
|
8000428: 4091 lsls r1, r2
|
||
|
|
800042a: 4301 orrs r1, r0
|
||
|
|
800042c: ea4f 471c mov.w r7, ip, lsr #16
|
||
|
|
8000430: fa1f fe8c uxth.w lr, ip
|
||
|
|
8000434: fbb3 f0f7 udiv r0, r3, r7
|
||
|
|
8000438: fb07 3610 mls r6, r7, r0, r3
|
||
|
|
800043c: 0c0b lsrs r3, r1, #16
|
||
|
|
800043e: ea43 4306 orr.w r3, r3, r6, lsl #16
|
||
|
|
8000442: fb00 f60e mul.w r6, r0, lr
|
||
|
|
8000446: 429e cmp r6, r3
|
||
|
|
8000448: fa04 f402 lsl.w r4, r4, r2
|
||
|
|
800044c: d908 bls.n 8000460 <__udivmoddi4+0x260>
|
||
|
|
800044e: eb1c 0303 adds.w r3, ip, r3
|
||
|
|
8000452: f100 38ff add.w r8, r0, #4294967295
|
||
|
|
8000456: d22f bcs.n 80004b8 <__udivmoddi4+0x2b8>
|
||
|
|
8000458: 429e cmp r6, r3
|
||
|
|
800045a: d92d bls.n 80004b8 <__udivmoddi4+0x2b8>
|
||
|
|
800045c: 3802 subs r0, #2
|
||
|
|
800045e: 4463 add r3, ip
|
||
|
|
8000460: 1b9b subs r3, r3, r6
|
||
|
|
8000462: b289 uxth r1, r1
|
||
|
|
8000464: fbb3 f6f7 udiv r6, r3, r7
|
||
|
|
8000468: fb07 3316 mls r3, r7, r6, r3
|
||
|
|
800046c: ea41 4103 orr.w r1, r1, r3, lsl #16
|
||
|
|
8000470: fb06 f30e mul.w r3, r6, lr
|
||
|
|
8000474: 428b cmp r3, r1
|
||
|
|
8000476: d908 bls.n 800048a <__udivmoddi4+0x28a>
|
||
|
|
8000478: eb1c 0101 adds.w r1, ip, r1
|
||
|
|
800047c: f106 38ff add.w r8, r6, #4294967295
|
||
|
|
8000480: d216 bcs.n 80004b0 <__udivmoddi4+0x2b0>
|
||
|
|
8000482: 428b cmp r3, r1
|
||
|
|
8000484: d914 bls.n 80004b0 <__udivmoddi4+0x2b0>
|
||
|
|
8000486: 3e02 subs r6, #2
|
||
|
|
8000488: 4461 add r1, ip
|
||
|
|
800048a: 1ac9 subs r1, r1, r3
|
||
|
|
800048c: ea46 4600 orr.w r6, r6, r0, lsl #16
|
||
|
|
8000490: e738 b.n 8000304 <__udivmoddi4+0x104>
|
||
|
|
8000492: 462e mov r6, r5
|
||
|
|
8000494: 4628 mov r0, r5
|
||
|
|
8000496: e705 b.n 80002a4 <__udivmoddi4+0xa4>
|
||
|
|
8000498: 4606 mov r6, r0
|
||
|
|
800049a: e6e3 b.n 8000264 <__udivmoddi4+0x64>
|
||
|
|
800049c: 4618 mov r0, r3
|
||
|
|
800049e: e6f8 b.n 8000292 <__udivmoddi4+0x92>
|
||
|
|
80004a0: 454b cmp r3, r9
|
||
|
|
80004a2: d2a9 bcs.n 80003f8 <__udivmoddi4+0x1f8>
|
||
|
|
80004a4: ebb9 0802 subs.w r8, r9, r2
|
||
|
|
80004a8: eb64 0e0c sbc.w lr, r4, ip
|
||
|
|
80004ac: 3801 subs r0, #1
|
||
|
|
80004ae: e7a3 b.n 80003f8 <__udivmoddi4+0x1f8>
|
||
|
|
80004b0: 4646 mov r6, r8
|
||
|
|
80004b2: e7ea b.n 800048a <__udivmoddi4+0x28a>
|
||
|
|
80004b4: 4620 mov r0, r4
|
||
|
|
80004b6: e794 b.n 80003e2 <__udivmoddi4+0x1e2>
|
||
|
|
80004b8: 4640 mov r0, r8
|
||
|
|
80004ba: e7d1 b.n 8000460 <__udivmoddi4+0x260>
|
||
|
|
80004bc: 46d0 mov r8, sl
|
||
|
|
80004be: e77b b.n 80003b8 <__udivmoddi4+0x1b8>
|
||
|
|
80004c0: 3b02 subs r3, #2
|
||
|
|
80004c2: 4461 add r1, ip
|
||
|
|
80004c4: e732 b.n 800032c <__udivmoddi4+0x12c>
|
||
|
|
80004c6: 4630 mov r0, r6
|
||
|
|
80004c8: e709 b.n 80002de <__udivmoddi4+0xde>
|
||
|
|
80004ca: 4464 add r4, ip
|
||
|
|
80004cc: 3802 subs r0, #2
|
||
|
|
80004ce: e742 b.n 8000356 <__udivmoddi4+0x156>
|
||
|
|
|
||
|
|
080004d0 <__aeabi_idiv0>:
|
||
|
|
80004d0: 4770 bx lr
|
||
|
|
80004d2: bf00 nop
|
||
|
|
|
||
|
|
080004d4 <vApplicationIdleHook>:
|
||
|
|
void vApplicationIdleHook(void);
|
||
|
|
void vApplicationTickHook(void);
|
||
|
|
|
||
|
|
/* USER CODE BEGIN 2 */
|
||
|
|
void vApplicationIdleHook( void )
|
||
|
|
{
|
||
|
|
80004d4: b480 push {r7}
|
||
|
|
80004d6: af00 add r7, sp, #0
|
||
|
|
specified, or call vTaskDelay()). If the application makes use of the
|
||
|
|
vTaskDelete() API function (as this demo application does) then it is also
|
||
|
|
important that vApplicationIdleHook() is permitted to return to its calling
|
||
|
|
function, because it is the responsibility of the idle task to clean up
|
||
|
|
memory allocated by the kernel to any task that has since been deleted. */
|
||
|
|
}
|
||
|
|
80004d8: bf00 nop
|
||
|
|
80004da: 46bd mov sp, r7
|
||
|
|
80004dc: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80004e0: 4770 bx lr
|
||
|
|
|
||
|
|
080004e2 <vApplicationTickHook>:
|
||
|
|
/* USER CODE END 2 */
|
||
|
|
|
||
|
|
/* USER CODE BEGIN 3 */
|
||
|
|
void vApplicationTickHook( void )
|
||
|
|
{
|
||
|
|
80004e2: b480 push {r7}
|
||
|
|
80004e4: af00 add r7, sp, #0
|
||
|
|
/* This function will be called by each tick interrupt if
|
||
|
|
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
|
||
|
|
added here, but the tick hook is called from an interrupt context, so
|
||
|
|
code must not attempt to block, and only the interrupt safe FreeRTOS API
|
||
|
|
functions can be used (those that end in FromISR()). */
|
||
|
|
}
|
||
|
|
80004e6: bf00 nop
|
||
|
|
80004e8: 46bd mov sp, r7
|
||
|
|
80004ea: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80004ee: 4770 bx lr
|
||
|
|
|
||
|
|
080004f0 <MX_FREERTOS_Init>:
|
||
|
|
/**
|
||
|
|
* @brief FreeRTOS initialization
|
||
|
|
* @param None
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void MX_FREERTOS_Init(void) {
|
||
|
|
80004f0: b580 push {r7, lr}
|
||
|
|
80004f2: af00 add r7, sp, #0
|
||
|
|
/* add queues, ... */
|
||
|
|
/* USER CODE END RTOS_QUEUES */
|
||
|
|
|
||
|
|
/* Create the thread(s) */
|
||
|
|
/* creation of defaultTask */
|
||
|
|
defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
|
||
|
|
80004f4: 4a04 ldr r2, [pc, #16] ; (8000508 <MX_FREERTOS_Init+0x18>)
|
||
|
|
80004f6: 2100 movs r1, #0
|
||
|
|
80004f8: 4804 ldr r0, [pc, #16] ; (800050c <MX_FREERTOS_Init+0x1c>)
|
||
|
|
80004fa: f002 fd6f bl 8002fdc <osThreadNew>
|
||
|
|
80004fe: 4603 mov r3, r0
|
||
|
|
8000500: 4a03 ldr r2, [pc, #12] ; (8000510 <MX_FREERTOS_Init+0x20>)
|
||
|
|
8000502: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* USER CODE BEGIN RTOS_EVENTS */
|
||
|
|
/* add events, ... */
|
||
|
|
/* USER CODE END RTOS_EVENTS */
|
||
|
|
|
||
|
|
}
|
||
|
|
8000504: bf00 nop
|
||
|
|
8000506: bd80 pop {r7, pc}
|
||
|
|
8000508: 08005d04 .word 0x08005d04
|
||
|
|
800050c: 08000515 .word 0x08000515
|
||
|
|
8000510: 200000a0 .word 0x200000a0
|
||
|
|
|
||
|
|
08000514 <StartDefaultTask>:
|
||
|
|
* @param argument: Not used
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
/* USER CODE END Header_StartDefaultTask */
|
||
|
|
void StartDefaultTask(void *argument)
|
||
|
|
{
|
||
|
|
8000514: b580 push {r7, lr}
|
||
|
|
8000516: b082 sub sp, #8
|
||
|
|
8000518: af00 add r7, sp, #0
|
||
|
|
800051a: 6078 str r0, [r7, #4]
|
||
|
|
/* USER CODE BEGIN StartDefaultTask */
|
||
|
|
/* Infinite loop */
|
||
|
|
for(;;)
|
||
|
|
{
|
||
|
|
osDelay(1);
|
||
|
|
800051c: 2001 movs r0, #1
|
||
|
|
800051e: f002 fdef bl 8003100 <osDelay>
|
||
|
|
8000522: e7fb b.n 800051c <StartDefaultTask+0x8>
|
||
|
|
|
||
|
|
08000524 <MX_GPIO_Init>:
|
||
|
|
* Output
|
||
|
|
* EVENT_OUT
|
||
|
|
* EXTI
|
||
|
|
*/
|
||
|
|
void MX_GPIO_Init(void)
|
||
|
|
{
|
||
|
|
8000524: b580 push {r7, lr}
|
||
|
|
8000526: b08a sub sp, #40 ; 0x28
|
||
|
|
8000528: af00 add r7, sp, #0
|
||
|
|
|
||
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||
|
|
800052a: f107 0314 add.w r3, r7, #20
|
||
|
|
800052e: 2200 movs r2, #0
|
||
|
|
8000530: 601a str r2, [r3, #0]
|
||
|
|
8000532: 605a str r2, [r3, #4]
|
||
|
|
8000534: 609a str r2, [r3, #8]
|
||
|
|
8000536: 60da str r2, [r3, #12]
|
||
|
|
8000538: 611a str r2, [r3, #16]
|
||
|
|
|
||
|
|
/* GPIO Ports Clock Enable */
|
||
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||
|
|
800053a: 4b2b ldr r3, [pc, #172] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
800053c: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
800053e: 4a2a ldr r2, [pc, #168] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
8000540: f043 0304 orr.w r3, r3, #4
|
||
|
|
8000544: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
8000546: 4b28 ldr r3, [pc, #160] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
8000548: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
800054a: f003 0304 and.w r3, r3, #4
|
||
|
|
800054e: 613b str r3, [r7, #16]
|
||
|
|
8000550: 693b ldr r3, [r7, #16]
|
||
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||
|
|
8000552: 4b25 ldr r3, [pc, #148] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
8000554: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8000556: 4a24 ldr r2, [pc, #144] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
8000558: f043 0380 orr.w r3, r3, #128 ; 0x80
|
||
|
|
800055c: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
800055e: 4b22 ldr r3, [pc, #136] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
8000560: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8000562: f003 0380 and.w r3, r3, #128 ; 0x80
|
||
|
|
8000566: 60fb str r3, [r7, #12]
|
||
|
|
8000568: 68fb ldr r3, [r7, #12]
|
||
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||
|
|
800056a: 4b1f ldr r3, [pc, #124] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
800056c: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
800056e: 4a1e ldr r2, [pc, #120] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
8000570: f043 0301 orr.w r3, r3, #1
|
||
|
|
8000574: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
8000576: 4b1c ldr r3, [pc, #112] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
8000578: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
800057a: f003 0301 and.w r3, r3, #1
|
||
|
|
800057e: 60bb str r3, [r7, #8]
|
||
|
|
8000580: 68bb ldr r3, [r7, #8]
|
||
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||
|
|
8000582: 4b19 ldr r3, [pc, #100] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
8000584: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8000586: 4a18 ldr r2, [pc, #96] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
8000588: f043 0302 orr.w r3, r3, #2
|
||
|
|
800058c: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
800058e: 4b16 ldr r3, [pc, #88] ; (80005e8 <MX_GPIO_Init+0xc4>)
|
||
|
|
8000590: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8000592: f003 0302 and.w r3, r3, #2
|
||
|
|
8000596: 607b str r3, [r7, #4]
|
||
|
|
8000598: 687b ldr r3, [r7, #4]
|
||
|
|
|
||
|
|
/*Configure GPIO pin Output Level */
|
||
|
|
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
|
||
|
|
800059a: 2200 movs r2, #0
|
||
|
|
800059c: 2120 movs r1, #32
|
||
|
|
800059e: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
||
|
|
80005a2: f000 fcad bl 8000f00 <HAL_GPIO_WritePin>
|
||
|
|
|
||
|
|
/*Configure GPIO pin : PtPin */
|
||
|
|
GPIO_InitStruct.Pin = B1_Pin;
|
||
|
|
80005a6: f44f 5300 mov.w r3, #8192 ; 0x2000
|
||
|
|
80005aa: 617b str r3, [r7, #20]
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
||
|
|
80005ac: f44f 1304 mov.w r3, #2162688 ; 0x210000
|
||
|
|
80005b0: 61bb str r3, [r7, #24]
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
80005b2: 2300 movs r3, #0
|
||
|
|
80005b4: 61fb str r3, [r7, #28]
|
||
|
|
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
|
||
|
|
80005b6: f107 0314 add.w r3, r7, #20
|
||
|
|
80005ba: 4619 mov r1, r3
|
||
|
|
80005bc: 480b ldr r0, [pc, #44] ; (80005ec <MX_GPIO_Init+0xc8>)
|
||
|
|
80005be: f000 faf5 bl 8000bac <HAL_GPIO_Init>
|
||
|
|
|
||
|
|
/*Configure GPIO pin : PtPin */
|
||
|
|
GPIO_InitStruct.Pin = LD2_Pin;
|
||
|
|
80005c2: 2320 movs r3, #32
|
||
|
|
80005c4: 617b str r3, [r7, #20]
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||
|
|
80005c6: 2301 movs r3, #1
|
||
|
|
80005c8: 61bb str r3, [r7, #24]
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
80005ca: 2300 movs r3, #0
|
||
|
|
80005cc: 61fb str r3, [r7, #28]
|
||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||
|
|
80005ce: 2300 movs r3, #0
|
||
|
|
80005d0: 623b str r3, [r7, #32]
|
||
|
|
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
|
||
|
|
80005d2: f107 0314 add.w r3, r7, #20
|
||
|
|
80005d6: 4619 mov r1, r3
|
||
|
|
80005d8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
||
|
|
80005dc: f000 fae6 bl 8000bac <HAL_GPIO_Init>
|
||
|
|
|
||
|
|
}
|
||
|
|
80005e0: bf00 nop
|
||
|
|
80005e2: 3728 adds r7, #40 ; 0x28
|
||
|
|
80005e4: 46bd mov sp, r7
|
||
|
|
80005e6: bd80 pop {r7, pc}
|
||
|
|
80005e8: 40021000 .word 0x40021000
|
||
|
|
80005ec: 48000800 .word 0x48000800
|
||
|
|
|
||
|
|
080005f0 <main>:
|
||
|
|
/**
|
||
|
|
* @brief The application entry point.
|
||
|
|
* @retval int
|
||
|
|
*/
|
||
|
|
int main(void)
|
||
|
|
{
|
||
|
|
80005f0: b580 push {r7, lr}
|
||
|
|
80005f2: af00 add r7, sp, #0
|
||
|
|
/* USER CODE END 1 */
|
||
|
|
|
||
|
|
/* MCU Configuration--------------------------------------------------------*/
|
||
|
|
|
||
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
||
|
|
HAL_Init();
|
||
|
|
80005f4: f000 f978 bl 80008e8 <HAL_Init>
|
||
|
|
/* USER CODE BEGIN Init */
|
||
|
|
|
||
|
|
/* USER CODE END Init */
|
||
|
|
|
||
|
|
/* Configure the system clock */
|
||
|
|
SystemClock_Config();
|
||
|
|
80005f8: f000 f80b bl 8000612 <SystemClock_Config>
|
||
|
|
/* USER CODE BEGIN SysInit */
|
||
|
|
|
||
|
|
/* USER CODE END SysInit */
|
||
|
|
|
||
|
|
/* Initialize all configured peripherals */
|
||
|
|
MX_GPIO_Init();
|
||
|
|
80005fc: f7ff ff92 bl 8000524 <MX_GPIO_Init>
|
||
|
|
MX_USART2_UART_Init();
|
||
|
|
8000600: f000 f8bc bl 800077c <MX_USART2_UART_Init>
|
||
|
|
/* USER CODE BEGIN 2 */
|
||
|
|
|
||
|
|
/* USER CODE END 2 */
|
||
|
|
|
||
|
|
/* Init scheduler */
|
||
|
|
osKernelInitialize(); /* Call init function for freertos objects (in freertos.c) */
|
||
|
|
8000604: f002 fc9e bl 8002f44 <osKernelInitialize>
|
||
|
|
MX_FREERTOS_Init();
|
||
|
|
8000608: f7ff ff72 bl 80004f0 <MX_FREERTOS_Init>
|
||
|
|
|
||
|
|
/* Start scheduler */
|
||
|
|
osKernelStart();
|
||
|
|
800060c: f002 fcc0 bl 8002f90 <osKernelStart>
|
||
|
|
|
||
|
|
/* We should never get here as control is now taken by the scheduler */
|
||
|
|
/* Infinite loop */
|
||
|
|
/* USER CODE BEGIN WHILE */
|
||
|
|
while (1)
|
||
|
|
8000610: e7fe b.n 8000610 <main+0x20>
|
||
|
|
|
||
|
|
08000612 <SystemClock_Config>:
|
||
|
|
/**
|
||
|
|
* @brief System Clock Configuration
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SystemClock_Config(void)
|
||
|
|
{
|
||
|
|
8000612: b580 push {r7, lr}
|
||
|
|
8000614: b096 sub sp, #88 ; 0x58
|
||
|
|
8000616: af00 add r7, sp, #0
|
||
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||
|
|
8000618: f107 0314 add.w r3, r7, #20
|
||
|
|
800061c: 2244 movs r2, #68 ; 0x44
|
||
|
|
800061e: 2100 movs r1, #0
|
||
|
|
8000620: 4618 mov r0, r3
|
||
|
|
8000622: f005 fa87 bl 8005b34 <memset>
|
||
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||
|
|
8000626: 463b mov r3, r7
|
||
|
|
8000628: 2200 movs r2, #0
|
||
|
|
800062a: 601a str r2, [r3, #0]
|
||
|
|
800062c: 605a str r2, [r3, #4]
|
||
|
|
800062e: 609a str r2, [r3, #8]
|
||
|
|
8000630: 60da str r2, [r3, #12]
|
||
|
|
8000632: 611a str r2, [r3, #16]
|
||
|
|
|
||
|
|
/** Configure the main internal regulator output voltage
|
||
|
|
*/
|
||
|
|
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
|
||
|
|
8000634: f44f 7000 mov.w r0, #512 ; 0x200
|
||
|
|
8000638: f000 fc88 bl 8000f4c <HAL_PWREx_ControlVoltageScaling>
|
||
|
|
800063c: 4603 mov r3, r0
|
||
|
|
800063e: 2b00 cmp r3, #0
|
||
|
|
8000640: d001 beq.n 8000646 <SystemClock_Config+0x34>
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
8000642: f000 f837 bl 80006b4 <Error_Handler>
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
||
|
|
* in the RCC_OscInitTypeDef structure.
|
||
|
|
*/
|
||
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
||
|
|
8000646: 2302 movs r3, #2
|
||
|
|
8000648: 617b str r3, [r7, #20]
|
||
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||
|
|
800064a: f44f 7380 mov.w r3, #256 ; 0x100
|
||
|
|
800064e: 623b str r3, [r7, #32]
|
||
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||
|
|
8000650: 2310 movs r3, #16
|
||
|
|
8000652: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||
|
|
8000654: 2302 movs r3, #2
|
||
|
|
8000656: 63fb str r3, [r7, #60] ; 0x3c
|
||
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
||
|
|
8000658: 2302 movs r3, #2
|
||
|
|
800065a: 643b str r3, [r7, #64] ; 0x40
|
||
|
|
RCC_OscInitStruct.PLL.PLLM = 1;
|
||
|
|
800065c: 2301 movs r3, #1
|
||
|
|
800065e: 647b str r3, [r7, #68] ; 0x44
|
||
|
|
RCC_OscInitStruct.PLL.PLLN = 10;
|
||
|
|
8000660: 230a movs r3, #10
|
||
|
|
8000662: 64bb str r3, [r7, #72] ; 0x48
|
||
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
|
||
|
|
8000664: 2307 movs r3, #7
|
||
|
|
8000666: 64fb str r3, [r7, #76] ; 0x4c
|
||
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
||
|
|
8000668: 2302 movs r3, #2
|
||
|
|
800066a: 653b str r3, [r7, #80] ; 0x50
|
||
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
||
|
|
800066c: 2302 movs r3, #2
|
||
|
|
800066e: 657b str r3, [r7, #84] ; 0x54
|
||
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||
|
|
8000670: f107 0314 add.w r3, r7, #20
|
||
|
|
8000674: 4618 mov r0, r3
|
||
|
|
8000676: f000 fcbf bl 8000ff8 <HAL_RCC_OscConfig>
|
||
|
|
800067a: 4603 mov r3, r0
|
||
|
|
800067c: 2b00 cmp r3, #0
|
||
|
|
800067e: d001 beq.n 8000684 <SystemClock_Config+0x72>
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
8000680: f000 f818 bl 80006b4 <Error_Handler>
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
||
|
|
*/
|
||
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||
|
|
8000684: 230f movs r3, #15
|
||
|
|
8000686: 603b str r3, [r7, #0]
|
||
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
||
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||
|
|
8000688: 2303 movs r3, #3
|
||
|
|
800068a: 607b str r3, [r7, #4]
|
||
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||
|
|
800068c: 2300 movs r3, #0
|
||
|
|
800068e: 60bb str r3, [r7, #8]
|
||
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
||
|
|
8000690: 2300 movs r3, #0
|
||
|
|
8000692: 60fb str r3, [r7, #12]
|
||
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||
|
|
8000694: 2300 movs r3, #0
|
||
|
|
8000696: 613b str r3, [r7, #16]
|
||
|
|
|
||
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||
|
|
8000698: 463b mov r3, r7
|
||
|
|
800069a: 2104 movs r1, #4
|
||
|
|
800069c: 4618 mov r0, r3
|
||
|
|
800069e: f001 f887 bl 80017b0 <HAL_RCC_ClockConfig>
|
||
|
|
80006a2: 4603 mov r3, r0
|
||
|
|
80006a4: 2b00 cmp r3, #0
|
||
|
|
80006a6: d001 beq.n 80006ac <SystemClock_Config+0x9a>
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
80006a8: f000 f804 bl 80006b4 <Error_Handler>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
80006ac: bf00 nop
|
||
|
|
80006ae: 3758 adds r7, #88 ; 0x58
|
||
|
|
80006b0: 46bd mov sp, r7
|
||
|
|
80006b2: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
080006b4 <Error_Handler>:
|
||
|
|
/**
|
||
|
|
* @brief This function is executed in case of error occurrence.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void Error_Handler(void)
|
||
|
|
{
|
||
|
|
80006b4: b480 push {r7}
|
||
|
|
80006b6: af00 add r7, sp, #0
|
||
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||
|
|
Can only be executed in Privileged modes.
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
||
|
|
{
|
||
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
||
|
|
80006b8: b672 cpsid i
|
||
|
|
}
|
||
|
|
80006ba: bf00 nop
|
||
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
||
|
|
/* User can add his own implementation to report the HAL error return state */
|
||
|
|
__disable_irq();
|
||
|
|
while (1)
|
||
|
|
80006bc: e7fe b.n 80006bc <Error_Handler+0x8>
|
||
|
|
...
|
||
|
|
|
||
|
|
080006c0 <HAL_MspInit>:
|
||
|
|
/* USER CODE END 0 */
|
||
|
|
/**
|
||
|
|
* Initializes the Global MSP.
|
||
|
|
*/
|
||
|
|
void HAL_MspInit(void)
|
||
|
|
{
|
||
|
|
80006c0: b580 push {r7, lr}
|
||
|
|
80006c2: b082 sub sp, #8
|
||
|
|
80006c4: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN MspInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END MspInit 0 */
|
||
|
|
|
||
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||
|
|
80006c6: 4b11 ldr r3, [pc, #68] ; (800070c <HAL_MspInit+0x4c>)
|
||
|
|
80006c8: 6e1b ldr r3, [r3, #96] ; 0x60
|
||
|
|
80006ca: 4a10 ldr r2, [pc, #64] ; (800070c <HAL_MspInit+0x4c>)
|
||
|
|
80006cc: f043 0301 orr.w r3, r3, #1
|
||
|
|
80006d0: 6613 str r3, [r2, #96] ; 0x60
|
||
|
|
80006d2: 4b0e ldr r3, [pc, #56] ; (800070c <HAL_MspInit+0x4c>)
|
||
|
|
80006d4: 6e1b ldr r3, [r3, #96] ; 0x60
|
||
|
|
80006d6: f003 0301 and.w r3, r3, #1
|
||
|
|
80006da: 607b str r3, [r7, #4]
|
||
|
|
80006dc: 687b ldr r3, [r7, #4]
|
||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||
|
|
80006de: 4b0b ldr r3, [pc, #44] ; (800070c <HAL_MspInit+0x4c>)
|
||
|
|
80006e0: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
80006e2: 4a0a ldr r2, [pc, #40] ; (800070c <HAL_MspInit+0x4c>)
|
||
|
|
80006e4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
80006e8: 6593 str r3, [r2, #88] ; 0x58
|
||
|
|
80006ea: 4b08 ldr r3, [pc, #32] ; (800070c <HAL_MspInit+0x4c>)
|
||
|
|
80006ec: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
80006ee: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
80006f2: 603b str r3, [r7, #0]
|
||
|
|
80006f4: 683b ldr r3, [r7, #0]
|
||
|
|
|
||
|
|
/* System interrupt init*/
|
||
|
|
/* PendSV_IRQn interrupt configuration */
|
||
|
|
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
|
||
|
|
80006f6: 2200 movs r2, #0
|
||
|
|
80006f8: 210f movs r1, #15
|
||
|
|
80006fa: f06f 0001 mvn.w r0, #1
|
||
|
|
80006fe: f000 fa2c bl 8000b5a <HAL_NVIC_SetPriority>
|
||
|
|
|
||
|
|
/* USER CODE BEGIN MspInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END MspInit 1 */
|
||
|
|
}
|
||
|
|
8000702: bf00 nop
|
||
|
|
8000704: 3708 adds r7, #8
|
||
|
|
8000706: 46bd mov sp, r7
|
||
|
|
8000708: bd80 pop {r7, pc}
|
||
|
|
800070a: bf00 nop
|
||
|
|
800070c: 40021000 .word 0x40021000
|
||
|
|
|
||
|
|
08000710 <NMI_Handler>:
|
||
|
|
/******************************************************************************/
|
||
|
|
/**
|
||
|
|
* @brief This function handles Non maskable interrupt.
|
||
|
|
*/
|
||
|
|
void NMI_Handler(void)
|
||
|
|
{
|
||
|
|
8000710: b480 push {r7}
|
||
|
|
8000712: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
||
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
||
|
|
while (1)
|
||
|
|
8000714: e7fe b.n 8000714 <NMI_Handler+0x4>
|
||
|
|
|
||
|
|
08000716 <HardFault_Handler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles Hard fault interrupt.
|
||
|
|
*/
|
||
|
|
void HardFault_Handler(void)
|
||
|
|
{
|
||
|
|
8000716: b480 push {r7}
|
||
|
|
8000718: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END HardFault_IRQn 0 */
|
||
|
|
while (1)
|
||
|
|
800071a: e7fe b.n 800071a <HardFault_Handler+0x4>
|
||
|
|
|
||
|
|
0800071c <MemManage_Handler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles Memory management fault.
|
||
|
|
*/
|
||
|
|
void MemManage_Handler(void)
|
||
|
|
{
|
||
|
|
800071c: b480 push {r7}
|
||
|
|
800071e: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
||
|
|
while (1)
|
||
|
|
8000720: e7fe b.n 8000720 <MemManage_Handler+0x4>
|
||
|
|
|
||
|
|
08000722 <BusFault_Handler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
||
|
|
*/
|
||
|
|
void BusFault_Handler(void)
|
||
|
|
{
|
||
|
|
8000722: b480 push {r7}
|
||
|
|
8000724: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END BusFault_IRQn 0 */
|
||
|
|
while (1)
|
||
|
|
8000726: e7fe b.n 8000726 <BusFault_Handler+0x4>
|
||
|
|
|
||
|
|
08000728 <UsageFault_Handler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles Undefined instruction or illegal state.
|
||
|
|
*/
|
||
|
|
void UsageFault_Handler(void)
|
||
|
|
{
|
||
|
|
8000728: b480 push {r7}
|
||
|
|
800072a: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
||
|
|
while (1)
|
||
|
|
800072c: e7fe b.n 800072c <UsageFault_Handler+0x4>
|
||
|
|
|
||
|
|
0800072e <DebugMon_Handler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles Debug monitor.
|
||
|
|
*/
|
||
|
|
void DebugMon_Handler(void)
|
||
|
|
{
|
||
|
|
800072e: b480 push {r7}
|
||
|
|
8000730: af00 add r7, sp, #0
|
||
|
|
|
||
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
||
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
||
|
|
|
||
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
||
|
|
}
|
||
|
|
8000732: bf00 nop
|
||
|
|
8000734: 46bd mov sp, r7
|
||
|
|
8000736: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
800073a: 4770 bx lr
|
||
|
|
|
||
|
|
0800073c <SysTick_Handler>:
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles System tick timer.
|
||
|
|
*/
|
||
|
|
void SysTick_Handler(void)
|
||
|
|
{
|
||
|
|
800073c: b580 push {r7, lr}
|
||
|
|
800073e: af00 add r7, sp, #0
|
||
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
||
|
|
|
||
|
|
/* USER CODE END SysTick_IRQn 0 */
|
||
|
|
HAL_IncTick();
|
||
|
|
8000740: f000 f92e bl 80009a0 <HAL_IncTick>
|
||
|
|
#if (INCLUDE_xTaskGetSchedulerState == 1 )
|
||
|
|
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
|
||
|
|
8000744: f004 f91e bl 8004984 <xTaskGetSchedulerState>
|
||
|
|
8000748: 4603 mov r3, r0
|
||
|
|
800074a: 2b01 cmp r3, #1
|
||
|
|
800074c: d001 beq.n 8000752 <SysTick_Handler+0x16>
|
||
|
|
{
|
||
|
|
#endif /* INCLUDE_xTaskGetSchedulerState */
|
||
|
|
xPortSysTickHandler();
|
||
|
|
800074e: f004 ff03 bl 8005558 <xPortSysTickHandler>
|
||
|
|
}
|
||
|
|
#endif /* INCLUDE_xTaskGetSchedulerState */
|
||
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
||
|
|
|
||
|
|
/* USER CODE END SysTick_IRQn 1 */
|
||
|
|
}
|
||
|
|
8000752: bf00 nop
|
||
|
|
8000754: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
08000758 <SystemInit>:
|
||
|
|
* @brief Setup the microcontroller system.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
|
||
|
|
void SystemInit(void)
|
||
|
|
{
|
||
|
|
8000758: b480 push {r7}
|
||
|
|
800075a: af00 add r7, sp, #0
|
||
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* FPU settings ------------------------------------------------------------*/
|
||
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||
|
|
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
||
|
|
800075c: 4b06 ldr r3, [pc, #24] ; (8000778 <SystemInit+0x20>)
|
||
|
|
800075e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8000762: 4a05 ldr r2, [pc, #20] ; (8000778 <SystemInit+0x20>)
|
||
|
|
8000764: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
|
||
|
|
8000768: f8c2 3088 str.w r3, [r2, #136] ; 0x88
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
800076c: bf00 nop
|
||
|
|
800076e: 46bd mov sp, r7
|
||
|
|
8000770: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8000774: 4770 bx lr
|
||
|
|
8000776: bf00 nop
|
||
|
|
8000778: e000ed00 .word 0xe000ed00
|
||
|
|
|
||
|
|
0800077c <MX_USART2_UART_Init>:
|
||
|
|
UART_HandleTypeDef huart2;
|
||
|
|
|
||
|
|
/* USART2 init function */
|
||
|
|
|
||
|
|
void MX_USART2_UART_Init(void)
|
||
|
|
{
|
||
|
|
800077c: b580 push {r7, lr}
|
||
|
|
800077e: af00 add r7, sp, #0
|
||
|
|
/* USER CODE END USART2_Init 0 */
|
||
|
|
|
||
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
||
|
|
|
||
|
|
/* USER CODE END USART2_Init 1 */
|
||
|
|
huart2.Instance = USART2;
|
||
|
|
8000780: 4b14 ldr r3, [pc, #80] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
8000782: 4a15 ldr r2, [pc, #84] ; (80007d8 <MX_USART2_UART_Init+0x5c>)
|
||
|
|
8000784: 601a str r2, [r3, #0]
|
||
|
|
huart2.Init.BaudRate = 115200;
|
||
|
|
8000786: 4b13 ldr r3, [pc, #76] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
8000788: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
||
|
|
800078c: 605a str r2, [r3, #4]
|
||
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
||
|
|
800078e: 4b11 ldr r3, [pc, #68] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
8000790: 2200 movs r2, #0
|
||
|
|
8000792: 609a str r2, [r3, #8]
|
||
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
||
|
|
8000794: 4b0f ldr r3, [pc, #60] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
8000796: 2200 movs r2, #0
|
||
|
|
8000798: 60da str r2, [r3, #12]
|
||
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
||
|
|
800079a: 4b0e ldr r3, [pc, #56] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
800079c: 2200 movs r2, #0
|
||
|
|
800079e: 611a str r2, [r3, #16]
|
||
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
||
|
|
80007a0: 4b0c ldr r3, [pc, #48] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
80007a2: 220c movs r2, #12
|
||
|
|
80007a4: 615a str r2, [r3, #20]
|
||
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||
|
|
80007a6: 4b0b ldr r3, [pc, #44] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
80007a8: 2200 movs r2, #0
|
||
|
|
80007aa: 619a str r2, [r3, #24]
|
||
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
||
|
|
80007ac: 4b09 ldr r3, [pc, #36] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
80007ae: 2200 movs r2, #0
|
||
|
|
80007b0: 61da str r2, [r3, #28]
|
||
|
|
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
||
|
|
80007b2: 4b08 ldr r3, [pc, #32] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
80007b4: 2200 movs r2, #0
|
||
|
|
80007b6: 621a str r2, [r3, #32]
|
||
|
|
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
||
|
|
80007b8: 4b06 ldr r3, [pc, #24] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
80007ba: 2200 movs r2, #0
|
||
|
|
80007bc: 625a str r2, [r3, #36] ; 0x24
|
||
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
||
|
|
80007be: 4805 ldr r0, [pc, #20] ; (80007d4 <MX_USART2_UART_Init+0x58>)
|
||
|
|
80007c0: f001 fed6 bl 8002570 <HAL_UART_Init>
|
||
|
|
80007c4: 4603 mov r3, r0
|
||
|
|
80007c6: 2b00 cmp r3, #0
|
||
|
|
80007c8: d001 beq.n 80007ce <MX_USART2_UART_Init+0x52>
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
80007ca: f7ff ff73 bl 80006b4 <Error_Handler>
|
||
|
|
}
|
||
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
||
|
|
|
||
|
|
/* USER CODE END USART2_Init 2 */
|
||
|
|
|
||
|
|
}
|
||
|
|
80007ce: bf00 nop
|
||
|
|
80007d0: bd80 pop {r7, pc}
|
||
|
|
80007d2: bf00 nop
|
||
|
|
80007d4: 200000a4 .word 0x200000a4
|
||
|
|
80007d8: 40004400 .word 0x40004400
|
||
|
|
|
||
|
|
080007dc <HAL_UART_MspInit>:
|
||
|
|
|
||
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
||
|
|
{
|
||
|
|
80007dc: b580 push {r7, lr}
|
||
|
|
80007de: b0ac sub sp, #176 ; 0xb0
|
||
|
|
80007e0: af00 add r7, sp, #0
|
||
|
|
80007e2: 6078 str r0, [r7, #4]
|
||
|
|
|
||
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||
|
|
80007e4: f107 039c add.w r3, r7, #156 ; 0x9c
|
||
|
|
80007e8: 2200 movs r2, #0
|
||
|
|
80007ea: 601a str r2, [r3, #0]
|
||
|
|
80007ec: 605a str r2, [r3, #4]
|
||
|
|
80007ee: 609a str r2, [r3, #8]
|
||
|
|
80007f0: 60da str r2, [r3, #12]
|
||
|
|
80007f2: 611a str r2, [r3, #16]
|
||
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
||
|
|
80007f4: f107 0314 add.w r3, r7, #20
|
||
|
|
80007f8: 2288 movs r2, #136 ; 0x88
|
||
|
|
80007fa: 2100 movs r1, #0
|
||
|
|
80007fc: 4618 mov r0, r3
|
||
|
|
80007fe: f005 f999 bl 8005b34 <memset>
|
||
|
|
if(uartHandle->Instance==USART2)
|
||
|
|
8000802: 687b ldr r3, [r7, #4]
|
||
|
|
8000804: 681b ldr r3, [r3, #0]
|
||
|
|
8000806: 4a21 ldr r2, [pc, #132] ; (800088c <HAL_UART_MspInit+0xb0>)
|
||
|
|
8000808: 4293 cmp r3, r2
|
||
|
|
800080a: d13b bne.n 8000884 <HAL_UART_MspInit+0xa8>
|
||
|
|
|
||
|
|
/* USER CODE END USART2_MspInit 0 */
|
||
|
|
|
||
|
|
/** Initializes the peripherals clock
|
||
|
|
*/
|
||
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
|
||
|
|
800080c: 2302 movs r3, #2
|
||
|
|
800080e: 617b str r3, [r7, #20]
|
||
|
|
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
|
||
|
|
8000810: 2300 movs r3, #0
|
||
|
|
8000812: 653b str r3, [r7, #80] ; 0x50
|
||
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
||
|
|
8000814: f107 0314 add.w r3, r7, #20
|
||
|
|
8000818: 4618 mov r0, r3
|
||
|
|
800081a: f001 f9ed bl 8001bf8 <HAL_RCCEx_PeriphCLKConfig>
|
||
|
|
800081e: 4603 mov r3, r0
|
||
|
|
8000820: 2b00 cmp r3, #0
|
||
|
|
8000822: d001 beq.n 8000828 <HAL_UART_MspInit+0x4c>
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
8000824: f7ff ff46 bl 80006b4 <Error_Handler>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* USART2 clock enable */
|
||
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
||
|
|
8000828: 4b19 ldr r3, [pc, #100] ; (8000890 <HAL_UART_MspInit+0xb4>)
|
||
|
|
800082a: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
800082c: 4a18 ldr r2, [pc, #96] ; (8000890 <HAL_UART_MspInit+0xb4>)
|
||
|
|
800082e: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
||
|
|
8000832: 6593 str r3, [r2, #88] ; 0x58
|
||
|
|
8000834: 4b16 ldr r3, [pc, #88] ; (8000890 <HAL_UART_MspInit+0xb4>)
|
||
|
|
8000836: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8000838: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
||
|
|
800083c: 613b str r3, [r7, #16]
|
||
|
|
800083e: 693b ldr r3, [r7, #16]
|
||
|
|
|
||
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||
|
|
8000840: 4b13 ldr r3, [pc, #76] ; (8000890 <HAL_UART_MspInit+0xb4>)
|
||
|
|
8000842: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8000844: 4a12 ldr r2, [pc, #72] ; (8000890 <HAL_UART_MspInit+0xb4>)
|
||
|
|
8000846: f043 0301 orr.w r3, r3, #1
|
||
|
|
800084a: 64d3 str r3, [r2, #76] ; 0x4c
|
||
|
|
800084c: 4b10 ldr r3, [pc, #64] ; (8000890 <HAL_UART_MspInit+0xb4>)
|
||
|
|
800084e: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8000850: f003 0301 and.w r3, r3, #1
|
||
|
|
8000854: 60fb str r3, [r7, #12]
|
||
|
|
8000856: 68fb ldr r3, [r7, #12]
|
||
|
|
/**USART2 GPIO Configuration
|
||
|
|
PA2 ------> USART2_TX
|
||
|
|
PA3 ------> USART2_RX
|
||
|
|
*/
|
||
|
|
GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
|
||
|
|
8000858: 230c movs r3, #12
|
||
|
|
800085a: f8c7 309c str.w r3, [r7, #156] ; 0x9c
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
|
|
800085e: 2302 movs r3, #2
|
||
|
|
8000860: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
8000864: 2300 movs r3, #0
|
||
|
|
8000866: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||
|
|
800086a: 2303 movs r3, #3
|
||
|
|
800086c: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
|
||
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
||
|
|
8000870: 2307 movs r3, #7
|
||
|
|
8000872: f8c7 30ac str.w r3, [r7, #172] ; 0xac
|
||
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||
|
|
8000876: f107 039c add.w r3, r7, #156 ; 0x9c
|
||
|
|
800087a: 4619 mov r1, r3
|
||
|
|
800087c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
||
|
|
8000880: f000 f994 bl 8000bac <HAL_GPIO_Init>
|
||
|
|
|
||
|
|
/* USER CODE BEGIN USART2_MspInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END USART2_MspInit 1 */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8000884: bf00 nop
|
||
|
|
8000886: 37b0 adds r7, #176 ; 0xb0
|
||
|
|
8000888: 46bd mov sp, r7
|
||
|
|
800088a: bd80 pop {r7, pc}
|
||
|
|
800088c: 40004400 .word 0x40004400
|
||
|
|
8000890: 40021000 .word 0x40021000
|
||
|
|
|
||
|
|
08000894 <Reset_Handler>:
|
||
|
|
|
||
|
|
.section .text.Reset_Handler
|
||
|
|
.weak Reset_Handler
|
||
|
|
.type Reset_Handler, %function
|
||
|
|
Reset_Handler:
|
||
|
|
ldr sp, =_estack /* Set stack pointer */
|
||
|
|
8000894: f8df d034 ldr.w sp, [pc, #52] ; 80008cc <LoopForever+0x2>
|
||
|
|
|
||
|
|
/* Call the clock system initialization function.*/
|
||
|
|
bl SystemInit
|
||
|
|
8000898: f7ff ff5e bl 8000758 <SystemInit>
|
||
|
|
|
||
|
|
/* Copy the data segment initializers from flash to SRAM */
|
||
|
|
ldr r0, =_sdata
|
||
|
|
800089c: 480c ldr r0, [pc, #48] ; (80008d0 <LoopForever+0x6>)
|
||
|
|
ldr r1, =_edata
|
||
|
|
800089e: 490d ldr r1, [pc, #52] ; (80008d4 <LoopForever+0xa>)
|
||
|
|
ldr r2, =_sidata
|
||
|
|
80008a0: 4a0d ldr r2, [pc, #52] ; (80008d8 <LoopForever+0xe>)
|
||
|
|
movs r3, #0
|
||
|
|
80008a2: 2300 movs r3, #0
|
||
|
|
b LoopCopyDataInit
|
||
|
|
80008a4: e002 b.n 80008ac <LoopCopyDataInit>
|
||
|
|
|
||
|
|
080008a6 <CopyDataInit>:
|
||
|
|
|
||
|
|
CopyDataInit:
|
||
|
|
ldr r4, [r2, r3]
|
||
|
|
80008a6: 58d4 ldr r4, [r2, r3]
|
||
|
|
str r4, [r0, r3]
|
||
|
|
80008a8: 50c4 str r4, [r0, r3]
|
||
|
|
adds r3, r3, #4
|
||
|
|
80008aa: 3304 adds r3, #4
|
||
|
|
|
||
|
|
080008ac <LoopCopyDataInit>:
|
||
|
|
|
||
|
|
LoopCopyDataInit:
|
||
|
|
adds r4, r0, r3
|
||
|
|
80008ac: 18c4 adds r4, r0, r3
|
||
|
|
cmp r4, r1
|
||
|
|
80008ae: 428c cmp r4, r1
|
||
|
|
bcc CopyDataInit
|
||
|
|
80008b0: d3f9 bcc.n 80008a6 <CopyDataInit>
|
||
|
|
|
||
|
|
/* Zero fill the bss segment. */
|
||
|
|
ldr r2, =_sbss
|
||
|
|
80008b2: 4a0a ldr r2, [pc, #40] ; (80008dc <LoopForever+0x12>)
|
||
|
|
ldr r4, =_ebss
|
||
|
|
80008b4: 4c0a ldr r4, [pc, #40] ; (80008e0 <LoopForever+0x16>)
|
||
|
|
movs r3, #0
|
||
|
|
80008b6: 2300 movs r3, #0
|
||
|
|
b LoopFillZerobss
|
||
|
|
80008b8: e001 b.n 80008be <LoopFillZerobss>
|
||
|
|
|
||
|
|
080008ba <FillZerobss>:
|
||
|
|
|
||
|
|
FillZerobss:
|
||
|
|
str r3, [r2]
|
||
|
|
80008ba: 6013 str r3, [r2, #0]
|
||
|
|
adds r2, r2, #4
|
||
|
|
80008bc: 3204 adds r2, #4
|
||
|
|
|
||
|
|
080008be <LoopFillZerobss>:
|
||
|
|
|
||
|
|
LoopFillZerobss:
|
||
|
|
cmp r2, r4
|
||
|
|
80008be: 42a2 cmp r2, r4
|
||
|
|
bcc FillZerobss
|
||
|
|
80008c0: d3fb bcc.n 80008ba <FillZerobss>
|
||
|
|
|
||
|
|
/* Call static constructors */
|
||
|
|
bl __libc_init_array
|
||
|
|
80008c2: f005 f903 bl 8005acc <__libc_init_array>
|
||
|
|
/* Call the application's entry point.*/
|
||
|
|
bl main
|
||
|
|
80008c6: f7ff fe93 bl 80005f0 <main>
|
||
|
|
|
||
|
|
080008ca <LoopForever>:
|
||
|
|
|
||
|
|
LoopForever:
|
||
|
|
b LoopForever
|
||
|
|
80008ca: e7fe b.n 80008ca <LoopForever>
|
||
|
|
ldr sp, =_estack /* Set stack pointer */
|
||
|
|
80008cc: 20018000 .word 0x20018000
|
||
|
|
ldr r0, =_sdata
|
||
|
|
80008d0: 20000000 .word 0x20000000
|
||
|
|
ldr r1, =_edata
|
||
|
|
80008d4: 20000084 .word 0x20000084
|
||
|
|
ldr r2, =_sidata
|
||
|
|
80008d8: 08005de0 .word 0x08005de0
|
||
|
|
ldr r2, =_sbss
|
||
|
|
80008dc: 20000084 .word 0x20000084
|
||
|
|
ldr r4, =_ebss
|
||
|
|
80008e0: 20003e24 .word 0x20003e24
|
||
|
|
|
||
|
|
080008e4 <ADC1_2_IRQHandler>:
|
||
|
|
* @retval : None
|
||
|
|
*/
|
||
|
|
.section .text.Default_Handler,"ax",%progbits
|
||
|
|
Default_Handler:
|
||
|
|
Infinite_Loop:
|
||
|
|
b Infinite_Loop
|
||
|
|
80008e4: e7fe b.n 80008e4 <ADC1_2_IRQHandler>
|
||
|
|
...
|
||
|
|
|
||
|
|
080008e8 <HAL_Init>:
|
||
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
||
|
|
*
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_Init(void)
|
||
|
|
{
|
||
|
|
80008e8: b580 push {r7, lr}
|
||
|
|
80008ea: b082 sub sp, #8
|
||
|
|
80008ec: af00 add r7, sp, #0
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
80008ee: 2300 movs r3, #0
|
||
|
|
80008f0: 71fb strb r3, [r7, #7]
|
||
|
|
#if (DATA_CACHE_ENABLE == 0)
|
||
|
|
__HAL_FLASH_DATA_CACHE_DISABLE();
|
||
|
|
#endif /* DATA_CACHE_ENABLE */
|
||
|
|
|
||
|
|
#if (PREFETCH_ENABLE != 0)
|
||
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
||
|
|
80008f2: 4b0c ldr r3, [pc, #48] ; (8000924 <HAL_Init+0x3c>)
|
||
|
|
80008f4: 681b ldr r3, [r3, #0]
|
||
|
|
80008f6: 4a0b ldr r2, [pc, #44] ; (8000924 <HAL_Init+0x3c>)
|
||
|
|
80008f8: f443 7380 orr.w r3, r3, #256 ; 0x100
|
||
|
|
80008fc: 6013 str r3, [r2, #0]
|
||
|
|
#endif /* PREFETCH_ENABLE */
|
||
|
|
|
||
|
|
/* Set Interrupt Group Priority */
|
||
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||
|
|
80008fe: 2003 movs r0, #3
|
||
|
|
8000900: f000 f920 bl 8000b44 <HAL_NVIC_SetPriorityGrouping>
|
||
|
|
|
||
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
||
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
||
|
|
8000904: 200f movs r0, #15
|
||
|
|
8000906: f000 f80f bl 8000928 <HAL_InitTick>
|
||
|
|
800090a: 4603 mov r3, r0
|
||
|
|
800090c: 2b00 cmp r3, #0
|
||
|
|
800090e: d002 beq.n 8000916 <HAL_Init+0x2e>
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
8000910: 2301 movs r3, #1
|
||
|
|
8000912: 71fb strb r3, [r7, #7]
|
||
|
|
8000914: e001 b.n 800091a <HAL_Init+0x32>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Init the low level hardware */
|
||
|
|
HAL_MspInit();
|
||
|
|
8000916: f7ff fed3 bl 80006c0 <HAL_MspInit>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Return function status */
|
||
|
|
return status;
|
||
|
|
800091a: 79fb ldrb r3, [r7, #7]
|
||
|
|
}
|
||
|
|
800091c: 4618 mov r0, r3
|
||
|
|
800091e: 3708 adds r7, #8
|
||
|
|
8000920: 46bd mov sp, r7
|
||
|
|
8000922: bd80 pop {r7, pc}
|
||
|
|
8000924: 40022000 .word 0x40022000
|
||
|
|
|
||
|
|
08000928 <HAL_InitTick>:
|
||
|
|
* implementation in user file.
|
||
|
|
* @param TickPriority Tick interrupt priority.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||
|
|
{
|
||
|
|
8000928: b580 push {r7, lr}
|
||
|
|
800092a: b084 sub sp, #16
|
||
|
|
800092c: af00 add r7, sp, #0
|
||
|
|
800092e: 6078 str r0, [r7, #4]
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
8000930: 2300 movs r3, #0
|
||
|
|
8000932: 73fb strb r3, [r7, #15]
|
||
|
|
|
||
|
|
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
|
||
|
|
if ((uint32_t)uwTickFreq != 0U)
|
||
|
|
8000934: 4b17 ldr r3, [pc, #92] ; (8000994 <HAL_InitTick+0x6c>)
|
||
|
|
8000936: 781b ldrb r3, [r3, #0]
|
||
|
|
8000938: 2b00 cmp r3, #0
|
||
|
|
800093a: d023 beq.n 8000984 <HAL_InitTick+0x5c>
|
||
|
|
{
|
||
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
||
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
|
||
|
|
800093c: 4b16 ldr r3, [pc, #88] ; (8000998 <HAL_InitTick+0x70>)
|
||
|
|
800093e: 681a ldr r2, [r3, #0]
|
||
|
|
8000940: 4b14 ldr r3, [pc, #80] ; (8000994 <HAL_InitTick+0x6c>)
|
||
|
|
8000942: 781b ldrb r3, [r3, #0]
|
||
|
|
8000944: 4619 mov r1, r3
|
||
|
|
8000946: f44f 737a mov.w r3, #1000 ; 0x3e8
|
||
|
|
800094a: fbb3 f3f1 udiv r3, r3, r1
|
||
|
|
800094e: fbb2 f3f3 udiv r3, r2, r3
|
||
|
|
8000952: 4618 mov r0, r3
|
||
|
|
8000954: f000 f91d bl 8000b92 <HAL_SYSTICK_Config>
|
||
|
|
8000958: 4603 mov r3, r0
|
||
|
|
800095a: 2b00 cmp r3, #0
|
||
|
|
800095c: d10f bne.n 800097e <HAL_InitTick+0x56>
|
||
|
|
{
|
||
|
|
/* Configure the SysTick IRQ priority */
|
||
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||
|
|
800095e: 687b ldr r3, [r7, #4]
|
||
|
|
8000960: 2b0f cmp r3, #15
|
||
|
|
8000962: d809 bhi.n 8000978 <HAL_InitTick+0x50>
|
||
|
|
{
|
||
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
||
|
|
8000964: 2200 movs r2, #0
|
||
|
|
8000966: 6879 ldr r1, [r7, #4]
|
||
|
|
8000968: f04f 30ff mov.w r0, #4294967295
|
||
|
|
800096c: f000 f8f5 bl 8000b5a <HAL_NVIC_SetPriority>
|
||
|
|
uwTickPrio = TickPriority;
|
||
|
|
8000970: 4a0a ldr r2, [pc, #40] ; (800099c <HAL_InitTick+0x74>)
|
||
|
|
8000972: 687b ldr r3, [r7, #4]
|
||
|
|
8000974: 6013 str r3, [r2, #0]
|
||
|
|
8000976: e007 b.n 8000988 <HAL_InitTick+0x60>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
8000978: 2301 movs r3, #1
|
||
|
|
800097a: 73fb strb r3, [r7, #15]
|
||
|
|
800097c: e004 b.n 8000988 <HAL_InitTick+0x60>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
800097e: 2301 movs r3, #1
|
||
|
|
8000980: 73fb strb r3, [r7, #15]
|
||
|
|
8000982: e001 b.n 8000988 <HAL_InitTick+0x60>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
8000984: 2301 movs r3, #1
|
||
|
|
8000986: 73fb strb r3, [r7, #15]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Return function status */
|
||
|
|
return status;
|
||
|
|
8000988: 7bfb ldrb r3, [r7, #15]
|
||
|
|
}
|
||
|
|
800098a: 4618 mov r0, r3
|
||
|
|
800098c: 3710 adds r7, #16
|
||
|
|
800098e: 46bd mov sp, r7
|
||
|
|
8000990: bd80 pop {r7, pc}
|
||
|
|
8000992: bf00 nop
|
||
|
|
8000994: 20000008 .word 0x20000008
|
||
|
|
8000998: 20000000 .word 0x20000000
|
||
|
|
800099c: 20000004 .word 0x20000004
|
||
|
|
|
||
|
|
080009a0 <HAL_IncTick>:
|
||
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
||
|
|
* implementations in user file.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
__weak void HAL_IncTick(void)
|
||
|
|
{
|
||
|
|
80009a0: b480 push {r7}
|
||
|
|
80009a2: af00 add r7, sp, #0
|
||
|
|
uwTick += (uint32_t)uwTickFreq;
|
||
|
|
80009a4: 4b06 ldr r3, [pc, #24] ; (80009c0 <HAL_IncTick+0x20>)
|
||
|
|
80009a6: 781b ldrb r3, [r3, #0]
|
||
|
|
80009a8: 461a mov r2, r3
|
||
|
|
80009aa: 4b06 ldr r3, [pc, #24] ; (80009c4 <HAL_IncTick+0x24>)
|
||
|
|
80009ac: 681b ldr r3, [r3, #0]
|
||
|
|
80009ae: 4413 add r3, r2
|
||
|
|
80009b0: 4a04 ldr r2, [pc, #16] ; (80009c4 <HAL_IncTick+0x24>)
|
||
|
|
80009b2: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
80009b4: bf00 nop
|
||
|
|
80009b6: 46bd mov sp, r7
|
||
|
|
80009b8: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80009bc: 4770 bx lr
|
||
|
|
80009be: bf00 nop
|
||
|
|
80009c0: 20000008 .word 0x20000008
|
||
|
|
80009c4: 20000128 .word 0x20000128
|
||
|
|
|
||
|
|
080009c8 <HAL_GetTick>:
|
||
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
||
|
|
* implementations in user file.
|
||
|
|
* @retval tick value
|
||
|
|
*/
|
||
|
|
__weak uint32_t HAL_GetTick(void)
|
||
|
|
{
|
||
|
|
80009c8: b480 push {r7}
|
||
|
|
80009ca: af00 add r7, sp, #0
|
||
|
|
return uwTick;
|
||
|
|
80009cc: 4b03 ldr r3, [pc, #12] ; (80009dc <HAL_GetTick+0x14>)
|
||
|
|
80009ce: 681b ldr r3, [r3, #0]
|
||
|
|
}
|
||
|
|
80009d0: 4618 mov r0, r3
|
||
|
|
80009d2: 46bd mov sp, r7
|
||
|
|
80009d4: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80009d8: 4770 bx lr
|
||
|
|
80009da: bf00 nop
|
||
|
|
80009dc: 20000128 .word 0x20000128
|
||
|
|
|
||
|
|
080009e0 <__NVIC_SetPriorityGrouping>:
|
||
|
|
In case of a conflict between priority grouping and available
|
||
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||
|
|
\param [in] PriorityGroup Priority grouping field.
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||
|
|
{
|
||
|
|
80009e0: b480 push {r7}
|
||
|
|
80009e2: b085 sub sp, #20
|
||
|
|
80009e4: af00 add r7, sp, #0
|
||
|
|
80009e6: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t reg_value;
|
||
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||
|
|
80009e8: 687b ldr r3, [r7, #4]
|
||
|
|
80009ea: f003 0307 and.w r3, r3, #7
|
||
|
|
80009ee: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
||
|
|
80009f0: 4b0c ldr r3, [pc, #48] ; (8000a24 <__NVIC_SetPriorityGrouping+0x44>)
|
||
|
|
80009f2: 68db ldr r3, [r3, #12]
|
||
|
|
80009f4: 60bb str r3, [r7, #8]
|
||
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||
|
|
80009f6: 68ba ldr r2, [r7, #8]
|
||
|
|
80009f8: f64f 03ff movw r3, #63743 ; 0xf8ff
|
||
|
|
80009fc: 4013 ands r3, r2
|
||
|
|
80009fe: 60bb str r3, [r7, #8]
|
||
|
|
reg_value = (reg_value |
|
||
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
||
|
|
8000a00: 68fb ldr r3, [r7, #12]
|
||
|
|
8000a02: 021a lsls r2, r3, #8
|
||
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||
|
|
8000a04: 68bb ldr r3, [r7, #8]
|
||
|
|
8000a06: 4313 orrs r3, r2
|
||
|
|
reg_value = (reg_value |
|
||
|
|
8000a08: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
|
||
|
|
8000a0c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
||
|
|
8000a10: 60bb str r3, [r7, #8]
|
||
|
|
SCB->AIRCR = reg_value;
|
||
|
|
8000a12: 4a04 ldr r2, [pc, #16] ; (8000a24 <__NVIC_SetPriorityGrouping+0x44>)
|
||
|
|
8000a14: 68bb ldr r3, [r7, #8]
|
||
|
|
8000a16: 60d3 str r3, [r2, #12]
|
||
|
|
}
|
||
|
|
8000a18: bf00 nop
|
||
|
|
8000a1a: 3714 adds r7, #20
|
||
|
|
8000a1c: 46bd mov sp, r7
|
||
|
|
8000a1e: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8000a22: 4770 bx lr
|
||
|
|
8000a24: e000ed00 .word 0xe000ed00
|
||
|
|
|
||
|
|
08000a28 <__NVIC_GetPriorityGrouping>:
|
||
|
|
\brief Get Priority Grouping
|
||
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
||
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
||
|
|
{
|
||
|
|
8000a28: b480 push {r7}
|
||
|
|
8000a2a: af00 add r7, sp, #0
|
||
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
||
|
|
8000a2c: 4b04 ldr r3, [pc, #16] ; (8000a40 <__NVIC_GetPriorityGrouping+0x18>)
|
||
|
|
8000a2e: 68db ldr r3, [r3, #12]
|
||
|
|
8000a30: 0a1b lsrs r3, r3, #8
|
||
|
|
8000a32: f003 0307 and.w r3, r3, #7
|
||
|
|
}
|
||
|
|
8000a36: 4618 mov r0, r3
|
||
|
|
8000a38: 46bd mov sp, r7
|
||
|
|
8000a3a: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8000a3e: 4770 bx lr
|
||
|
|
8000a40: e000ed00 .word 0xe000ed00
|
||
|
|
|
||
|
|
08000a44 <__NVIC_SetPriority>:
|
||
|
|
\param [in] IRQn Interrupt number.
|
||
|
|
\param [in] priority Priority to set.
|
||
|
|
\note The priority cannot be set for every processor exception.
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||
|
|
{
|
||
|
|
8000a44: b480 push {r7}
|
||
|
|
8000a46: b083 sub sp, #12
|
||
|
|
8000a48: af00 add r7, sp, #0
|
||
|
|
8000a4a: 4603 mov r3, r0
|
||
|
|
8000a4c: 6039 str r1, [r7, #0]
|
||
|
|
8000a4e: 71fb strb r3, [r7, #7]
|
||
|
|
if ((int32_t)(IRQn) >= 0)
|
||
|
|
8000a50: f997 3007 ldrsb.w r3, [r7, #7]
|
||
|
|
8000a54: 2b00 cmp r3, #0
|
||
|
|
8000a56: db0a blt.n 8000a6e <__NVIC_SetPriority+0x2a>
|
||
|
|
{
|
||
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||
|
|
8000a58: 683b ldr r3, [r7, #0]
|
||
|
|
8000a5a: b2da uxtb r2, r3
|
||
|
|
8000a5c: 490c ldr r1, [pc, #48] ; (8000a90 <__NVIC_SetPriority+0x4c>)
|
||
|
|
8000a5e: f997 3007 ldrsb.w r3, [r7, #7]
|
||
|
|
8000a62: 0112 lsls r2, r2, #4
|
||
|
|
8000a64: b2d2 uxtb r2, r2
|
||
|
|
8000a66: 440b add r3, r1
|
||
|
|
8000a68: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8000a6c: e00a b.n 8000a84 <__NVIC_SetPriority+0x40>
|
||
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||
|
|
8000a6e: 683b ldr r3, [r7, #0]
|
||
|
|
8000a70: b2da uxtb r2, r3
|
||
|
|
8000a72: 4908 ldr r1, [pc, #32] ; (8000a94 <__NVIC_SetPriority+0x50>)
|
||
|
|
8000a74: 79fb ldrb r3, [r7, #7]
|
||
|
|
8000a76: f003 030f and.w r3, r3, #15
|
||
|
|
8000a7a: 3b04 subs r3, #4
|
||
|
|
8000a7c: 0112 lsls r2, r2, #4
|
||
|
|
8000a7e: b2d2 uxtb r2, r2
|
||
|
|
8000a80: 440b add r3, r1
|
||
|
|
8000a82: 761a strb r2, [r3, #24]
|
||
|
|
}
|
||
|
|
8000a84: bf00 nop
|
||
|
|
8000a86: 370c adds r7, #12
|
||
|
|
8000a88: 46bd mov sp, r7
|
||
|
|
8000a8a: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8000a8e: 4770 bx lr
|
||
|
|
8000a90: e000e100 .word 0xe000e100
|
||
|
|
8000a94: e000ed00 .word 0xe000ed00
|
||
|
|
|
||
|
|
08000a98 <NVIC_EncodePriority>:
|
||
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||
|
|
{
|
||
|
|
8000a98: b480 push {r7}
|
||
|
|
8000a9a: b089 sub sp, #36 ; 0x24
|
||
|
|
8000a9c: af00 add r7, sp, #0
|
||
|
|
8000a9e: 60f8 str r0, [r7, #12]
|
||
|
|
8000aa0: 60b9 str r1, [r7, #8]
|
||
|
|
8000aa2: 607a str r2, [r7, #4]
|
||
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||
|
|
8000aa4: 68fb ldr r3, [r7, #12]
|
||
|
|
8000aa6: f003 0307 and.w r3, r3, #7
|
||
|
|
8000aaa: 61fb str r3, [r7, #28]
|
||
|
|
uint32_t PreemptPriorityBits;
|
||
|
|
uint32_t SubPriorityBits;
|
||
|
|
|
||
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||
|
|
8000aac: 69fb ldr r3, [r7, #28]
|
||
|
|
8000aae: f1c3 0307 rsb r3, r3, #7
|
||
|
|
8000ab2: 2b04 cmp r3, #4
|
||
|
|
8000ab4: bf28 it cs
|
||
|
|
8000ab6: 2304 movcs r3, #4
|
||
|
|
8000ab8: 61bb str r3, [r7, #24]
|
||
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||
|
|
8000aba: 69fb ldr r3, [r7, #28]
|
||
|
|
8000abc: 3304 adds r3, #4
|
||
|
|
8000abe: 2b06 cmp r3, #6
|
||
|
|
8000ac0: d902 bls.n 8000ac8 <NVIC_EncodePriority+0x30>
|
||
|
|
8000ac2: 69fb ldr r3, [r7, #28]
|
||
|
|
8000ac4: 3b03 subs r3, #3
|
||
|
|
8000ac6: e000 b.n 8000aca <NVIC_EncodePriority+0x32>
|
||
|
|
8000ac8: 2300 movs r3, #0
|
||
|
|
8000aca: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
return (
|
||
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||
|
|
8000acc: f04f 32ff mov.w r2, #4294967295
|
||
|
|
8000ad0: 69bb ldr r3, [r7, #24]
|
||
|
|
8000ad2: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000ad6: 43da mvns r2, r3
|
||
|
|
8000ad8: 68bb ldr r3, [r7, #8]
|
||
|
|
8000ada: 401a ands r2, r3
|
||
|
|
8000adc: 697b ldr r3, [r7, #20]
|
||
|
|
8000ade: 409a lsls r2, r3
|
||
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||
|
|
8000ae0: f04f 31ff mov.w r1, #4294967295
|
||
|
|
8000ae4: 697b ldr r3, [r7, #20]
|
||
|
|
8000ae6: fa01 f303 lsl.w r3, r1, r3
|
||
|
|
8000aea: 43d9 mvns r1, r3
|
||
|
|
8000aec: 687b ldr r3, [r7, #4]
|
||
|
|
8000aee: 400b ands r3, r1
|
||
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||
|
|
8000af0: 4313 orrs r3, r2
|
||
|
|
);
|
||
|
|
}
|
||
|
|
8000af2: 4618 mov r0, r3
|
||
|
|
8000af4: 3724 adds r7, #36 ; 0x24
|
||
|
|
8000af6: 46bd mov sp, r7
|
||
|
|
8000af8: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8000afc: 4770 bx lr
|
||
|
|
...
|
||
|
|
|
||
|
|
08000b00 <SysTick_Config>:
|
||
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||
|
|
must contain a vendor-specific implementation of this function.
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||
|
|
{
|
||
|
|
8000b00: b580 push {r7, lr}
|
||
|
|
8000b02: b082 sub sp, #8
|
||
|
|
8000b04: af00 add r7, sp, #0
|
||
|
|
8000b06: 6078 str r0, [r7, #4]
|
||
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||
|
|
8000b08: 687b ldr r3, [r7, #4]
|
||
|
|
8000b0a: 3b01 subs r3, #1
|
||
|
|
8000b0c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
||
|
|
8000b10: d301 bcc.n 8000b16 <SysTick_Config+0x16>
|
||
|
|
{
|
||
|
|
return (1UL); /* Reload value impossible */
|
||
|
|
8000b12: 2301 movs r3, #1
|
||
|
|
8000b14: e00f b.n 8000b36 <SysTick_Config+0x36>
|
||
|
|
}
|
||
|
|
|
||
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||
|
|
8000b16: 4a0a ldr r2, [pc, #40] ; (8000b40 <SysTick_Config+0x40>)
|
||
|
|
8000b18: 687b ldr r3, [r7, #4]
|
||
|
|
8000b1a: 3b01 subs r3, #1
|
||
|
|
8000b1c: 6053 str r3, [r2, #4]
|
||
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||
|
|
8000b1e: 210f movs r1, #15
|
||
|
|
8000b20: f04f 30ff mov.w r0, #4294967295
|
||
|
|
8000b24: f7ff ff8e bl 8000a44 <__NVIC_SetPriority>
|
||
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||
|
|
8000b28: 4b05 ldr r3, [pc, #20] ; (8000b40 <SysTick_Config+0x40>)
|
||
|
|
8000b2a: 2200 movs r2, #0
|
||
|
|
8000b2c: 609a str r2, [r3, #8]
|
||
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||
|
|
8000b2e: 4b04 ldr r3, [pc, #16] ; (8000b40 <SysTick_Config+0x40>)
|
||
|
|
8000b30: 2207 movs r2, #7
|
||
|
|
8000b32: 601a str r2, [r3, #0]
|
||
|
|
SysTick_CTRL_TICKINT_Msk |
|
||
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||
|
|
return (0UL); /* Function successful */
|
||
|
|
8000b34: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8000b36: 4618 mov r0, r3
|
||
|
|
8000b38: 3708 adds r7, #8
|
||
|
|
8000b3a: 46bd mov sp, r7
|
||
|
|
8000b3c: bd80 pop {r7, pc}
|
||
|
|
8000b3e: bf00 nop
|
||
|
|
8000b40: e000e010 .word 0xe000e010
|
||
|
|
|
||
|
|
08000b44 <HAL_NVIC_SetPriorityGrouping>:
|
||
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||
|
|
{
|
||
|
|
8000b44: b580 push {r7, lr}
|
||
|
|
8000b46: b082 sub sp, #8
|
||
|
|
8000b48: af00 add r7, sp, #0
|
||
|
|
8000b4a: 6078 str r0, [r7, #4]
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||
|
|
|
||
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
||
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
||
|
|
8000b4c: 6878 ldr r0, [r7, #4]
|
||
|
|
8000b4e: f7ff ff47 bl 80009e0 <__NVIC_SetPriorityGrouping>
|
||
|
|
}
|
||
|
|
8000b52: bf00 nop
|
||
|
|
8000b54: 3708 adds r7, #8
|
||
|
|
8000b56: 46bd mov sp, r7
|
||
|
|
8000b58: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08000b5a <HAL_NVIC_SetPriority>:
|
||
|
|
* This parameter can be a value between 0 and 15
|
||
|
|
* A lower priority value indicates a higher priority.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||
|
|
{
|
||
|
|
8000b5a: b580 push {r7, lr}
|
||
|
|
8000b5c: b086 sub sp, #24
|
||
|
|
8000b5e: af00 add r7, sp, #0
|
||
|
|
8000b60: 4603 mov r3, r0
|
||
|
|
8000b62: 60b9 str r1, [r7, #8]
|
||
|
|
8000b64: 607a str r2, [r7, #4]
|
||
|
|
8000b66: 73fb strb r3, [r7, #15]
|
||
|
|
uint32_t prioritygroup = 0x00;
|
||
|
|
8000b68: 2300 movs r3, #0
|
||
|
|
8000b6a: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
||
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||
|
|
|
||
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
||
|
|
8000b6c: f7ff ff5c bl 8000a28 <__NVIC_GetPriorityGrouping>
|
||
|
|
8000b70: 6178 str r0, [r7, #20]
|
||
|
|
|
||
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
||
|
|
8000b72: 687a ldr r2, [r7, #4]
|
||
|
|
8000b74: 68b9 ldr r1, [r7, #8]
|
||
|
|
8000b76: 6978 ldr r0, [r7, #20]
|
||
|
|
8000b78: f7ff ff8e bl 8000a98 <NVIC_EncodePriority>
|
||
|
|
8000b7c: 4602 mov r2, r0
|
||
|
|
8000b7e: f997 300f ldrsb.w r3, [r7, #15]
|
||
|
|
8000b82: 4611 mov r1, r2
|
||
|
|
8000b84: 4618 mov r0, r3
|
||
|
|
8000b86: f7ff ff5d bl 8000a44 <__NVIC_SetPriority>
|
||
|
|
}
|
||
|
|
8000b8a: bf00 nop
|
||
|
|
8000b8c: 3718 adds r7, #24
|
||
|
|
8000b8e: 46bd mov sp, r7
|
||
|
|
8000b90: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08000b92 <HAL_SYSTICK_Config>:
|
||
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
||
|
|
* @retval status: - 0 Function succeeded.
|
||
|
|
* - 1 Function failed.
|
||
|
|
*/
|
||
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||
|
|
{
|
||
|
|
8000b92: b580 push {r7, lr}
|
||
|
|
8000b94: b082 sub sp, #8
|
||
|
|
8000b96: af00 add r7, sp, #0
|
||
|
|
8000b98: 6078 str r0, [r7, #4]
|
||
|
|
return SysTick_Config(TicksNumb);
|
||
|
|
8000b9a: 6878 ldr r0, [r7, #4]
|
||
|
|
8000b9c: f7ff ffb0 bl 8000b00 <SysTick_Config>
|
||
|
|
8000ba0: 4603 mov r3, r0
|
||
|
|
}
|
||
|
|
8000ba2: 4618 mov r0, r3
|
||
|
|
8000ba4: 3708 adds r7, #8
|
||
|
|
8000ba6: 46bd mov sp, r7
|
||
|
|
8000ba8: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
08000bac <HAL_GPIO_Init>:
|
||
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
||
|
|
* the configuration information for the specified GPIO peripheral.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||
|
|
{
|
||
|
|
8000bac: b480 push {r7}
|
||
|
|
8000bae: b087 sub sp, #28
|
||
|
|
8000bb0: af00 add r7, sp, #0
|
||
|
|
8000bb2: 6078 str r0, [r7, #4]
|
||
|
|
8000bb4: 6039 str r1, [r7, #0]
|
||
|
|
uint32_t position = 0x00u;
|
||
|
|
8000bb6: 2300 movs r3, #0
|
||
|
|
8000bb8: 617b str r3, [r7, #20]
|
||
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||
|
|
|
||
|
|
/* Configure the port pins */
|
||
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
||
|
|
8000bba: e17f b.n 8000ebc <HAL_GPIO_Init+0x310>
|
||
|
|
{
|
||
|
|
/* Get current io position */
|
||
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
||
|
|
8000bbc: 683b ldr r3, [r7, #0]
|
||
|
|
8000bbe: 681a ldr r2, [r3, #0]
|
||
|
|
8000bc0: 2101 movs r1, #1
|
||
|
|
8000bc2: 697b ldr r3, [r7, #20]
|
||
|
|
8000bc4: fa01 f303 lsl.w r3, r1, r3
|
||
|
|
8000bc8: 4013 ands r3, r2
|
||
|
|
8000bca: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
if (iocurrent != 0x00u)
|
||
|
|
8000bcc: 68fb ldr r3, [r7, #12]
|
||
|
|
8000bce: 2b00 cmp r3, #0
|
||
|
|
8000bd0: f000 8171 beq.w 8000eb6 <HAL_GPIO_Init+0x30a>
|
||
|
|
{
|
||
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||
|
|
/* In case of Output or Alternate function mode selection */
|
||
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
||
|
|
8000bd4: 683b ldr r3, [r7, #0]
|
||
|
|
8000bd6: 685b ldr r3, [r3, #4]
|
||
|
|
8000bd8: f003 0303 and.w r3, r3, #3
|
||
|
|
8000bdc: 2b01 cmp r3, #1
|
||
|
|
8000bde: d005 beq.n 8000bec <HAL_GPIO_Init+0x40>
|
||
|
|
8000be0: 683b ldr r3, [r7, #0]
|
||
|
|
8000be2: 685b ldr r3, [r3, #4]
|
||
|
|
8000be4: f003 0303 and.w r3, r3, #3
|
||
|
|
8000be8: 2b02 cmp r3, #2
|
||
|
|
8000bea: d130 bne.n 8000c4e <HAL_GPIO_Init+0xa2>
|
||
|
|
{
|
||
|
|
/* Check the Speed parameter */
|
||
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||
|
|
|
||
|
|
/* Configure the IO Speed */
|
||
|
|
temp = GPIOx->OSPEEDR;
|
||
|
|
8000bec: 687b ldr r3, [r7, #4]
|
||
|
|
8000bee: 689b ldr r3, [r3, #8]
|
||
|
|
8000bf0: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
||
|
|
8000bf2: 697b ldr r3, [r7, #20]
|
||
|
|
8000bf4: 005b lsls r3, r3, #1
|
||
|
|
8000bf6: 2203 movs r2, #3
|
||
|
|
8000bf8: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000bfc: 43db mvns r3, r3
|
||
|
|
8000bfe: 693a ldr r2, [r7, #16]
|
||
|
|
8000c00: 4013 ands r3, r2
|
||
|
|
8000c02: 613b str r3, [r7, #16]
|
||
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
||
|
|
8000c04: 683b ldr r3, [r7, #0]
|
||
|
|
8000c06: 68da ldr r2, [r3, #12]
|
||
|
|
8000c08: 697b ldr r3, [r7, #20]
|
||
|
|
8000c0a: 005b lsls r3, r3, #1
|
||
|
|
8000c0c: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000c10: 693a ldr r2, [r7, #16]
|
||
|
|
8000c12: 4313 orrs r3, r2
|
||
|
|
8000c14: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->OSPEEDR = temp;
|
||
|
|
8000c16: 687b ldr r3, [r7, #4]
|
||
|
|
8000c18: 693a ldr r2, [r7, #16]
|
||
|
|
8000c1a: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
/* Configure the IO Output Type */
|
||
|
|
temp = GPIOx->OTYPER;
|
||
|
|
8000c1c: 687b ldr r3, [r7, #4]
|
||
|
|
8000c1e: 685b ldr r3, [r3, #4]
|
||
|
|
8000c20: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
||
|
|
8000c22: 2201 movs r2, #1
|
||
|
|
8000c24: 697b ldr r3, [r7, #20]
|
||
|
|
8000c26: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000c2a: 43db mvns r3, r3
|
||
|
|
8000c2c: 693a ldr r2, [r7, #16]
|
||
|
|
8000c2e: 4013 ands r3, r2
|
||
|
|
8000c30: 613b str r3, [r7, #16]
|
||
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
||
|
|
8000c32: 683b ldr r3, [r7, #0]
|
||
|
|
8000c34: 685b ldr r3, [r3, #4]
|
||
|
|
8000c36: 091b lsrs r3, r3, #4
|
||
|
|
8000c38: f003 0201 and.w r2, r3, #1
|
||
|
|
8000c3c: 697b ldr r3, [r7, #20]
|
||
|
|
8000c3e: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000c42: 693a ldr r2, [r7, #16]
|
||
|
|
8000c44: 4313 orrs r3, r2
|
||
|
|
8000c46: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->OTYPER = temp;
|
||
|
|
8000c48: 687b ldr r3, [r7, #4]
|
||
|
|
8000c4a: 693a ldr r2, [r7, #16]
|
||
|
|
8000c4c: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
||
|
|
|
||
|
|
/* In case of Analog mode, check if ADC control mode is selected */
|
||
|
|
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
|
||
|
|
8000c4e: 683b ldr r3, [r7, #0]
|
||
|
|
8000c50: 685b ldr r3, [r3, #4]
|
||
|
|
8000c52: f003 0303 and.w r3, r3, #3
|
||
|
|
8000c56: 2b03 cmp r3, #3
|
||
|
|
8000c58: d118 bne.n 8000c8c <HAL_GPIO_Init+0xe0>
|
||
|
|
{
|
||
|
|
/* Configure the IO Output Type */
|
||
|
|
temp = GPIOx->ASCR;
|
||
|
|
8000c5a: 687b ldr r3, [r7, #4]
|
||
|
|
8000c5c: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
8000c5e: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(GPIO_ASCR_ASC0 << position) ;
|
||
|
|
8000c60: 2201 movs r2, #1
|
||
|
|
8000c62: 697b ldr r3, [r7, #20]
|
||
|
|
8000c64: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000c68: 43db mvns r3, r3
|
||
|
|
8000c6a: 693a ldr r2, [r7, #16]
|
||
|
|
8000c6c: 4013 ands r3, r2
|
||
|
|
8000c6e: 613b str r3, [r7, #16]
|
||
|
|
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
|
||
|
|
8000c70: 683b ldr r3, [r7, #0]
|
||
|
|
8000c72: 685b ldr r3, [r3, #4]
|
||
|
|
8000c74: 08db lsrs r3, r3, #3
|
||
|
|
8000c76: f003 0201 and.w r2, r3, #1
|
||
|
|
8000c7a: 697b ldr r3, [r7, #20]
|
||
|
|
8000c7c: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000c80: 693a ldr r2, [r7, #16]
|
||
|
|
8000c82: 4313 orrs r3, r2
|
||
|
|
8000c84: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->ASCR = temp;
|
||
|
|
8000c86: 687b ldr r3, [r7, #4]
|
||
|
|
8000c88: 693a ldr r2, [r7, #16]
|
||
|
|
8000c8a: 62da str r2, [r3, #44] ; 0x2c
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
||
|
|
|
||
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
||
|
|
8000c8c: 683b ldr r3, [r7, #0]
|
||
|
|
8000c8e: 685b ldr r3, [r3, #4]
|
||
|
|
8000c90: f003 0303 and.w r3, r3, #3
|
||
|
|
8000c94: 2b03 cmp r3, #3
|
||
|
|
8000c96: d017 beq.n 8000cc8 <HAL_GPIO_Init+0x11c>
|
||
|
|
{
|
||
|
|
/* Check the Pull parameter */
|
||
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||
|
|
|
||
|
|
temp = GPIOx->PUPDR;
|
||
|
|
8000c98: 687b ldr r3, [r7, #4]
|
||
|
|
8000c9a: 68db ldr r3, [r3, #12]
|
||
|
|
8000c9c: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
||
|
|
8000c9e: 697b ldr r3, [r7, #20]
|
||
|
|
8000ca0: 005b lsls r3, r3, #1
|
||
|
|
8000ca2: 2203 movs r2, #3
|
||
|
|
8000ca4: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000ca8: 43db mvns r3, r3
|
||
|
|
8000caa: 693a ldr r2, [r7, #16]
|
||
|
|
8000cac: 4013 ands r3, r2
|
||
|
|
8000cae: 613b str r3, [r7, #16]
|
||
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
||
|
|
8000cb0: 683b ldr r3, [r7, #0]
|
||
|
|
8000cb2: 689a ldr r2, [r3, #8]
|
||
|
|
8000cb4: 697b ldr r3, [r7, #20]
|
||
|
|
8000cb6: 005b lsls r3, r3, #1
|
||
|
|
8000cb8: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000cbc: 693a ldr r2, [r7, #16]
|
||
|
|
8000cbe: 4313 orrs r3, r2
|
||
|
|
8000cc0: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->PUPDR = temp;
|
||
|
|
8000cc2: 687b ldr r3, [r7, #4]
|
||
|
|
8000cc4: 693a ldr r2, [r7, #16]
|
||
|
|
8000cc6: 60da str r2, [r3, #12]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* In case of Alternate function mode selection */
|
||
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
||
|
|
8000cc8: 683b ldr r3, [r7, #0]
|
||
|
|
8000cca: 685b ldr r3, [r3, #4]
|
||
|
|
8000ccc: f003 0303 and.w r3, r3, #3
|
||
|
|
8000cd0: 2b02 cmp r3, #2
|
||
|
|
8000cd2: d123 bne.n 8000d1c <HAL_GPIO_Init+0x170>
|
||
|
|
/* Check the Alternate function parameters */
|
||
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||
|
|
|
||
|
|
/* Configure Alternate function mapped with the current IO */
|
||
|
|
temp = GPIOx->AFR[position >> 3u];
|
||
|
|
8000cd4: 697b ldr r3, [r7, #20]
|
||
|
|
8000cd6: 08da lsrs r2, r3, #3
|
||
|
|
8000cd8: 687b ldr r3, [r7, #4]
|
||
|
|
8000cda: 3208 adds r2, #8
|
||
|
|
8000cdc: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
||
|
|
8000ce0: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
||
|
|
8000ce2: 697b ldr r3, [r7, #20]
|
||
|
|
8000ce4: f003 0307 and.w r3, r3, #7
|
||
|
|
8000ce8: 009b lsls r3, r3, #2
|
||
|
|
8000cea: 220f movs r2, #15
|
||
|
|
8000cec: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000cf0: 43db mvns r3, r3
|
||
|
|
8000cf2: 693a ldr r2, [r7, #16]
|
||
|
|
8000cf4: 4013 ands r3, r2
|
||
|
|
8000cf6: 613b str r3, [r7, #16]
|
||
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
||
|
|
8000cf8: 683b ldr r3, [r7, #0]
|
||
|
|
8000cfa: 691a ldr r2, [r3, #16]
|
||
|
|
8000cfc: 697b ldr r3, [r7, #20]
|
||
|
|
8000cfe: f003 0307 and.w r3, r3, #7
|
||
|
|
8000d02: 009b lsls r3, r3, #2
|
||
|
|
8000d04: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000d08: 693a ldr r2, [r7, #16]
|
||
|
|
8000d0a: 4313 orrs r3, r2
|
||
|
|
8000d0c: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->AFR[position >> 3u] = temp;
|
||
|
|
8000d0e: 697b ldr r3, [r7, #20]
|
||
|
|
8000d10: 08da lsrs r2, r3, #3
|
||
|
|
8000d12: 687b ldr r3, [r7, #4]
|
||
|
|
8000d14: 3208 adds r2, #8
|
||
|
|
8000d16: 6939 ldr r1, [r7, #16]
|
||
|
|
8000d18: f843 1022 str.w r1, [r3, r2, lsl #2]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||
|
|
temp = GPIOx->MODER;
|
||
|
|
8000d1c: 687b ldr r3, [r7, #4]
|
||
|
|
8000d1e: 681b ldr r3, [r3, #0]
|
||
|
|
8000d20: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
||
|
|
8000d22: 697b ldr r3, [r7, #20]
|
||
|
|
8000d24: 005b lsls r3, r3, #1
|
||
|
|
8000d26: 2203 movs r2, #3
|
||
|
|
8000d28: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000d2c: 43db mvns r3, r3
|
||
|
|
8000d2e: 693a ldr r2, [r7, #16]
|
||
|
|
8000d30: 4013 ands r3, r2
|
||
|
|
8000d32: 613b str r3, [r7, #16]
|
||
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
||
|
|
8000d34: 683b ldr r3, [r7, #0]
|
||
|
|
8000d36: 685b ldr r3, [r3, #4]
|
||
|
|
8000d38: f003 0203 and.w r2, r3, #3
|
||
|
|
8000d3c: 697b ldr r3, [r7, #20]
|
||
|
|
8000d3e: 005b lsls r3, r3, #1
|
||
|
|
8000d40: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000d44: 693a ldr r2, [r7, #16]
|
||
|
|
8000d46: 4313 orrs r3, r2
|
||
|
|
8000d48: 613b str r3, [r7, #16]
|
||
|
|
GPIOx->MODER = temp;
|
||
|
|
8000d4a: 687b ldr r3, [r7, #4]
|
||
|
|
8000d4c: 693a ldr r2, [r7, #16]
|
||
|
|
8000d4e: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||
|
|
/* Configure the External Interrupt or event for the current IO */
|
||
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
||
|
|
8000d50: 683b ldr r3, [r7, #0]
|
||
|
|
8000d52: 685b ldr r3, [r3, #4]
|
||
|
|
8000d54: f403 3340 and.w r3, r3, #196608 ; 0x30000
|
||
|
|
8000d58: 2b00 cmp r3, #0
|
||
|
|
8000d5a: f000 80ac beq.w 8000eb6 <HAL_GPIO_Init+0x30a>
|
||
|
|
{
|
||
|
|
/* Enable SYSCFG Clock */
|
||
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||
|
|
8000d5e: 4b5f ldr r3, [pc, #380] ; (8000edc <HAL_GPIO_Init+0x330>)
|
||
|
|
8000d60: 6e1b ldr r3, [r3, #96] ; 0x60
|
||
|
|
8000d62: 4a5e ldr r2, [pc, #376] ; (8000edc <HAL_GPIO_Init+0x330>)
|
||
|
|
8000d64: f043 0301 orr.w r3, r3, #1
|
||
|
|
8000d68: 6613 str r3, [r2, #96] ; 0x60
|
||
|
|
8000d6a: 4b5c ldr r3, [pc, #368] ; (8000edc <HAL_GPIO_Init+0x330>)
|
||
|
|
8000d6c: 6e1b ldr r3, [r3, #96] ; 0x60
|
||
|
|
8000d6e: f003 0301 and.w r3, r3, #1
|
||
|
|
8000d72: 60bb str r3, [r7, #8]
|
||
|
|
8000d74: 68bb ldr r3, [r7, #8]
|
||
|
|
|
||
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
||
|
|
8000d76: 4a5a ldr r2, [pc, #360] ; (8000ee0 <HAL_GPIO_Init+0x334>)
|
||
|
|
8000d78: 697b ldr r3, [r7, #20]
|
||
|
|
8000d7a: 089b lsrs r3, r3, #2
|
||
|
|
8000d7c: 3302 adds r3, #2
|
||
|
|
8000d7e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
||
|
|
8000d82: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
||
|
|
8000d84: 697b ldr r3, [r7, #20]
|
||
|
|
8000d86: f003 0303 and.w r3, r3, #3
|
||
|
|
8000d8a: 009b lsls r3, r3, #2
|
||
|
|
8000d8c: 220f movs r2, #15
|
||
|
|
8000d8e: fa02 f303 lsl.w r3, r2, r3
|
||
|
|
8000d92: 43db mvns r3, r3
|
||
|
|
8000d94: 693a ldr r2, [r7, #16]
|
||
|
|
8000d96: 4013 ands r3, r2
|
||
|
|
8000d98: 613b str r3, [r7, #16]
|
||
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
||
|
|
8000d9a: 687b ldr r3, [r7, #4]
|
||
|
|
8000d9c: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000
|
||
|
|
8000da0: d025 beq.n 8000dee <HAL_GPIO_Init+0x242>
|
||
|
|
8000da2: 687b ldr r3, [r7, #4]
|
||
|
|
8000da4: 4a4f ldr r2, [pc, #316] ; (8000ee4 <HAL_GPIO_Init+0x338>)
|
||
|
|
8000da6: 4293 cmp r3, r2
|
||
|
|
8000da8: d01f beq.n 8000dea <HAL_GPIO_Init+0x23e>
|
||
|
|
8000daa: 687b ldr r3, [r7, #4]
|
||
|
|
8000dac: 4a4e ldr r2, [pc, #312] ; (8000ee8 <HAL_GPIO_Init+0x33c>)
|
||
|
|
8000dae: 4293 cmp r3, r2
|
||
|
|
8000db0: d019 beq.n 8000de6 <HAL_GPIO_Init+0x23a>
|
||
|
|
8000db2: 687b ldr r3, [r7, #4]
|
||
|
|
8000db4: 4a4d ldr r2, [pc, #308] ; (8000eec <HAL_GPIO_Init+0x340>)
|
||
|
|
8000db6: 4293 cmp r3, r2
|
||
|
|
8000db8: d013 beq.n 8000de2 <HAL_GPIO_Init+0x236>
|
||
|
|
8000dba: 687b ldr r3, [r7, #4]
|
||
|
|
8000dbc: 4a4c ldr r2, [pc, #304] ; (8000ef0 <HAL_GPIO_Init+0x344>)
|
||
|
|
8000dbe: 4293 cmp r3, r2
|
||
|
|
8000dc0: d00d beq.n 8000dde <HAL_GPIO_Init+0x232>
|
||
|
|
8000dc2: 687b ldr r3, [r7, #4]
|
||
|
|
8000dc4: 4a4b ldr r2, [pc, #300] ; (8000ef4 <HAL_GPIO_Init+0x348>)
|
||
|
|
8000dc6: 4293 cmp r3, r2
|
||
|
|
8000dc8: d007 beq.n 8000dda <HAL_GPIO_Init+0x22e>
|
||
|
|
8000dca: 687b ldr r3, [r7, #4]
|
||
|
|
8000dcc: 4a4a ldr r2, [pc, #296] ; (8000ef8 <HAL_GPIO_Init+0x34c>)
|
||
|
|
8000dce: 4293 cmp r3, r2
|
||
|
|
8000dd0: d101 bne.n 8000dd6 <HAL_GPIO_Init+0x22a>
|
||
|
|
8000dd2: 2306 movs r3, #6
|
||
|
|
8000dd4: e00c b.n 8000df0 <HAL_GPIO_Init+0x244>
|
||
|
|
8000dd6: 2307 movs r3, #7
|
||
|
|
8000dd8: e00a b.n 8000df0 <HAL_GPIO_Init+0x244>
|
||
|
|
8000dda: 2305 movs r3, #5
|
||
|
|
8000ddc: e008 b.n 8000df0 <HAL_GPIO_Init+0x244>
|
||
|
|
8000dde: 2304 movs r3, #4
|
||
|
|
8000de0: e006 b.n 8000df0 <HAL_GPIO_Init+0x244>
|
||
|
|
8000de2: 2303 movs r3, #3
|
||
|
|
8000de4: e004 b.n 8000df0 <HAL_GPIO_Init+0x244>
|
||
|
|
8000de6: 2302 movs r3, #2
|
||
|
|
8000de8: e002 b.n 8000df0 <HAL_GPIO_Init+0x244>
|
||
|
|
8000dea: 2301 movs r3, #1
|
||
|
|
8000dec: e000 b.n 8000df0 <HAL_GPIO_Init+0x244>
|
||
|
|
8000dee: 2300 movs r3, #0
|
||
|
|
8000df0: 697a ldr r2, [r7, #20]
|
||
|
|
8000df2: f002 0203 and.w r2, r2, #3
|
||
|
|
8000df6: 0092 lsls r2, r2, #2
|
||
|
|
8000df8: 4093 lsls r3, r2
|
||
|
|
8000dfa: 693a ldr r2, [r7, #16]
|
||
|
|
8000dfc: 4313 orrs r3, r2
|
||
|
|
8000dfe: 613b str r3, [r7, #16]
|
||
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
||
|
|
8000e00: 4937 ldr r1, [pc, #220] ; (8000ee0 <HAL_GPIO_Init+0x334>)
|
||
|
|
8000e02: 697b ldr r3, [r7, #20]
|
||
|
|
8000e04: 089b lsrs r3, r3, #2
|
||
|
|
8000e06: 3302 adds r3, #2
|
||
|
|
8000e08: 693a ldr r2, [r7, #16]
|
||
|
|
8000e0a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
||
|
|
|
||
|
|
/* Clear Rising Falling edge configuration */
|
||
|
|
temp = EXTI->RTSR1;
|
||
|
|
8000e0e: 4b3b ldr r3, [pc, #236] ; (8000efc <HAL_GPIO_Init+0x350>)
|
||
|
|
8000e10: 689b ldr r3, [r3, #8]
|
||
|
|
8000e12: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(iocurrent);
|
||
|
|
8000e14: 68fb ldr r3, [r7, #12]
|
||
|
|
8000e16: 43db mvns r3, r3
|
||
|
|
8000e18: 693a ldr r2, [r7, #16]
|
||
|
|
8000e1a: 4013 ands r3, r2
|
||
|
|
8000e1c: 613b str r3, [r7, #16]
|
||
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
||
|
|
8000e1e: 683b ldr r3, [r7, #0]
|
||
|
|
8000e20: 685b ldr r3, [r3, #4]
|
||
|
|
8000e22: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
||
|
|
8000e26: 2b00 cmp r3, #0
|
||
|
|
8000e28: d003 beq.n 8000e32 <HAL_GPIO_Init+0x286>
|
||
|
|
{
|
||
|
|
temp |= iocurrent;
|
||
|
|
8000e2a: 693a ldr r2, [r7, #16]
|
||
|
|
8000e2c: 68fb ldr r3, [r7, #12]
|
||
|
|
8000e2e: 4313 orrs r3, r2
|
||
|
|
8000e30: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
EXTI->RTSR1 = temp;
|
||
|
|
8000e32: 4a32 ldr r2, [pc, #200] ; (8000efc <HAL_GPIO_Init+0x350>)
|
||
|
|
8000e34: 693b ldr r3, [r7, #16]
|
||
|
|
8000e36: 6093 str r3, [r2, #8]
|
||
|
|
|
||
|
|
temp = EXTI->FTSR1;
|
||
|
|
8000e38: 4b30 ldr r3, [pc, #192] ; (8000efc <HAL_GPIO_Init+0x350>)
|
||
|
|
8000e3a: 68db ldr r3, [r3, #12]
|
||
|
|
8000e3c: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(iocurrent);
|
||
|
|
8000e3e: 68fb ldr r3, [r7, #12]
|
||
|
|
8000e40: 43db mvns r3, r3
|
||
|
|
8000e42: 693a ldr r2, [r7, #16]
|
||
|
|
8000e44: 4013 ands r3, r2
|
||
|
|
8000e46: 613b str r3, [r7, #16]
|
||
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
||
|
|
8000e48: 683b ldr r3, [r7, #0]
|
||
|
|
8000e4a: 685b ldr r3, [r3, #4]
|
||
|
|
8000e4c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
||
|
|
8000e50: 2b00 cmp r3, #0
|
||
|
|
8000e52: d003 beq.n 8000e5c <HAL_GPIO_Init+0x2b0>
|
||
|
|
{
|
||
|
|
temp |= iocurrent;
|
||
|
|
8000e54: 693a ldr r2, [r7, #16]
|
||
|
|
8000e56: 68fb ldr r3, [r7, #12]
|
||
|
|
8000e58: 4313 orrs r3, r2
|
||
|
|
8000e5a: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
EXTI->FTSR1 = temp;
|
||
|
|
8000e5c: 4a27 ldr r2, [pc, #156] ; (8000efc <HAL_GPIO_Init+0x350>)
|
||
|
|
8000e5e: 693b ldr r3, [r7, #16]
|
||
|
|
8000e60: 60d3 str r3, [r2, #12]
|
||
|
|
|
||
|
|
/* Clear EXTI line configuration */
|
||
|
|
temp = EXTI->EMR1;
|
||
|
|
8000e62: 4b26 ldr r3, [pc, #152] ; (8000efc <HAL_GPIO_Init+0x350>)
|
||
|
|
8000e64: 685b ldr r3, [r3, #4]
|
||
|
|
8000e66: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(iocurrent);
|
||
|
|
8000e68: 68fb ldr r3, [r7, #12]
|
||
|
|
8000e6a: 43db mvns r3, r3
|
||
|
|
8000e6c: 693a ldr r2, [r7, #16]
|
||
|
|
8000e6e: 4013 ands r3, r2
|
||
|
|
8000e70: 613b str r3, [r7, #16]
|
||
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
||
|
|
8000e72: 683b ldr r3, [r7, #0]
|
||
|
|
8000e74: 685b ldr r3, [r3, #4]
|
||
|
|
8000e76: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
||
|
|
8000e7a: 2b00 cmp r3, #0
|
||
|
|
8000e7c: d003 beq.n 8000e86 <HAL_GPIO_Init+0x2da>
|
||
|
|
{
|
||
|
|
temp |= iocurrent;
|
||
|
|
8000e7e: 693a ldr r2, [r7, #16]
|
||
|
|
8000e80: 68fb ldr r3, [r7, #12]
|
||
|
|
8000e82: 4313 orrs r3, r2
|
||
|
|
8000e84: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
EXTI->EMR1 = temp;
|
||
|
|
8000e86: 4a1d ldr r2, [pc, #116] ; (8000efc <HAL_GPIO_Init+0x350>)
|
||
|
|
8000e88: 693b ldr r3, [r7, #16]
|
||
|
|
8000e8a: 6053 str r3, [r2, #4]
|
||
|
|
|
||
|
|
temp = EXTI->IMR1;
|
||
|
|
8000e8c: 4b1b ldr r3, [pc, #108] ; (8000efc <HAL_GPIO_Init+0x350>)
|
||
|
|
8000e8e: 681b ldr r3, [r3, #0]
|
||
|
|
8000e90: 613b str r3, [r7, #16]
|
||
|
|
temp &= ~(iocurrent);
|
||
|
|
8000e92: 68fb ldr r3, [r7, #12]
|
||
|
|
8000e94: 43db mvns r3, r3
|
||
|
|
8000e96: 693a ldr r2, [r7, #16]
|
||
|
|
8000e98: 4013 ands r3, r2
|
||
|
|
8000e9a: 613b str r3, [r7, #16]
|
||
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
||
|
|
8000e9c: 683b ldr r3, [r7, #0]
|
||
|
|
8000e9e: 685b ldr r3, [r3, #4]
|
||
|
|
8000ea0: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
||
|
|
8000ea4: 2b00 cmp r3, #0
|
||
|
|
8000ea6: d003 beq.n 8000eb0 <HAL_GPIO_Init+0x304>
|
||
|
|
{
|
||
|
|
temp |= iocurrent;
|
||
|
|
8000ea8: 693a ldr r2, [r7, #16]
|
||
|
|
8000eaa: 68fb ldr r3, [r7, #12]
|
||
|
|
8000eac: 4313 orrs r3, r2
|
||
|
|
8000eae: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
EXTI->IMR1 = temp;
|
||
|
|
8000eb0: 4a12 ldr r2, [pc, #72] ; (8000efc <HAL_GPIO_Init+0x350>)
|
||
|
|
8000eb2: 693b ldr r3, [r7, #16]
|
||
|
|
8000eb4: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
position++;
|
||
|
|
8000eb6: 697b ldr r3, [r7, #20]
|
||
|
|
8000eb8: 3301 adds r3, #1
|
||
|
|
8000eba: 617b str r3, [r7, #20]
|
||
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
||
|
|
8000ebc: 683b ldr r3, [r7, #0]
|
||
|
|
8000ebe: 681a ldr r2, [r3, #0]
|
||
|
|
8000ec0: 697b ldr r3, [r7, #20]
|
||
|
|
8000ec2: fa22 f303 lsr.w r3, r2, r3
|
||
|
|
8000ec6: 2b00 cmp r3, #0
|
||
|
|
8000ec8: f47f ae78 bne.w 8000bbc <HAL_GPIO_Init+0x10>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8000ecc: bf00 nop
|
||
|
|
8000ece: bf00 nop
|
||
|
|
8000ed0: 371c adds r7, #28
|
||
|
|
8000ed2: 46bd mov sp, r7
|
||
|
|
8000ed4: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8000ed8: 4770 bx lr
|
||
|
|
8000eda: bf00 nop
|
||
|
|
8000edc: 40021000 .word 0x40021000
|
||
|
|
8000ee0: 40010000 .word 0x40010000
|
||
|
|
8000ee4: 48000400 .word 0x48000400
|
||
|
|
8000ee8: 48000800 .word 0x48000800
|
||
|
|
8000eec: 48000c00 .word 0x48000c00
|
||
|
|
8000ef0: 48001000 .word 0x48001000
|
||
|
|
8000ef4: 48001400 .word 0x48001400
|
||
|
|
8000ef8: 48001800 .word 0x48001800
|
||
|
|
8000efc: 40010400 .word 0x40010400
|
||
|
|
|
||
|
|
08000f00 <HAL_GPIO_WritePin>:
|
||
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
||
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||
|
|
{
|
||
|
|
8000f00: b480 push {r7}
|
||
|
|
8000f02: b083 sub sp, #12
|
||
|
|
8000f04: af00 add r7, sp, #0
|
||
|
|
8000f06: 6078 str r0, [r7, #4]
|
||
|
|
8000f08: 460b mov r3, r1
|
||
|
|
8000f0a: 807b strh r3, [r7, #2]
|
||
|
|
8000f0c: 4613 mov r3, r2
|
||
|
|
8000f0e: 707b strb r3, [r7, #1]
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||
|
|
|
||
|
|
if(PinState != GPIO_PIN_RESET)
|
||
|
|
8000f10: 787b ldrb r3, [r7, #1]
|
||
|
|
8000f12: 2b00 cmp r3, #0
|
||
|
|
8000f14: d003 beq.n 8000f1e <HAL_GPIO_WritePin+0x1e>
|
||
|
|
{
|
||
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
||
|
|
8000f16: 887a ldrh r2, [r7, #2]
|
||
|
|
8000f18: 687b ldr r3, [r7, #4]
|
||
|
|
8000f1a: 619a str r2, [r3, #24]
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8000f1c: e002 b.n 8000f24 <HAL_GPIO_WritePin+0x24>
|
||
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
||
|
|
8000f1e: 887a ldrh r2, [r7, #2]
|
||
|
|
8000f20: 687b ldr r3, [r7, #4]
|
||
|
|
8000f22: 629a str r2, [r3, #40] ; 0x28
|
||
|
|
}
|
||
|
|
8000f24: bf00 nop
|
||
|
|
8000f26: 370c adds r7, #12
|
||
|
|
8000f28: 46bd mov sp, r7
|
||
|
|
8000f2a: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8000f2e: 4770 bx lr
|
||
|
|
|
||
|
|
08000f30 <HAL_PWREx_GetVoltageRange>:
|
||
|
|
* @brief Return Voltage Scaling Range.
|
||
|
|
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
|
||
|
|
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
|
||
|
|
*/
|
||
|
|
uint32_t HAL_PWREx_GetVoltageRange(void)
|
||
|
|
{
|
||
|
|
8000f30: b480 push {r7}
|
||
|
|
8000f32: af00 add r7, sp, #0
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
return (PWR->CR1 & PWR_CR1_VOS);
|
||
|
|
8000f34: 4b04 ldr r3, [pc, #16] ; (8000f48 <HAL_PWREx_GetVoltageRange+0x18>)
|
||
|
|
8000f36: 681b ldr r3, [r3, #0]
|
||
|
|
8000f38: f403 63c0 and.w r3, r3, #1536 ; 0x600
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
8000f3c: 4618 mov r0, r3
|
||
|
|
8000f3e: 46bd mov sp, r7
|
||
|
|
8000f40: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8000f44: 4770 bx lr
|
||
|
|
8000f46: bf00 nop
|
||
|
|
8000f48: 40007000 .word 0x40007000
|
||
|
|
|
||
|
|
08000f4c <HAL_PWREx_ControlVoltageScaling>:
|
||
|
|
* cleared before returning the status. If the flag is not cleared within
|
||
|
|
* 50 microseconds, HAL_TIMEOUT status is reported.
|
||
|
|
* @retval HAL Status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
||
|
|
{
|
||
|
|
8000f4c: b480 push {r7}
|
||
|
|
8000f4e: b085 sub sp, #20
|
||
|
|
8000f50: af00 add r7, sp, #0
|
||
|
|
8000f52: 6078 str r0, [r7, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
#else
|
||
|
|
|
||
|
|
/* If Set Range 1 */
|
||
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
||
|
|
8000f54: 687b ldr r3, [r7, #4]
|
||
|
|
8000f56: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
||
|
|
8000f5a: d130 bne.n 8000fbe <HAL_PWREx_ControlVoltageScaling+0x72>
|
||
|
|
{
|
||
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
|
||
|
|
8000f5c: 4b23 ldr r3, [pc, #140] ; (8000fec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
||
|
|
8000f5e: 681b ldr r3, [r3, #0]
|
||
|
|
8000f60: f403 63c0 and.w r3, r3, #1536 ; 0x600
|
||
|
|
8000f64: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
||
|
|
8000f68: d038 beq.n 8000fdc <HAL_PWREx_ControlVoltageScaling+0x90>
|
||
|
|
{
|
||
|
|
/* Set Range 1 */
|
||
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
||
|
|
8000f6a: 4b20 ldr r3, [pc, #128] ; (8000fec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
||
|
|
8000f6c: 681b ldr r3, [r3, #0]
|
||
|
|
8000f6e: f423 63c0 bic.w r3, r3, #1536 ; 0x600
|
||
|
|
8000f72: 4a1e ldr r2, [pc, #120] ; (8000fec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
||
|
|
8000f74: f443 7300 orr.w r3, r3, #512 ; 0x200
|
||
|
|
8000f78: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Wait until VOSF is cleared */
|
||
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
||
|
|
8000f7a: 4b1d ldr r3, [pc, #116] ; (8000ff0 <HAL_PWREx_ControlVoltageScaling+0xa4>)
|
||
|
|
8000f7c: 681b ldr r3, [r3, #0]
|
||
|
|
8000f7e: 2232 movs r2, #50 ; 0x32
|
||
|
|
8000f80: fb02 f303 mul.w r3, r2, r3
|
||
|
|
8000f84: 4a1b ldr r2, [pc, #108] ; (8000ff4 <HAL_PWREx_ControlVoltageScaling+0xa8>)
|
||
|
|
8000f86: fba2 2303 umull r2, r3, r2, r3
|
||
|
|
8000f8a: 0c9b lsrs r3, r3, #18
|
||
|
|
8000f8c: 3301 adds r3, #1
|
||
|
|
8000f8e: 60fb str r3, [r7, #12]
|
||
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
||
|
|
8000f90: e002 b.n 8000f98 <HAL_PWREx_ControlVoltageScaling+0x4c>
|
||
|
|
{
|
||
|
|
wait_loop_index--;
|
||
|
|
8000f92: 68fb ldr r3, [r7, #12]
|
||
|
|
8000f94: 3b01 subs r3, #1
|
||
|
|
8000f96: 60fb str r3, [r7, #12]
|
||
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
||
|
|
8000f98: 4b14 ldr r3, [pc, #80] ; (8000fec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
||
|
|
8000f9a: 695b ldr r3, [r3, #20]
|
||
|
|
8000f9c: f403 6380 and.w r3, r3, #1024 ; 0x400
|
||
|
|
8000fa0: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
||
|
|
8000fa4: d102 bne.n 8000fac <HAL_PWREx_ControlVoltageScaling+0x60>
|
||
|
|
8000fa6: 68fb ldr r3, [r7, #12]
|
||
|
|
8000fa8: 2b00 cmp r3, #0
|
||
|
|
8000faa: d1f2 bne.n 8000f92 <HAL_PWREx_ControlVoltageScaling+0x46>
|
||
|
|
}
|
||
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
||
|
|
8000fac: 4b0f ldr r3, [pc, #60] ; (8000fec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
||
|
|
8000fae: 695b ldr r3, [r3, #20]
|
||
|
|
8000fb0: f403 6380 and.w r3, r3, #1024 ; 0x400
|
||
|
|
8000fb4: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
||
|
|
8000fb8: d110 bne.n 8000fdc <HAL_PWREx_ControlVoltageScaling+0x90>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8000fba: 2303 movs r3, #3
|
||
|
|
8000fbc: e00f b.n 8000fde <HAL_PWREx_ControlVoltageScaling+0x92>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
|
||
|
|
8000fbe: 4b0b ldr r3, [pc, #44] ; (8000fec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
||
|
|
8000fc0: 681b ldr r3, [r3, #0]
|
||
|
|
8000fc2: f403 63c0 and.w r3, r3, #1536 ; 0x600
|
||
|
|
8000fc6: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
||
|
|
8000fca: d007 beq.n 8000fdc <HAL_PWREx_ControlVoltageScaling+0x90>
|
||
|
|
{
|
||
|
|
/* Set Range 2 */
|
||
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
|
||
|
|
8000fcc: 4b07 ldr r3, [pc, #28] ; (8000fec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
||
|
|
8000fce: 681b ldr r3, [r3, #0]
|
||
|
|
8000fd0: f423 63c0 bic.w r3, r3, #1536 ; 0x600
|
||
|
|
8000fd4: 4a05 ldr r2, [pc, #20] ; (8000fec <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
||
|
|
8000fd6: f443 6380 orr.w r3, r3, #1024 ; 0x400
|
||
|
|
8000fda: 6013 str r3, [r2, #0]
|
||
|
|
/* No need to wait for VOSF to be cleared for this transition */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return HAL_OK;
|
||
|
|
8000fdc: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8000fde: 4618 mov r0, r3
|
||
|
|
8000fe0: 3714 adds r7, #20
|
||
|
|
8000fe2: 46bd mov sp, r7
|
||
|
|
8000fe4: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8000fe8: 4770 bx lr
|
||
|
|
8000fea: bf00 nop
|
||
|
|
8000fec: 40007000 .word 0x40007000
|
||
|
|
8000ff0: 20000000 .word 0x20000000
|
||
|
|
8000ff4: 431bde83 .word 0x431bde83
|
||
|
|
|
||
|
|
08000ff8 <HAL_RCC_OscConfig>:
|
||
|
|
* supported by this macro. User should request a transition to HSE Off
|
||
|
|
* first and then HSE On or HSE Bypass.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
||
|
|
{
|
||
|
|
8000ff8: b580 push {r7, lr}
|
||
|
|
8000ffa: b088 sub sp, #32
|
||
|
|
8000ffc: af00 add r7, sp, #0
|
||
|
|
8000ffe: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t tickstart;
|
||
|
|
HAL_StatusTypeDef status;
|
||
|
|
uint32_t sysclk_source, pll_config;
|
||
|
|
|
||
|
|
/* Check Null pointer */
|
||
|
|
if(RCC_OscInitStruct == NULL)
|
||
|
|
8001000: 687b ldr r3, [r7, #4]
|
||
|
|
8001002: 2b00 cmp r3, #0
|
||
|
|
8001004: d101 bne.n 800100a <HAL_RCC_OscConfig+0x12>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001006: 2301 movs r3, #1
|
||
|
|
8001008: e3ca b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
||
|
|
|
||
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
||
|
|
800100a: 4b97 ldr r3, [pc, #604] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800100c: 689b ldr r3, [r3, #8]
|
||
|
|
800100e: f003 030c and.w r3, r3, #12
|
||
|
|
8001012: 61bb str r3, [r7, #24]
|
||
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
||
|
|
8001014: 4b94 ldr r3, [pc, #592] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001016: 68db ldr r3, [r3, #12]
|
||
|
|
8001018: f003 0303 and.w r3, r3, #3
|
||
|
|
800101c: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
||
|
|
800101e: 687b ldr r3, [r7, #4]
|
||
|
|
8001020: 681b ldr r3, [r3, #0]
|
||
|
|
8001022: f003 0310 and.w r3, r3, #16
|
||
|
|
8001026: 2b00 cmp r3, #0
|
||
|
|
8001028: f000 80e4 beq.w 80011f4 <HAL_RCC_OscConfig+0x1fc>
|
||
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
||
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
||
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
||
|
|
|
||
|
|
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
|
||
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
||
|
|
800102c: 69bb ldr r3, [r7, #24]
|
||
|
|
800102e: 2b00 cmp r3, #0
|
||
|
|
8001030: d007 beq.n 8001042 <HAL_RCC_OscConfig+0x4a>
|
||
|
|
8001032: 69bb ldr r3, [r7, #24]
|
||
|
|
8001034: 2b0c cmp r3, #12
|
||
|
|
8001036: f040 808b bne.w 8001150 <HAL_RCC_OscConfig+0x158>
|
||
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
|
||
|
|
800103a: 697b ldr r3, [r7, #20]
|
||
|
|
800103c: 2b01 cmp r3, #1
|
||
|
|
800103e: f040 8087 bne.w 8001150 <HAL_RCC_OscConfig+0x158>
|
||
|
|
{
|
||
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
||
|
|
8001042: 4b89 ldr r3, [pc, #548] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001044: 681b ldr r3, [r3, #0]
|
||
|
|
8001046: f003 0302 and.w r3, r3, #2
|
||
|
|
800104a: 2b00 cmp r3, #0
|
||
|
|
800104c: d005 beq.n 800105a <HAL_RCC_OscConfig+0x62>
|
||
|
|
800104e: 687b ldr r3, [r7, #4]
|
||
|
|
8001050: 699b ldr r3, [r3, #24]
|
||
|
|
8001052: 2b00 cmp r3, #0
|
||
|
|
8001054: d101 bne.n 800105a <HAL_RCC_OscConfig+0x62>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001056: 2301 movs r3, #1
|
||
|
|
8001058: e3a2 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
||
|
|
must be correctly programmed according to the frequency of the CPU clock
|
||
|
|
(HCLK) and the supply voltage of the device. */
|
||
|
|
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
|
||
|
|
800105a: 687b ldr r3, [r7, #4]
|
||
|
|
800105c: 6a1a ldr r2, [r3, #32]
|
||
|
|
800105e: 4b82 ldr r3, [pc, #520] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001060: 681b ldr r3, [r3, #0]
|
||
|
|
8001062: f003 0308 and.w r3, r3, #8
|
||
|
|
8001066: 2b00 cmp r3, #0
|
||
|
|
8001068: d004 beq.n 8001074 <HAL_RCC_OscConfig+0x7c>
|
||
|
|
800106a: 4b7f ldr r3, [pc, #508] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800106c: 681b ldr r3, [r3, #0]
|
||
|
|
800106e: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
||
|
|
8001072: e005 b.n 8001080 <HAL_RCC_OscConfig+0x88>
|
||
|
|
8001074: 4b7c ldr r3, [pc, #496] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001076: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
||
|
|
800107a: 091b lsrs r3, r3, #4
|
||
|
|
800107c: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
||
|
|
8001080: 4293 cmp r3, r2
|
||
|
|
8001082: d223 bcs.n 80010cc <HAL_RCC_OscConfig+0xd4>
|
||
|
|
{
|
||
|
|
/* First increase number of wait states update if necessary */
|
||
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
||
|
|
8001084: 687b ldr r3, [r7, #4]
|
||
|
|
8001086: 6a1b ldr r3, [r3, #32]
|
||
|
|
8001088: 4618 mov r0, r3
|
||
|
|
800108a: f000 fd55 bl 8001b38 <RCC_SetFlashLatencyFromMSIRange>
|
||
|
|
800108e: 4603 mov r3, r0
|
||
|
|
8001090: 2b00 cmp r3, #0
|
||
|
|
8001092: d001 beq.n 8001098 <HAL_RCC_OscConfig+0xa0>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001094: 2301 movs r3, #1
|
||
|
|
8001096: e383 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
||
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
||
|
|
8001098: 4b73 ldr r3, [pc, #460] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800109a: 681b ldr r3, [r3, #0]
|
||
|
|
800109c: 4a72 ldr r2, [pc, #456] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800109e: f043 0308 orr.w r3, r3, #8
|
||
|
|
80010a2: 6013 str r3, [r2, #0]
|
||
|
|
80010a4: 4b70 ldr r3, [pc, #448] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80010a6: 681b ldr r3, [r3, #0]
|
||
|
|
80010a8: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
||
|
|
80010ac: 687b ldr r3, [r7, #4]
|
||
|
|
80010ae: 6a1b ldr r3, [r3, #32]
|
||
|
|
80010b0: 496d ldr r1, [pc, #436] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80010b2: 4313 orrs r3, r2
|
||
|
|
80010b4: 600b str r3, [r1, #0]
|
||
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
||
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
||
|
|
80010b6: 4b6c ldr r3, [pc, #432] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80010b8: 685b ldr r3, [r3, #4]
|
||
|
|
80010ba: f423 427f bic.w r2, r3, #65280 ; 0xff00
|
||
|
|
80010be: 687b ldr r3, [r7, #4]
|
||
|
|
80010c0: 69db ldr r3, [r3, #28]
|
||
|
|
80010c2: 021b lsls r3, r3, #8
|
||
|
|
80010c4: 4968 ldr r1, [pc, #416] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80010c6: 4313 orrs r3, r2
|
||
|
|
80010c8: 604b str r3, [r1, #4]
|
||
|
|
80010ca: e025 b.n 8001118 <HAL_RCC_OscConfig+0x120>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Else, keep current flash latency while decreasing applies */
|
||
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
||
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
||
|
|
80010cc: 4b66 ldr r3, [pc, #408] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80010ce: 681b ldr r3, [r3, #0]
|
||
|
|
80010d0: 4a65 ldr r2, [pc, #404] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80010d2: f043 0308 orr.w r3, r3, #8
|
||
|
|
80010d6: 6013 str r3, [r2, #0]
|
||
|
|
80010d8: 4b63 ldr r3, [pc, #396] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80010da: 681b ldr r3, [r3, #0]
|
||
|
|
80010dc: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
||
|
|
80010e0: 687b ldr r3, [r7, #4]
|
||
|
|
80010e2: 6a1b ldr r3, [r3, #32]
|
||
|
|
80010e4: 4960 ldr r1, [pc, #384] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80010e6: 4313 orrs r3, r2
|
||
|
|
80010e8: 600b str r3, [r1, #0]
|
||
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
||
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
||
|
|
80010ea: 4b5f ldr r3, [pc, #380] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80010ec: 685b ldr r3, [r3, #4]
|
||
|
|
80010ee: f423 427f bic.w r2, r3, #65280 ; 0xff00
|
||
|
|
80010f2: 687b ldr r3, [r7, #4]
|
||
|
|
80010f4: 69db ldr r3, [r3, #28]
|
||
|
|
80010f6: 021b lsls r3, r3, #8
|
||
|
|
80010f8: 495b ldr r1, [pc, #364] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80010fa: 4313 orrs r3, r2
|
||
|
|
80010fc: 604b str r3, [r1, #4]
|
||
|
|
|
||
|
|
/* Decrease number of wait states update if necessary */
|
||
|
|
/* Only possible when MSI is the System clock source */
|
||
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
||
|
|
80010fe: 69bb ldr r3, [r7, #24]
|
||
|
|
8001100: 2b00 cmp r3, #0
|
||
|
|
8001102: d109 bne.n 8001118 <HAL_RCC_OscConfig+0x120>
|
||
|
|
{
|
||
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
||
|
|
8001104: 687b ldr r3, [r7, #4]
|
||
|
|
8001106: 6a1b ldr r3, [r3, #32]
|
||
|
|
8001108: 4618 mov r0, r3
|
||
|
|
800110a: f000 fd15 bl 8001b38 <RCC_SetFlashLatencyFromMSIRange>
|
||
|
|
800110e: 4603 mov r3, r0
|
||
|
|
8001110: 2b00 cmp r3, #0
|
||
|
|
8001112: d001 beq.n 8001118 <HAL_RCC_OscConfig+0x120>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001114: 2301 movs r3, #1
|
||
|
|
8001116: e343 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Update the SystemCoreClock global variable */
|
||
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
||
|
|
8001118: f000 fc4a bl 80019b0 <HAL_RCC_GetSysClockFreq>
|
||
|
|
800111c: 4602 mov r2, r0
|
||
|
|
800111e: 4b52 ldr r3, [pc, #328] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001120: 689b ldr r3, [r3, #8]
|
||
|
|
8001122: 091b lsrs r3, r3, #4
|
||
|
|
8001124: f003 030f and.w r3, r3, #15
|
||
|
|
8001128: 4950 ldr r1, [pc, #320] ; (800126c <HAL_RCC_OscConfig+0x274>)
|
||
|
|
800112a: 5ccb ldrb r3, [r1, r3]
|
||
|
|
800112c: f003 031f and.w r3, r3, #31
|
||
|
|
8001130: fa22 f303 lsr.w r3, r2, r3
|
||
|
|
8001134: 4a4e ldr r2, [pc, #312] ; (8001270 <HAL_RCC_OscConfig+0x278>)
|
||
|
|
8001136: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Configure the source of time base considering new system clocks settings*/
|
||
|
|
status = HAL_InitTick(uwTickPrio);
|
||
|
|
8001138: 4b4e ldr r3, [pc, #312] ; (8001274 <HAL_RCC_OscConfig+0x27c>)
|
||
|
|
800113a: 681b ldr r3, [r3, #0]
|
||
|
|
800113c: 4618 mov r0, r3
|
||
|
|
800113e: f7ff fbf3 bl 8000928 <HAL_InitTick>
|
||
|
|
8001142: 4603 mov r3, r0
|
||
|
|
8001144: 73fb strb r3, [r7, #15]
|
||
|
|
if(status != HAL_OK)
|
||
|
|
8001146: 7bfb ldrb r3, [r7, #15]
|
||
|
|
8001148: 2b00 cmp r3, #0
|
||
|
|
800114a: d052 beq.n 80011f2 <HAL_RCC_OscConfig+0x1fa>
|
||
|
|
{
|
||
|
|
return status;
|
||
|
|
800114c: 7bfb ldrb r3, [r7, #15]
|
||
|
|
800114e: e327 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Check the MSI State */
|
||
|
|
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
||
|
|
8001150: 687b ldr r3, [r7, #4]
|
||
|
|
8001152: 699b ldr r3, [r3, #24]
|
||
|
|
8001154: 2b00 cmp r3, #0
|
||
|
|
8001156: d032 beq.n 80011be <HAL_RCC_OscConfig+0x1c6>
|
||
|
|
{
|
||
|
|
/* Enable the Internal High Speed oscillator (MSI). */
|
||
|
|
__HAL_RCC_MSI_ENABLE();
|
||
|
|
8001158: 4b43 ldr r3, [pc, #268] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800115a: 681b ldr r3, [r3, #0]
|
||
|
|
800115c: 4a42 ldr r2, [pc, #264] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800115e: f043 0301 orr.w r3, r3, #1
|
||
|
|
8001162: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Get timeout */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001164: f7ff fc30 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001168: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till MSI is ready */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
||
|
|
800116a: e008 b.n 800117e <HAL_RCC_OscConfig+0x186>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
||
|
|
800116c: f7ff fc2c bl 80009c8 <HAL_GetTick>
|
||
|
|
8001170: 4602 mov r2, r0
|
||
|
|
8001172: 693b ldr r3, [r7, #16]
|
||
|
|
8001174: 1ad3 subs r3, r2, r3
|
||
|
|
8001176: 2b02 cmp r3, #2
|
||
|
|
8001178: d901 bls.n 800117e <HAL_RCC_OscConfig+0x186>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
800117a: 2303 movs r3, #3
|
||
|
|
800117c: e310 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
||
|
|
800117e: 4b3a ldr r3, [pc, #232] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001180: 681b ldr r3, [r3, #0]
|
||
|
|
8001182: f003 0302 and.w r3, r3, #2
|
||
|
|
8001186: 2b00 cmp r3, #0
|
||
|
|
8001188: d0f0 beq.n 800116c <HAL_RCC_OscConfig+0x174>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
||
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
||
|
|
800118a: 4b37 ldr r3, [pc, #220] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800118c: 681b ldr r3, [r3, #0]
|
||
|
|
800118e: 4a36 ldr r2, [pc, #216] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001190: f043 0308 orr.w r3, r3, #8
|
||
|
|
8001194: 6013 str r3, [r2, #0]
|
||
|
|
8001196: 4b34 ldr r3, [pc, #208] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001198: 681b ldr r3, [r3, #0]
|
||
|
|
800119a: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
||
|
|
800119e: 687b ldr r3, [r7, #4]
|
||
|
|
80011a0: 6a1b ldr r3, [r3, #32]
|
||
|
|
80011a2: 4931 ldr r1, [pc, #196] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80011a4: 4313 orrs r3, r2
|
||
|
|
80011a6: 600b str r3, [r1, #0]
|
||
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
||
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
||
|
|
80011a8: 4b2f ldr r3, [pc, #188] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80011aa: 685b ldr r3, [r3, #4]
|
||
|
|
80011ac: f423 427f bic.w r2, r3, #65280 ; 0xff00
|
||
|
|
80011b0: 687b ldr r3, [r7, #4]
|
||
|
|
80011b2: 69db ldr r3, [r3, #28]
|
||
|
|
80011b4: 021b lsls r3, r3, #8
|
||
|
|
80011b6: 492c ldr r1, [pc, #176] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80011b8: 4313 orrs r3, r2
|
||
|
|
80011ba: 604b str r3, [r1, #4]
|
||
|
|
80011bc: e01a b.n 80011f4 <HAL_RCC_OscConfig+0x1fc>
|
||
|
|
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable the Internal High Speed oscillator (MSI). */
|
||
|
|
__HAL_RCC_MSI_DISABLE();
|
||
|
|
80011be: 4b2a ldr r3, [pc, #168] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80011c0: 681b ldr r3, [r3, #0]
|
||
|
|
80011c2: 4a29 ldr r2, [pc, #164] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80011c4: f023 0301 bic.w r3, r3, #1
|
||
|
|
80011c8: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Get timeout */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80011ca: f7ff fbfd bl 80009c8 <HAL_GetTick>
|
||
|
|
80011ce: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till MSI is ready */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
||
|
|
80011d0: e008 b.n 80011e4 <HAL_RCC_OscConfig+0x1ec>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
||
|
|
80011d2: f7ff fbf9 bl 80009c8 <HAL_GetTick>
|
||
|
|
80011d6: 4602 mov r2, r0
|
||
|
|
80011d8: 693b ldr r3, [r7, #16]
|
||
|
|
80011da: 1ad3 subs r3, r2, r3
|
||
|
|
80011dc: 2b02 cmp r3, #2
|
||
|
|
80011de: d901 bls.n 80011e4 <HAL_RCC_OscConfig+0x1ec>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80011e0: 2303 movs r3, #3
|
||
|
|
80011e2: e2dd b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
||
|
|
80011e4: 4b20 ldr r3, [pc, #128] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
80011e6: 681b ldr r3, [r3, #0]
|
||
|
|
80011e8: f003 0302 and.w r3, r3, #2
|
||
|
|
80011ec: 2b00 cmp r3, #0
|
||
|
|
80011ee: d1f0 bne.n 80011d2 <HAL_RCC_OscConfig+0x1da>
|
||
|
|
80011f0: e000 b.n 80011f4 <HAL_RCC_OscConfig+0x1fc>
|
||
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
||
|
|
80011f2: bf00 nop
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
||
|
|
80011f4: 687b ldr r3, [r7, #4]
|
||
|
|
80011f6: 681b ldr r3, [r3, #0]
|
||
|
|
80011f8: f003 0301 and.w r3, r3, #1
|
||
|
|
80011fc: 2b00 cmp r3, #0
|
||
|
|
80011fe: d074 beq.n 80012ea <HAL_RCC_OscConfig+0x2f2>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
||
|
|
|
||
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
||
|
|
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
|
||
|
|
8001200: 69bb ldr r3, [r7, #24]
|
||
|
|
8001202: 2b08 cmp r3, #8
|
||
|
|
8001204: d005 beq.n 8001212 <HAL_RCC_OscConfig+0x21a>
|
||
|
|
8001206: 69bb ldr r3, [r7, #24]
|
||
|
|
8001208: 2b0c cmp r3, #12
|
||
|
|
800120a: d10e bne.n 800122a <HAL_RCC_OscConfig+0x232>
|
||
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
|
||
|
|
800120c: 697b ldr r3, [r7, #20]
|
||
|
|
800120e: 2b03 cmp r3, #3
|
||
|
|
8001210: d10b bne.n 800122a <HAL_RCC_OscConfig+0x232>
|
||
|
|
{
|
||
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
||
|
|
8001212: 4b15 ldr r3, [pc, #84] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001214: 681b ldr r3, [r3, #0]
|
||
|
|
8001216: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
||
|
|
800121a: 2b00 cmp r3, #0
|
||
|
|
800121c: d064 beq.n 80012e8 <HAL_RCC_OscConfig+0x2f0>
|
||
|
|
800121e: 687b ldr r3, [r7, #4]
|
||
|
|
8001220: 685b ldr r3, [r3, #4]
|
||
|
|
8001222: 2b00 cmp r3, #0
|
||
|
|
8001224: d160 bne.n 80012e8 <HAL_RCC_OscConfig+0x2f0>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001226: 2301 movs r3, #1
|
||
|
|
8001228: e2ba b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
||
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
||
|
|
800122a: 687b ldr r3, [r7, #4]
|
||
|
|
800122c: 685b ldr r3, [r3, #4]
|
||
|
|
800122e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
||
|
|
8001232: d106 bne.n 8001242 <HAL_RCC_OscConfig+0x24a>
|
||
|
|
8001234: 4b0c ldr r3, [pc, #48] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001236: 681b ldr r3, [r3, #0]
|
||
|
|
8001238: 4a0b ldr r2, [pc, #44] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800123a: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
||
|
|
800123e: 6013 str r3, [r2, #0]
|
||
|
|
8001240: e026 b.n 8001290 <HAL_RCC_OscConfig+0x298>
|
||
|
|
8001242: 687b ldr r3, [r7, #4]
|
||
|
|
8001244: 685b ldr r3, [r3, #4]
|
||
|
|
8001246: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
|
||
|
|
800124a: d115 bne.n 8001278 <HAL_RCC_OscConfig+0x280>
|
||
|
|
800124c: 4b06 ldr r3, [pc, #24] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800124e: 681b ldr r3, [r3, #0]
|
||
|
|
8001250: 4a05 ldr r2, [pc, #20] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
8001252: f443 2380 orr.w r3, r3, #262144 ; 0x40000
|
||
|
|
8001256: 6013 str r3, [r2, #0]
|
||
|
|
8001258: 4b03 ldr r3, [pc, #12] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800125a: 681b ldr r3, [r3, #0]
|
||
|
|
800125c: 4a02 ldr r2, [pc, #8] ; (8001268 <HAL_RCC_OscConfig+0x270>)
|
||
|
|
800125e: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
||
|
|
8001262: 6013 str r3, [r2, #0]
|
||
|
|
8001264: e014 b.n 8001290 <HAL_RCC_OscConfig+0x298>
|
||
|
|
8001266: bf00 nop
|
||
|
|
8001268: 40021000 .word 0x40021000
|
||
|
|
800126c: 08005d28 .word 0x08005d28
|
||
|
|
8001270: 20000000 .word 0x20000000
|
||
|
|
8001274: 20000004 .word 0x20000004
|
||
|
|
8001278: 4ba0 ldr r3, [pc, #640] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
800127a: 681b ldr r3, [r3, #0]
|
||
|
|
800127c: 4a9f ldr r2, [pc, #636] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
800127e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
||
|
|
8001282: 6013 str r3, [r2, #0]
|
||
|
|
8001284: 4b9d ldr r3, [pc, #628] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001286: 681b ldr r3, [r3, #0]
|
||
|
|
8001288: 4a9c ldr r2, [pc, #624] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
800128a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
||
|
|
800128e: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Check the HSE State */
|
||
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
||
|
|
8001290: 687b ldr r3, [r7, #4]
|
||
|
|
8001292: 685b ldr r3, [r3, #4]
|
||
|
|
8001294: 2b00 cmp r3, #0
|
||
|
|
8001296: d013 beq.n 80012c0 <HAL_RCC_OscConfig+0x2c8>
|
||
|
|
{
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001298: f7ff fb96 bl 80009c8 <HAL_GetTick>
|
||
|
|
800129c: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till HSE is ready */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
||
|
|
800129e: e008 b.n 80012b2 <HAL_RCC_OscConfig+0x2ba>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
||
|
|
80012a0: f7ff fb92 bl 80009c8 <HAL_GetTick>
|
||
|
|
80012a4: 4602 mov r2, r0
|
||
|
|
80012a6: 693b ldr r3, [r7, #16]
|
||
|
|
80012a8: 1ad3 subs r3, r2, r3
|
||
|
|
80012aa: 2b64 cmp r3, #100 ; 0x64
|
||
|
|
80012ac: d901 bls.n 80012b2 <HAL_RCC_OscConfig+0x2ba>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80012ae: 2303 movs r3, #3
|
||
|
|
80012b0: e276 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
||
|
|
80012b2: 4b92 ldr r3, [pc, #584] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80012b4: 681b ldr r3, [r3, #0]
|
||
|
|
80012b6: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
||
|
|
80012ba: 2b00 cmp r3, #0
|
||
|
|
80012bc: d0f0 beq.n 80012a0 <HAL_RCC_OscConfig+0x2a8>
|
||
|
|
80012be: e014 b.n 80012ea <HAL_RCC_OscConfig+0x2f2>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80012c0: f7ff fb82 bl 80009c8 <HAL_GetTick>
|
||
|
|
80012c4: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till HSE is disabled */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
||
|
|
80012c6: e008 b.n 80012da <HAL_RCC_OscConfig+0x2e2>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
||
|
|
80012c8: f7ff fb7e bl 80009c8 <HAL_GetTick>
|
||
|
|
80012cc: 4602 mov r2, r0
|
||
|
|
80012ce: 693b ldr r3, [r7, #16]
|
||
|
|
80012d0: 1ad3 subs r3, r2, r3
|
||
|
|
80012d2: 2b64 cmp r3, #100 ; 0x64
|
||
|
|
80012d4: d901 bls.n 80012da <HAL_RCC_OscConfig+0x2e2>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80012d6: 2303 movs r3, #3
|
||
|
|
80012d8: e262 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
||
|
|
80012da: 4b88 ldr r3, [pc, #544] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80012dc: 681b ldr r3, [r3, #0]
|
||
|
|
80012de: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
||
|
|
80012e2: 2b00 cmp r3, #0
|
||
|
|
80012e4: d1f0 bne.n 80012c8 <HAL_RCC_OscConfig+0x2d0>
|
||
|
|
80012e6: e000 b.n 80012ea <HAL_RCC_OscConfig+0x2f2>
|
||
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
||
|
|
80012e8: bf00 nop
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
||
|
|
80012ea: 687b ldr r3, [r7, #4]
|
||
|
|
80012ec: 681b ldr r3, [r3, #0]
|
||
|
|
80012ee: f003 0302 and.w r3, r3, #2
|
||
|
|
80012f2: 2b00 cmp r3, #0
|
||
|
|
80012f4: d060 beq.n 80013b8 <HAL_RCC_OscConfig+0x3c0>
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
||
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
||
|
|
|
||
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
||
|
|
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
|
||
|
|
80012f6: 69bb ldr r3, [r7, #24]
|
||
|
|
80012f8: 2b04 cmp r3, #4
|
||
|
|
80012fa: d005 beq.n 8001308 <HAL_RCC_OscConfig+0x310>
|
||
|
|
80012fc: 69bb ldr r3, [r7, #24]
|
||
|
|
80012fe: 2b0c cmp r3, #12
|
||
|
|
8001300: d119 bne.n 8001336 <HAL_RCC_OscConfig+0x33e>
|
||
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
|
||
|
|
8001302: 697b ldr r3, [r7, #20]
|
||
|
|
8001304: 2b02 cmp r3, #2
|
||
|
|
8001306: d116 bne.n 8001336 <HAL_RCC_OscConfig+0x33e>
|
||
|
|
{
|
||
|
|
/* When HSI is used as system clock it will not be disabled */
|
||
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
||
|
|
8001308: 4b7c ldr r3, [pc, #496] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
800130a: 681b ldr r3, [r3, #0]
|
||
|
|
800130c: f403 6380 and.w r3, r3, #1024 ; 0x400
|
||
|
|
8001310: 2b00 cmp r3, #0
|
||
|
|
8001312: d005 beq.n 8001320 <HAL_RCC_OscConfig+0x328>
|
||
|
|
8001314: 687b ldr r3, [r7, #4]
|
||
|
|
8001316: 68db ldr r3, [r3, #12]
|
||
|
|
8001318: 2b00 cmp r3, #0
|
||
|
|
800131a: d101 bne.n 8001320 <HAL_RCC_OscConfig+0x328>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
800131c: 2301 movs r3, #1
|
||
|
|
800131e: e23f b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
}
|
||
|
|
/* Otherwise, just the calibration is allowed */
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
||
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
||
|
|
8001320: 4b76 ldr r3, [pc, #472] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001322: 685b ldr r3, [r3, #4]
|
||
|
|
8001324: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000
|
||
|
|
8001328: 687b ldr r3, [r7, #4]
|
||
|
|
800132a: 691b ldr r3, [r3, #16]
|
||
|
|
800132c: 061b lsls r3, r3, #24
|
||
|
|
800132e: 4973 ldr r1, [pc, #460] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001330: 4313 orrs r3, r2
|
||
|
|
8001332: 604b str r3, [r1, #4]
|
||
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
||
|
|
8001334: e040 b.n 80013b8 <HAL_RCC_OscConfig+0x3c0>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Check the HSI State */
|
||
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
||
|
|
8001336: 687b ldr r3, [r7, #4]
|
||
|
|
8001338: 68db ldr r3, [r3, #12]
|
||
|
|
800133a: 2b00 cmp r3, #0
|
||
|
|
800133c: d023 beq.n 8001386 <HAL_RCC_OscConfig+0x38e>
|
||
|
|
{
|
||
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
||
|
|
__HAL_RCC_HSI_ENABLE();
|
||
|
|
800133e: 4b6f ldr r3, [pc, #444] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001340: 681b ldr r3, [r3, #0]
|
||
|
|
8001342: 4a6e ldr r2, [pc, #440] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001344: f443 7380 orr.w r3, r3, #256 ; 0x100
|
||
|
|
8001348: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
800134a: f7ff fb3d bl 80009c8 <HAL_GetTick>
|
||
|
|
800134e: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till HSI is ready */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
||
|
|
8001350: e008 b.n 8001364 <HAL_RCC_OscConfig+0x36c>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
||
|
|
8001352: f7ff fb39 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001356: 4602 mov r2, r0
|
||
|
|
8001358: 693b ldr r3, [r7, #16]
|
||
|
|
800135a: 1ad3 subs r3, r2, r3
|
||
|
|
800135c: 2b02 cmp r3, #2
|
||
|
|
800135e: d901 bls.n 8001364 <HAL_RCC_OscConfig+0x36c>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001360: 2303 movs r3, #3
|
||
|
|
8001362: e21d b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
||
|
|
8001364: 4b65 ldr r3, [pc, #404] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001366: 681b ldr r3, [r3, #0]
|
||
|
|
8001368: f403 6380 and.w r3, r3, #1024 ; 0x400
|
||
|
|
800136c: 2b00 cmp r3, #0
|
||
|
|
800136e: d0f0 beq.n 8001352 <HAL_RCC_OscConfig+0x35a>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
||
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
||
|
|
8001370: 4b62 ldr r3, [pc, #392] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001372: 685b ldr r3, [r3, #4]
|
||
|
|
8001374: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000
|
||
|
|
8001378: 687b ldr r3, [r7, #4]
|
||
|
|
800137a: 691b ldr r3, [r3, #16]
|
||
|
|
800137c: 061b lsls r3, r3, #24
|
||
|
|
800137e: 495f ldr r1, [pc, #380] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001380: 4313 orrs r3, r2
|
||
|
|
8001382: 604b str r3, [r1, #4]
|
||
|
|
8001384: e018 b.n 80013b8 <HAL_RCC_OscConfig+0x3c0>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
||
|
|
__HAL_RCC_HSI_DISABLE();
|
||
|
|
8001386: 4b5d ldr r3, [pc, #372] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001388: 681b ldr r3, [r3, #0]
|
||
|
|
800138a: 4a5c ldr r2, [pc, #368] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
800138c: f423 7380 bic.w r3, r3, #256 ; 0x100
|
||
|
|
8001390: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001392: f7ff fb19 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001396: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till HSI is disabled */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
||
|
|
8001398: e008 b.n 80013ac <HAL_RCC_OscConfig+0x3b4>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
||
|
|
800139a: f7ff fb15 bl 80009c8 <HAL_GetTick>
|
||
|
|
800139e: 4602 mov r2, r0
|
||
|
|
80013a0: 693b ldr r3, [r7, #16]
|
||
|
|
80013a2: 1ad3 subs r3, r2, r3
|
||
|
|
80013a4: 2b02 cmp r3, #2
|
||
|
|
80013a6: d901 bls.n 80013ac <HAL_RCC_OscConfig+0x3b4>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80013a8: 2303 movs r3, #3
|
||
|
|
80013aa: e1f9 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
||
|
|
80013ac: 4b53 ldr r3, [pc, #332] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80013ae: 681b ldr r3, [r3, #0]
|
||
|
|
80013b0: f403 6380 and.w r3, r3, #1024 ; 0x400
|
||
|
|
80013b4: 2b00 cmp r3, #0
|
||
|
|
80013b6: d1f0 bne.n 800139a <HAL_RCC_OscConfig+0x3a2>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
||
|
|
80013b8: 687b ldr r3, [r7, #4]
|
||
|
|
80013ba: 681b ldr r3, [r3, #0]
|
||
|
|
80013bc: f003 0308 and.w r3, r3, #8
|
||
|
|
80013c0: 2b00 cmp r3, #0
|
||
|
|
80013c2: d03c beq.n 800143e <HAL_RCC_OscConfig+0x446>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
||
|
|
|
||
|
|
/* Check the LSI State */
|
||
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
||
|
|
80013c4: 687b ldr r3, [r7, #4]
|
||
|
|
80013c6: 695b ldr r3, [r3, #20]
|
||
|
|
80013c8: 2b00 cmp r3, #0
|
||
|
|
80013ca: d01c beq.n 8001406 <HAL_RCC_OscConfig+0x40e>
|
||
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
|
||
|
|
}
|
||
|
|
#endif /* RCC_CSR_LSIPREDIV */
|
||
|
|
|
||
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
||
|
|
__HAL_RCC_LSI_ENABLE();
|
||
|
|
80013cc: 4b4b ldr r3, [pc, #300] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80013ce: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
||
|
|
80013d2: 4a4a ldr r2, [pc, #296] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80013d4: f043 0301 orr.w r3, r3, #1
|
||
|
|
80013d8: f8c2 3094 str.w r3, [r2, #148] ; 0x94
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80013dc: f7ff faf4 bl 80009c8 <HAL_GetTick>
|
||
|
|
80013e0: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till LSI is ready */
|
||
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
||
|
|
80013e2: e008 b.n 80013f6 <HAL_RCC_OscConfig+0x3fe>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
||
|
|
80013e4: f7ff faf0 bl 80009c8 <HAL_GetTick>
|
||
|
|
80013e8: 4602 mov r2, r0
|
||
|
|
80013ea: 693b ldr r3, [r7, #16]
|
||
|
|
80013ec: 1ad3 subs r3, r2, r3
|
||
|
|
80013ee: 2b02 cmp r3, #2
|
||
|
|
80013f0: d901 bls.n 80013f6 <HAL_RCC_OscConfig+0x3fe>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80013f2: 2303 movs r3, #3
|
||
|
|
80013f4: e1d4 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
||
|
|
80013f6: 4b41 ldr r3, [pc, #260] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80013f8: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
||
|
|
80013fc: f003 0302 and.w r3, r3, #2
|
||
|
|
8001400: 2b00 cmp r3, #0
|
||
|
|
8001402: d0ef beq.n 80013e4 <HAL_RCC_OscConfig+0x3ec>
|
||
|
|
8001404: e01b b.n 800143e <HAL_RCC_OscConfig+0x446>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
||
|
|
__HAL_RCC_LSI_DISABLE();
|
||
|
|
8001406: 4b3d ldr r3, [pc, #244] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001408: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
||
|
|
800140c: 4a3b ldr r2, [pc, #236] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
800140e: f023 0301 bic.w r3, r3, #1
|
||
|
|
8001412: f8c2 3094 str.w r3, [r2, #148] ; 0x94
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001416: f7ff fad7 bl 80009c8 <HAL_GetTick>
|
||
|
|
800141a: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till LSI is disabled */
|
||
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
||
|
|
800141c: e008 b.n 8001430 <HAL_RCC_OscConfig+0x438>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
||
|
|
800141e: f7ff fad3 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001422: 4602 mov r2, r0
|
||
|
|
8001424: 693b ldr r3, [r7, #16]
|
||
|
|
8001426: 1ad3 subs r3, r2, r3
|
||
|
|
8001428: 2b02 cmp r3, #2
|
||
|
|
800142a: d901 bls.n 8001430 <HAL_RCC_OscConfig+0x438>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
800142c: 2303 movs r3, #3
|
||
|
|
800142e: e1b7 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
||
|
|
8001430: 4b32 ldr r3, [pc, #200] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001432: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
||
|
|
8001436: f003 0302 and.w r3, r3, #2
|
||
|
|
800143a: 2b00 cmp r3, #0
|
||
|
|
800143c: d1ef bne.n 800141e <HAL_RCC_OscConfig+0x426>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
||
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
||
|
|
800143e: 687b ldr r3, [r7, #4]
|
||
|
|
8001440: 681b ldr r3, [r3, #0]
|
||
|
|
8001442: f003 0304 and.w r3, r3, #4
|
||
|
|
8001446: 2b00 cmp r3, #0
|
||
|
|
8001448: f000 80a6 beq.w 8001598 <HAL_RCC_OscConfig+0x5a0>
|
||
|
|
{
|
||
|
|
FlagStatus pwrclkchanged = RESET;
|
||
|
|
800144c: 2300 movs r3, #0
|
||
|
|
800144e: 77fb strb r3, [r7, #31]
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
||
|
|
|
||
|
|
/* Update LSE configuration in Backup Domain control register */
|
||
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
||
|
|
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
|
||
|
|
8001450: 4b2a ldr r3, [pc, #168] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001452: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001454: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001458: 2b00 cmp r3, #0
|
||
|
|
800145a: d10d bne.n 8001478 <HAL_RCC_OscConfig+0x480>
|
||
|
|
{
|
||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||
|
|
800145c: 4b27 ldr r3, [pc, #156] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
800145e: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001460: 4a26 ldr r2, [pc, #152] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
8001462: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001466: 6593 str r3, [r2, #88] ; 0x58
|
||
|
|
8001468: 4b24 ldr r3, [pc, #144] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
800146a: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
800146c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001470: 60bb str r3, [r7, #8]
|
||
|
|
8001472: 68bb ldr r3, [r7, #8]
|
||
|
|
pwrclkchanged = SET;
|
||
|
|
8001474: 2301 movs r3, #1
|
||
|
|
8001476: 77fb strb r3, [r7, #31]
|
||
|
|
}
|
||
|
|
|
||
|
|
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
||
|
|
8001478: 4b21 ldr r3, [pc, #132] ; (8001500 <HAL_RCC_OscConfig+0x508>)
|
||
|
|
800147a: 681b ldr r3, [r3, #0]
|
||
|
|
800147c: f403 7380 and.w r3, r3, #256 ; 0x100
|
||
|
|
8001480: 2b00 cmp r3, #0
|
||
|
|
8001482: d118 bne.n 80014b6 <HAL_RCC_OscConfig+0x4be>
|
||
|
|
{
|
||
|
|
/* Enable write access to Backup domain */
|
||
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
||
|
|
8001484: 4b1e ldr r3, [pc, #120] ; (8001500 <HAL_RCC_OscConfig+0x508>)
|
||
|
|
8001486: 681b ldr r3, [r3, #0]
|
||
|
|
8001488: 4a1d ldr r2, [pc, #116] ; (8001500 <HAL_RCC_OscConfig+0x508>)
|
||
|
|
800148a: f443 7380 orr.w r3, r3, #256 ; 0x100
|
||
|
|
800148e: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Wait for Backup domain Write protection disable */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001490: f7ff fa9a bl 80009c8 <HAL_GetTick>
|
||
|
|
8001494: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
||
|
|
8001496: e008 b.n 80014aa <HAL_RCC_OscConfig+0x4b2>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
||
|
|
8001498: f7ff fa96 bl 80009c8 <HAL_GetTick>
|
||
|
|
800149c: 4602 mov r2, r0
|
||
|
|
800149e: 693b ldr r3, [r7, #16]
|
||
|
|
80014a0: 1ad3 subs r3, r2, r3
|
||
|
|
80014a2: 2b02 cmp r3, #2
|
||
|
|
80014a4: d901 bls.n 80014aa <HAL_RCC_OscConfig+0x4b2>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80014a6: 2303 movs r3, #3
|
||
|
|
80014a8: e17a b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
||
|
|
80014aa: 4b15 ldr r3, [pc, #84] ; (8001500 <HAL_RCC_OscConfig+0x508>)
|
||
|
|
80014ac: 681b ldr r3, [r3, #0]
|
||
|
|
80014ae: f403 7380 and.w r3, r3, #256 ; 0x100
|
||
|
|
80014b2: 2b00 cmp r3, #0
|
||
|
|
80014b4: d0f0 beq.n 8001498 <HAL_RCC_OscConfig+0x4a0>
|
||
|
|
{
|
||
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
||
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
||
|
|
80014b6: 687b ldr r3, [r7, #4]
|
||
|
|
80014b8: 689b ldr r3, [r3, #8]
|
||
|
|
80014ba: 2b01 cmp r3, #1
|
||
|
|
80014bc: d108 bne.n 80014d0 <HAL_RCC_OscConfig+0x4d8>
|
||
|
|
80014be: 4b0f ldr r3, [pc, #60] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80014c0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
80014c4: 4a0d ldr r2, [pc, #52] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80014c6: f043 0301 orr.w r3, r3, #1
|
||
|
|
80014ca: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
||
|
|
80014ce: e029 b.n 8001524 <HAL_RCC_OscConfig+0x52c>
|
||
|
|
80014d0: 687b ldr r3, [r7, #4]
|
||
|
|
80014d2: 689b ldr r3, [r3, #8]
|
||
|
|
80014d4: 2b05 cmp r3, #5
|
||
|
|
80014d6: d115 bne.n 8001504 <HAL_RCC_OscConfig+0x50c>
|
||
|
|
80014d8: 4b08 ldr r3, [pc, #32] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80014da: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
80014de: 4a07 ldr r2, [pc, #28] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80014e0: f043 0304 orr.w r3, r3, #4
|
||
|
|
80014e4: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
||
|
|
80014e8: 4b04 ldr r3, [pc, #16] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80014ea: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
80014ee: 4a03 ldr r2, [pc, #12] ; (80014fc <HAL_RCC_OscConfig+0x504>)
|
||
|
|
80014f0: f043 0301 orr.w r3, r3, #1
|
||
|
|
80014f4: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
||
|
|
80014f8: e014 b.n 8001524 <HAL_RCC_OscConfig+0x52c>
|
||
|
|
80014fa: bf00 nop
|
||
|
|
80014fc: 40021000 .word 0x40021000
|
||
|
|
8001500: 40007000 .word 0x40007000
|
||
|
|
8001504: 4b9c ldr r3, [pc, #624] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001506: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
800150a: 4a9b ldr r2, [pc, #620] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800150c: f023 0301 bic.w r3, r3, #1
|
||
|
|
8001510: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
||
|
|
8001514: 4b98 ldr r3, [pc, #608] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001516: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
800151a: 4a97 ldr r2, [pc, #604] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800151c: f023 0304 bic.w r3, r3, #4
|
||
|
|
8001520: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
||
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
||
|
|
|
||
|
|
/* Check the LSE State */
|
||
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
||
|
|
8001524: 687b ldr r3, [r7, #4]
|
||
|
|
8001526: 689b ldr r3, [r3, #8]
|
||
|
|
8001528: 2b00 cmp r3, #0
|
||
|
|
800152a: d016 beq.n 800155a <HAL_RCC_OscConfig+0x562>
|
||
|
|
{
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
800152c: f7ff fa4c bl 80009c8 <HAL_GetTick>
|
||
|
|
8001530: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till LSE is ready */
|
||
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
||
|
|
8001532: e00a b.n 800154a <HAL_RCC_OscConfig+0x552>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
||
|
|
8001534: f7ff fa48 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001538: 4602 mov r2, r0
|
||
|
|
800153a: 693b ldr r3, [r7, #16]
|
||
|
|
800153c: 1ad3 subs r3, r2, r3
|
||
|
|
800153e: f241 3288 movw r2, #5000 ; 0x1388
|
||
|
|
8001542: 4293 cmp r3, r2
|
||
|
|
8001544: d901 bls.n 800154a <HAL_RCC_OscConfig+0x552>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001546: 2303 movs r3, #3
|
||
|
|
8001548: e12a b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
||
|
|
800154a: 4b8b ldr r3, [pc, #556] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800154c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
8001550: f003 0302 and.w r3, r3, #2
|
||
|
|
8001554: 2b00 cmp r3, #0
|
||
|
|
8001556: d0ed beq.n 8001534 <HAL_RCC_OscConfig+0x53c>
|
||
|
|
8001558: e015 b.n 8001586 <HAL_RCC_OscConfig+0x58e>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
800155a: f7ff fa35 bl 80009c8 <HAL_GetTick>
|
||
|
|
800155e: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till LSE is disabled */
|
||
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
||
|
|
8001560: e00a b.n 8001578 <HAL_RCC_OscConfig+0x580>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
||
|
|
8001562: f7ff fa31 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001566: 4602 mov r2, r0
|
||
|
|
8001568: 693b ldr r3, [r7, #16]
|
||
|
|
800156a: 1ad3 subs r3, r2, r3
|
||
|
|
800156c: f241 3288 movw r2, #5000 ; 0x1388
|
||
|
|
8001570: 4293 cmp r3, r2
|
||
|
|
8001572: d901 bls.n 8001578 <HAL_RCC_OscConfig+0x580>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001574: 2303 movs r3, #3
|
||
|
|
8001576: e113 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
||
|
|
8001578: 4b7f ldr r3, [pc, #508] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800157a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
800157e: f003 0302 and.w r3, r3, #2
|
||
|
|
8001582: 2b00 cmp r3, #0
|
||
|
|
8001584: d1ed bne.n 8001562 <HAL_RCC_OscConfig+0x56a>
|
||
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
|
||
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Restore clock configuration if changed */
|
||
|
|
if(pwrclkchanged == SET)
|
||
|
|
8001586: 7ffb ldrb r3, [r7, #31]
|
||
|
|
8001588: 2b01 cmp r3, #1
|
||
|
|
800158a: d105 bne.n 8001598 <HAL_RCC_OscConfig+0x5a0>
|
||
|
|
{
|
||
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
||
|
|
800158c: 4b7a ldr r3, [pc, #488] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800158e: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001590: 4a79 ldr r2, [pc, #484] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001592: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001596: 6593 str r3, [r2, #88] ; 0x58
|
||
|
|
#endif /* RCC_HSI48_SUPPORT */
|
||
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
||
|
|
|
||
|
|
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
||
|
|
8001598: 687b ldr r3, [r7, #4]
|
||
|
|
800159a: 6a9b ldr r3, [r3, #40] ; 0x28
|
||
|
|
800159c: 2b00 cmp r3, #0
|
||
|
|
800159e: f000 80fe beq.w 800179e <HAL_RCC_OscConfig+0x7a6>
|
||
|
|
{
|
||
|
|
/* PLL On ? */
|
||
|
|
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
||
|
|
80015a2: 687b ldr r3, [r7, #4]
|
||
|
|
80015a4: 6a9b ldr r3, [r3, #40] ; 0x28
|
||
|
|
80015a6: 2b02 cmp r3, #2
|
||
|
|
80015a8: f040 80d0 bne.w 800174c <HAL_RCC_OscConfig+0x754>
|
||
|
|
#endif /* RCC_PLLP_SUPPORT */
|
||
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
||
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
||
|
|
|
||
|
|
/* Do nothing if PLL configuration is the unchanged */
|
||
|
|
pll_config = RCC->PLLCFGR;
|
||
|
|
80015ac: 4b72 ldr r3, [pc, #456] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
80015ae: 68db ldr r3, [r3, #12]
|
||
|
|
80015b0: 617b str r3, [r7, #20]
|
||
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||
|
|
80015b2: 697b ldr r3, [r7, #20]
|
||
|
|
80015b4: f003 0203 and.w r2, r3, #3
|
||
|
|
80015b8: 687b ldr r3, [r7, #4]
|
||
|
|
80015ba: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
80015bc: 429a cmp r2, r3
|
||
|
|
80015be: d130 bne.n 8001622 <HAL_RCC_OscConfig+0x62a>
|
||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
||
|
|
80015c0: 697b ldr r3, [r7, #20]
|
||
|
|
80015c2: f003 0270 and.w r2, r3, #112 ; 0x70
|
||
|
|
80015c6: 687b ldr r3, [r7, #4]
|
||
|
|
80015c8: 6b1b ldr r3, [r3, #48] ; 0x30
|
||
|
|
80015ca: 3b01 subs r3, #1
|
||
|
|
80015cc: 011b lsls r3, r3, #4
|
||
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||
|
|
80015ce: 429a cmp r2, r3
|
||
|
|
80015d0: d127 bne.n 8001622 <HAL_RCC_OscConfig+0x62a>
|
||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
||
|
|
80015d2: 697b ldr r3, [r7, #20]
|
||
|
|
80015d4: f403 42fe and.w r2, r3, #32512 ; 0x7f00
|
||
|
|
80015d8: 687b ldr r3, [r7, #4]
|
||
|
|
80015da: 6b5b ldr r3, [r3, #52] ; 0x34
|
||
|
|
80015dc: 021b lsls r3, r3, #8
|
||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
||
|
|
80015de: 429a cmp r2, r3
|
||
|
|
80015e0: d11f bne.n 8001622 <HAL_RCC_OscConfig+0x62a>
|
||
|
|
#if defined(RCC_PLLP_SUPPORT)
|
||
|
|
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
|
||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
||
|
|
#else
|
||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
||
|
|
80015e2: 697b ldr r3, [r7, #20]
|
||
|
|
80015e4: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
||
|
|
80015e8: 687a ldr r2, [r7, #4]
|
||
|
|
80015ea: 6b92 ldr r2, [r2, #56] ; 0x38
|
||
|
|
80015ec: 2a07 cmp r2, #7
|
||
|
|
80015ee: bf14 ite ne
|
||
|
|
80015f0: 2201 movne r2, #1
|
||
|
|
80015f2: 2200 moveq r2, #0
|
||
|
|
80015f4: b2d2 uxtb r2, r2
|
||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
||
|
|
80015f6: 4293 cmp r3, r2
|
||
|
|
80015f8: d113 bne.n 8001622 <HAL_RCC_OscConfig+0x62a>
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
||
|
|
80015fa: 697b ldr r3, [r7, #20]
|
||
|
|
80015fc: f403 02c0 and.w r2, r3, #6291456 ; 0x600000
|
||
|
|
8001600: 687b ldr r3, [r7, #4]
|
||
|
|
8001602: 6bdb ldr r3, [r3, #60] ; 0x3c
|
||
|
|
8001604: 085b lsrs r3, r3, #1
|
||
|
|
8001606: 3b01 subs r3, #1
|
||
|
|
8001608: 055b lsls r3, r3, #21
|
||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
||
|
|
800160a: 429a cmp r2, r3
|
||
|
|
800160c: d109 bne.n 8001622 <HAL_RCC_OscConfig+0x62a>
|
||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
|
||
|
|
800160e: 697b ldr r3, [r7, #20]
|
||
|
|
8001610: f003 62c0 and.w r2, r3, #100663296 ; 0x6000000
|
||
|
|
8001614: 687b ldr r3, [r7, #4]
|
||
|
|
8001616: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8001618: 085b lsrs r3, r3, #1
|
||
|
|
800161a: 3b01 subs r3, #1
|
||
|
|
800161c: 065b lsls r3, r3, #25
|
||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
||
|
|
800161e: 429a cmp r2, r3
|
||
|
|
8001620: d06e beq.n 8001700 <HAL_RCC_OscConfig+0x708>
|
||
|
|
{
|
||
|
|
/* Check if the PLL is used as system clock or not */
|
||
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
||
|
|
8001622: 69bb ldr r3, [r7, #24]
|
||
|
|
8001624: 2b0c cmp r3, #12
|
||
|
|
8001626: d069 beq.n 80016fc <HAL_RCC_OscConfig+0x704>
|
||
|
|
{
|
||
|
|
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
|
||
|
|
/* Check if main PLL can be updated */
|
||
|
|
/* Not possible if the source is shared by other enabled PLLSAIx */
|
||
|
|
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
|
||
|
|
8001628: 4b53 ldr r3, [pc, #332] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800162a: 681b ldr r3, [r3, #0]
|
||
|
|
800162c: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
|
||
|
|
8001630: 2b00 cmp r3, #0
|
||
|
|
8001632: d105 bne.n 8001640 <HAL_RCC_OscConfig+0x648>
|
||
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
||
|
|
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
|
||
|
|
8001634: 4b50 ldr r3, [pc, #320] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001636: 681b ldr r3, [r3, #0]
|
||
|
|
8001638: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
800163c: 2b00 cmp r3, #0
|
||
|
|
800163e: d001 beq.n 8001644 <HAL_RCC_OscConfig+0x64c>
|
||
|
|
#endif
|
||
|
|
)
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001640: 2301 movs r3, #1
|
||
|
|
8001642: e0ad b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
|
||
|
|
{
|
||
|
|
/* Disable the main PLL. */
|
||
|
|
__HAL_RCC_PLL_DISABLE();
|
||
|
|
8001644: 4b4c ldr r3, [pc, #304] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001646: 681b ldr r3, [r3, #0]
|
||
|
|
8001648: 4a4b ldr r2, [pc, #300] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800164a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
||
|
|
800164e: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001650: f7ff f9ba bl 80009c8 <HAL_GetTick>
|
||
|
|
8001654: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till PLL is ready */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
||
|
|
8001656: e008 b.n 800166a <HAL_RCC_OscConfig+0x672>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
||
|
|
8001658: f7ff f9b6 bl 80009c8 <HAL_GetTick>
|
||
|
|
800165c: 4602 mov r2, r0
|
||
|
|
800165e: 693b ldr r3, [r7, #16]
|
||
|
|
8001660: 1ad3 subs r3, r2, r3
|
||
|
|
8001662: 2b02 cmp r3, #2
|
||
|
|
8001664: d901 bls.n 800166a <HAL_RCC_OscConfig+0x672>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001666: 2303 movs r3, #3
|
||
|
|
8001668: e09a b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
||
|
|
800166a: 4b43 ldr r3, [pc, #268] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800166c: 681b ldr r3, [r3, #0]
|
||
|
|
800166e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
||
|
|
8001672: 2b00 cmp r3, #0
|
||
|
|
8001674: d1f0 bne.n 8001658 <HAL_RCC_OscConfig+0x660>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
||
|
|
#if defined(RCC_PLLP_SUPPORT)
|
||
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
||
|
|
8001676: 4b40 ldr r3, [pc, #256] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001678: 68da ldr r2, [r3, #12]
|
||
|
|
800167a: 4b40 ldr r3, [pc, #256] ; (800177c <HAL_RCC_OscConfig+0x784>)
|
||
|
|
800167c: 4013 ands r3, r2
|
||
|
|
800167e: 687a ldr r2, [r7, #4]
|
||
|
|
8001680: 6ad1 ldr r1, [r2, #44] ; 0x2c
|
||
|
|
8001682: 687a ldr r2, [r7, #4]
|
||
|
|
8001684: 6b12 ldr r2, [r2, #48] ; 0x30
|
||
|
|
8001686: 3a01 subs r2, #1
|
||
|
|
8001688: 0112 lsls r2, r2, #4
|
||
|
|
800168a: 4311 orrs r1, r2
|
||
|
|
800168c: 687a ldr r2, [r7, #4]
|
||
|
|
800168e: 6b52 ldr r2, [r2, #52] ; 0x34
|
||
|
|
8001690: 0212 lsls r2, r2, #8
|
||
|
|
8001692: 4311 orrs r1, r2
|
||
|
|
8001694: 687a ldr r2, [r7, #4]
|
||
|
|
8001696: 6bd2 ldr r2, [r2, #60] ; 0x3c
|
||
|
|
8001698: 0852 lsrs r2, r2, #1
|
||
|
|
800169a: 3a01 subs r2, #1
|
||
|
|
800169c: 0552 lsls r2, r2, #21
|
||
|
|
800169e: 4311 orrs r1, r2
|
||
|
|
80016a0: 687a ldr r2, [r7, #4]
|
||
|
|
80016a2: 6c12 ldr r2, [r2, #64] ; 0x40
|
||
|
|
80016a4: 0852 lsrs r2, r2, #1
|
||
|
|
80016a6: 3a01 subs r2, #1
|
||
|
|
80016a8: 0652 lsls r2, r2, #25
|
||
|
|
80016aa: 4311 orrs r1, r2
|
||
|
|
80016ac: 687a ldr r2, [r7, #4]
|
||
|
|
80016ae: 6b92 ldr r2, [r2, #56] ; 0x38
|
||
|
|
80016b0: 0912 lsrs r2, r2, #4
|
||
|
|
80016b2: 0452 lsls r2, r2, #17
|
||
|
|
80016b4: 430a orrs r2, r1
|
||
|
|
80016b6: 4930 ldr r1, [pc, #192] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
80016b8: 4313 orrs r3, r2
|
||
|
|
80016ba: 60cb str r3, [r1, #12]
|
||
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
||
|
|
RCC_OscInitStruct->PLL.PLLR);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Enable the main PLL. */
|
||
|
|
__HAL_RCC_PLL_ENABLE();
|
||
|
|
80016bc: 4b2e ldr r3, [pc, #184] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
80016be: 681b ldr r3, [r3, #0]
|
||
|
|
80016c0: 4a2d ldr r2, [pc, #180] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
80016c2: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
||
|
|
80016c6: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Enable PLL System Clock output. */
|
||
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
||
|
|
80016c8: 4b2b ldr r3, [pc, #172] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
80016ca: 68db ldr r3, [r3, #12]
|
||
|
|
80016cc: 4a2a ldr r2, [pc, #168] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
80016ce: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
||
|
|
80016d2: 60d3 str r3, [r2, #12]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80016d4: f7ff f978 bl 80009c8 <HAL_GetTick>
|
||
|
|
80016d8: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till PLL is ready */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
||
|
|
80016da: e008 b.n 80016ee <HAL_RCC_OscConfig+0x6f6>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
||
|
|
80016dc: f7ff f974 bl 80009c8 <HAL_GetTick>
|
||
|
|
80016e0: 4602 mov r2, r0
|
||
|
|
80016e2: 693b ldr r3, [r7, #16]
|
||
|
|
80016e4: 1ad3 subs r3, r2, r3
|
||
|
|
80016e6: 2b02 cmp r3, #2
|
||
|
|
80016e8: d901 bls.n 80016ee <HAL_RCC_OscConfig+0x6f6>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80016ea: 2303 movs r3, #3
|
||
|
|
80016ec: e058 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
||
|
|
80016ee: 4b22 ldr r3, [pc, #136] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
80016f0: 681b ldr r3, [r3, #0]
|
||
|
|
80016f2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
||
|
|
80016f6: 2b00 cmp r3, #0
|
||
|
|
80016f8: d0f0 beq.n 80016dc <HAL_RCC_OscConfig+0x6e4>
|
||
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
||
|
|
80016fa: e050 b.n 800179e <HAL_RCC_OscConfig+0x7a6>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* PLL is already used as System core clock */
|
||
|
|
return HAL_ERROR;
|
||
|
|
80016fc: 2301 movs r3, #1
|
||
|
|
80016fe: e04f b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* PLL configuration is unchanged */
|
||
|
|
/* Re-enable PLL if it was disabled (ie. low power mode) */
|
||
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
||
|
|
8001700: 4b1d ldr r3, [pc, #116] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001702: 681b ldr r3, [r3, #0]
|
||
|
|
8001704: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
||
|
|
8001708: 2b00 cmp r3, #0
|
||
|
|
800170a: d148 bne.n 800179e <HAL_RCC_OscConfig+0x7a6>
|
||
|
|
{
|
||
|
|
/* Enable the main PLL. */
|
||
|
|
__HAL_RCC_PLL_ENABLE();
|
||
|
|
800170c: 4b1a ldr r3, [pc, #104] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800170e: 681b ldr r3, [r3, #0]
|
||
|
|
8001710: 4a19 ldr r2, [pc, #100] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001712: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
||
|
|
8001716: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Enable PLL System Clock output. */
|
||
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
||
|
|
8001718: 4b17 ldr r3, [pc, #92] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800171a: 68db ldr r3, [r3, #12]
|
||
|
|
800171c: 4a16 ldr r2, [pc, #88] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
800171e: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
||
|
|
8001722: 60d3 str r3, [r2, #12]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001724: f7ff f950 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001728: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till PLL is ready */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
||
|
|
800172a: e008 b.n 800173e <HAL_RCC_OscConfig+0x746>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
||
|
|
800172c: f7ff f94c bl 80009c8 <HAL_GetTick>
|
||
|
|
8001730: 4602 mov r2, r0
|
||
|
|
8001732: 693b ldr r3, [r7, #16]
|
||
|
|
8001734: 1ad3 subs r3, r2, r3
|
||
|
|
8001736: 2b02 cmp r3, #2
|
||
|
|
8001738: d901 bls.n 800173e <HAL_RCC_OscConfig+0x746>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
800173a: 2303 movs r3, #3
|
||
|
|
800173c: e030 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
||
|
|
800173e: 4b0e ldr r3, [pc, #56] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001740: 681b ldr r3, [r3, #0]
|
||
|
|
8001742: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
||
|
|
8001746: 2b00 cmp r3, #0
|
||
|
|
8001748: d0f0 beq.n 800172c <HAL_RCC_OscConfig+0x734>
|
||
|
|
800174a: e028 b.n 800179e <HAL_RCC_OscConfig+0x7a6>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Check that PLL is not used as system clock or not */
|
||
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
||
|
|
800174c: 69bb ldr r3, [r7, #24]
|
||
|
|
800174e: 2b0c cmp r3, #12
|
||
|
|
8001750: d023 beq.n 800179a <HAL_RCC_OscConfig+0x7a2>
|
||
|
|
{
|
||
|
|
/* Disable the main PLL. */
|
||
|
|
__HAL_RCC_PLL_DISABLE();
|
||
|
|
8001752: 4b09 ldr r3, [pc, #36] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001754: 681b ldr r3, [r3, #0]
|
||
|
|
8001756: 4a08 ldr r2, [pc, #32] ; (8001778 <HAL_RCC_OscConfig+0x780>)
|
||
|
|
8001758: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
||
|
|
800175c: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
800175e: f7ff f933 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001762: 6138 str r0, [r7, #16]
|
||
|
|
|
||
|
|
/* Wait till PLL is disabled */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
||
|
|
8001764: e00c b.n 8001780 <HAL_RCC_OscConfig+0x788>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
||
|
|
8001766: f7ff f92f bl 80009c8 <HAL_GetTick>
|
||
|
|
800176a: 4602 mov r2, r0
|
||
|
|
800176c: 693b ldr r3, [r7, #16]
|
||
|
|
800176e: 1ad3 subs r3, r2, r3
|
||
|
|
8001770: 2b02 cmp r3, #2
|
||
|
|
8001772: d905 bls.n 8001780 <HAL_RCC_OscConfig+0x788>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8001774: 2303 movs r3, #3
|
||
|
|
8001776: e013 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
8001778: 40021000 .word 0x40021000
|
||
|
|
800177c: f99d808c .word 0xf99d808c
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
||
|
|
8001780: 4b09 ldr r3, [pc, #36] ; (80017a8 <HAL_RCC_OscConfig+0x7b0>)
|
||
|
|
8001782: 681b ldr r3, [r3, #0]
|
||
|
|
8001784: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
||
|
|
8001788: 2b00 cmp r3, #0
|
||
|
|
800178a: d1ec bne.n 8001766 <HAL_RCC_OscConfig+0x76e>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* Unselect main PLL clock source and disable main PLL outputs to save power */
|
||
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
||
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
|
||
|
|
800178c: 4b06 ldr r3, [pc, #24] ; (80017a8 <HAL_RCC_OscConfig+0x7b0>)
|
||
|
|
800178e: 68da ldr r2, [r3, #12]
|
||
|
|
8001790: 4905 ldr r1, [pc, #20] ; (80017a8 <HAL_RCC_OscConfig+0x7b0>)
|
||
|
|
8001792: 4b06 ldr r3, [pc, #24] ; (80017ac <HAL_RCC_OscConfig+0x7b4>)
|
||
|
|
8001794: 4013 ands r3, r2
|
||
|
|
8001796: 60cb str r3, [r1, #12]
|
||
|
|
8001798: e001 b.n 800179e <HAL_RCC_OscConfig+0x7a6>
|
||
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* PLL is already used as System core clock */
|
||
|
|
return HAL_ERROR;
|
||
|
|
800179a: 2301 movs r3, #1
|
||
|
|
800179c: e000 b.n 80017a0 <HAL_RCC_OscConfig+0x7a8>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return HAL_OK;
|
||
|
|
800179e: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
80017a0: 4618 mov r0, r3
|
||
|
|
80017a2: 3720 adds r7, #32
|
||
|
|
80017a4: 46bd mov sp, r7
|
||
|
|
80017a6: bd80 pop {r7, pc}
|
||
|
|
80017a8: 40021000 .word 0x40021000
|
||
|
|
80017ac: feeefffc .word 0xfeeefffc
|
||
|
|
|
||
|
|
080017b0 <HAL_RCC_ClockConfig>:
|
||
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
||
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
||
|
|
{
|
||
|
|
80017b0: b580 push {r7, lr}
|
||
|
|
80017b2: b084 sub sp, #16
|
||
|
|
80017b4: af00 add r7, sp, #0
|
||
|
|
80017b6: 6078 str r0, [r7, #4]
|
||
|
|
80017b8: 6039 str r1, [r7, #0]
|
||
|
|
uint32_t hpre = RCC_SYSCLK_DIV1;
|
||
|
|
#endif
|
||
|
|
HAL_StatusTypeDef status;
|
||
|
|
|
||
|
|
/* Check Null pointer */
|
||
|
|
if(RCC_ClkInitStruct == NULL)
|
||
|
|
80017ba: 687b ldr r3, [r7, #4]
|
||
|
|
80017bc: 2b00 cmp r3, #0
|
||
|
|
80017be: d101 bne.n 80017c4 <HAL_RCC_ClockConfig+0x14>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
80017c0: 2301 movs r3, #1
|
||
|
|
80017c2: e0e7 b.n 8001994 <HAL_RCC_ClockConfig+0x1e4>
|
||
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
||
|
|
must be correctly programmed according to the frequency of the CPU clock
|
||
|
|
(HCLK) and the supply voltage of the device. */
|
||
|
|
|
||
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
||
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
||
|
|
80017c4: 4b75 ldr r3, [pc, #468] ; (800199c <HAL_RCC_ClockConfig+0x1ec>)
|
||
|
|
80017c6: 681b ldr r3, [r3, #0]
|
||
|
|
80017c8: f003 0307 and.w r3, r3, #7
|
||
|
|
80017cc: 683a ldr r2, [r7, #0]
|
||
|
|
80017ce: 429a cmp r2, r3
|
||
|
|
80017d0: d910 bls.n 80017f4 <HAL_RCC_ClockConfig+0x44>
|
||
|
|
{
|
||
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
||
|
|
80017d2: 4b72 ldr r3, [pc, #456] ; (800199c <HAL_RCC_ClockConfig+0x1ec>)
|
||
|
|
80017d4: 681b ldr r3, [r3, #0]
|
||
|
|
80017d6: f023 0207 bic.w r2, r3, #7
|
||
|
|
80017da: 4970 ldr r1, [pc, #448] ; (800199c <HAL_RCC_ClockConfig+0x1ec>)
|
||
|
|
80017dc: 683b ldr r3, [r7, #0]
|
||
|
|
80017de: 4313 orrs r3, r2
|
||
|
|
80017e0: 600b str r3, [r1, #0]
|
||
|
|
|
||
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
||
|
|
memory by reading the FLASH_ACR register */
|
||
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
||
|
|
80017e2: 4b6e ldr r3, [pc, #440] ; (800199c <HAL_RCC_ClockConfig+0x1ec>)
|
||
|
|
80017e4: 681b ldr r3, [r3, #0]
|
||
|
|
80017e6: f003 0307 and.w r3, r3, #7
|
||
|
|
80017ea: 683a ldr r2, [r7, #0]
|
||
|
|
80017ec: 429a cmp r2, r3
|
||
|
|
80017ee: d001 beq.n 80017f4 <HAL_RCC_ClockConfig+0x44>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
80017f0: 2301 movs r3, #1
|
||
|
|
80017f2: e0cf b.n 8001994 <HAL_RCC_ClockConfig+0x1e4>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
|
||
|
|
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
|
||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
||
|
|
80017f4: 687b ldr r3, [r7, #4]
|
||
|
|
80017f6: 681b ldr r3, [r3, #0]
|
||
|
|
80017f8: f003 0302 and.w r3, r3, #2
|
||
|
|
80017fc: 2b00 cmp r3, #0
|
||
|
|
80017fe: d010 beq.n 8001822 <HAL_RCC_ClockConfig+0x72>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
||
|
|
|
||
|
|
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
||
|
|
8001800: 687b ldr r3, [r7, #4]
|
||
|
|
8001802: 689a ldr r2, [r3, #8]
|
||
|
|
8001804: 4b66 ldr r3, [pc, #408] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001806: 689b ldr r3, [r3, #8]
|
||
|
|
8001808: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
||
|
|
800180c: 429a cmp r2, r3
|
||
|
|
800180e: d908 bls.n 8001822 <HAL_RCC_ClockConfig+0x72>
|
||
|
|
{
|
||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
||
|
|
8001810: 4b63 ldr r3, [pc, #396] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001812: 689b ldr r3, [r3, #8]
|
||
|
|
8001814: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
||
|
|
8001818: 687b ldr r3, [r7, #4]
|
||
|
|
800181a: 689b ldr r3, [r3, #8]
|
||
|
|
800181c: 4960 ldr r1, [pc, #384] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
800181e: 4313 orrs r3, r2
|
||
|
|
8001820: 608b str r3, [r1, #8]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
||
|
|
8001822: 687b ldr r3, [r7, #4]
|
||
|
|
8001824: 681b ldr r3, [r3, #0]
|
||
|
|
8001826: f003 0301 and.w r3, r3, #1
|
||
|
|
800182a: 2b00 cmp r3, #0
|
||
|
|
800182c: d04c beq.n 80018c8 <HAL_RCC_ClockConfig+0x118>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
||
|
|
|
||
|
|
/* PLL is selected as System Clock Source */
|
||
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
||
|
|
800182e: 687b ldr r3, [r7, #4]
|
||
|
|
8001830: 685b ldr r3, [r3, #4]
|
||
|
|
8001832: 2b03 cmp r3, #3
|
||
|
|
8001834: d107 bne.n 8001846 <HAL_RCC_ClockConfig+0x96>
|
||
|
|
{
|
||
|
|
/* Check the PLL ready flag */
|
||
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
||
|
|
8001836: 4b5a ldr r3, [pc, #360] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001838: 681b ldr r3, [r3, #0]
|
||
|
|
800183a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
||
|
|
800183e: 2b00 cmp r3, #0
|
||
|
|
8001840: d121 bne.n 8001886 <HAL_RCC_ClockConfig+0xd6>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001842: 2301 movs r3, #1
|
||
|
|
8001844: e0a6 b.n 8001994 <HAL_RCC_ClockConfig+0x1e4>
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* HSE is selected as System Clock Source */
|
||
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
||
|
|
8001846: 687b ldr r3, [r7, #4]
|
||
|
|
8001848: 685b ldr r3, [r3, #4]
|
||
|
|
800184a: 2b02 cmp r3, #2
|
||
|
|
800184c: d107 bne.n 800185e <HAL_RCC_ClockConfig+0xae>
|
||
|
|
{
|
||
|
|
/* Check the HSE ready flag */
|
||
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
||
|
|
800184e: 4b54 ldr r3, [pc, #336] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001850: 681b ldr r3, [r3, #0]
|
||
|
|
8001852: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
||
|
|
8001856: 2b00 cmp r3, #0
|
||
|
|
8001858: d115 bne.n 8001886 <HAL_RCC_ClockConfig+0xd6>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
800185a: 2301 movs r3, #1
|
||
|
|
800185c: e09a b.n 8001994 <HAL_RCC_ClockConfig+0x1e4>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* MSI is selected as System Clock Source */
|
||
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
||
|
|
800185e: 687b ldr r3, [r7, #4]
|
||
|
|
8001860: 685b ldr r3, [r3, #4]
|
||
|
|
8001862: 2b00 cmp r3, #0
|
||
|
|
8001864: d107 bne.n 8001876 <HAL_RCC_ClockConfig+0xc6>
|
||
|
|
{
|
||
|
|
/* Check the MSI ready flag */
|
||
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
||
|
|
8001866: 4b4e ldr r3, [pc, #312] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001868: 681b ldr r3, [r3, #0]
|
||
|
|
800186a: f003 0302 and.w r3, r3, #2
|
||
|
|
800186e: 2b00 cmp r3, #0
|
||
|
|
8001870: d109 bne.n 8001886 <HAL_RCC_ClockConfig+0xd6>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001872: 2301 movs r3, #1
|
||
|
|
8001874: e08e b.n 8001994 <HAL_RCC_ClockConfig+0x1e4>
|
||
|
|
}
|
||
|
|
/* HSI is selected as System Clock Source */
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Check the HSI ready flag */
|
||
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
||
|
|
8001876: 4b4a ldr r3, [pc, #296] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001878: 681b ldr r3, [r3, #0]
|
||
|
|
800187a: f403 6380 and.w r3, r3, #1024 ; 0x400
|
||
|
|
800187e: 2b00 cmp r3, #0
|
||
|
|
8001880: d101 bne.n 8001886 <HAL_RCC_ClockConfig+0xd6>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001882: 2301 movs r3, #1
|
||
|
|
8001884: e086 b.n 8001994 <HAL_RCC_ClockConfig+0x1e4>
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
||
|
|
8001886: 4b46 ldr r3, [pc, #280] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001888: 689b ldr r3, [r3, #8]
|
||
|
|
800188a: f023 0203 bic.w r2, r3, #3
|
||
|
|
800188e: 687b ldr r3, [r7, #4]
|
||
|
|
8001890: 685b ldr r3, [r3, #4]
|
||
|
|
8001892: 4943 ldr r1, [pc, #268] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001894: 4313 orrs r3, r2
|
||
|
|
8001896: 608b str r3, [r1, #8]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001898: f7ff f896 bl 80009c8 <HAL_GetTick>
|
||
|
|
800189c: 60f8 str r0, [r7, #12]
|
||
|
|
|
||
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
||
|
|
800189e: e00a b.n 80018b6 <HAL_RCC_ClockConfig+0x106>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
||
|
|
80018a0: f7ff f892 bl 80009c8 <HAL_GetTick>
|
||
|
|
80018a4: 4602 mov r2, r0
|
||
|
|
80018a6: 68fb ldr r3, [r7, #12]
|
||
|
|
80018a8: 1ad3 subs r3, r2, r3
|
||
|
|
80018aa: f241 3288 movw r2, #5000 ; 0x1388
|
||
|
|
80018ae: 4293 cmp r3, r2
|
||
|
|
80018b0: d901 bls.n 80018b6 <HAL_RCC_ClockConfig+0x106>
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
80018b2: 2303 movs r3, #3
|
||
|
|
80018b4: e06e b.n 8001994 <HAL_RCC_ClockConfig+0x1e4>
|
||
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
||
|
|
80018b6: 4b3a ldr r3, [pc, #232] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
80018b8: 689b ldr r3, [r3, #8]
|
||
|
|
80018ba: f003 020c and.w r2, r3, #12
|
||
|
|
80018be: 687b ldr r3, [r7, #4]
|
||
|
|
80018c0: 685b ldr r3, [r3, #4]
|
||
|
|
80018c2: 009b lsls r3, r3, #2
|
||
|
|
80018c4: 429a cmp r2, r3
|
||
|
|
80018c6: d1eb bne.n 80018a0 <HAL_RCC_ClockConfig+0xf0>
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
|
||
|
|
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
|
||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
||
|
|
80018c8: 687b ldr r3, [r7, #4]
|
||
|
|
80018ca: 681b ldr r3, [r3, #0]
|
||
|
|
80018cc: f003 0302 and.w r3, r3, #2
|
||
|
|
80018d0: 2b00 cmp r3, #0
|
||
|
|
80018d2: d010 beq.n 80018f6 <HAL_RCC_ClockConfig+0x146>
|
||
|
|
{
|
||
|
|
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
||
|
|
80018d4: 687b ldr r3, [r7, #4]
|
||
|
|
80018d6: 689a ldr r2, [r3, #8]
|
||
|
|
80018d8: 4b31 ldr r3, [pc, #196] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
80018da: 689b ldr r3, [r3, #8]
|
||
|
|
80018dc: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
||
|
|
80018e0: 429a cmp r2, r3
|
||
|
|
80018e2: d208 bcs.n 80018f6 <HAL_RCC_ClockConfig+0x146>
|
||
|
|
{
|
||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
||
|
|
80018e4: 4b2e ldr r3, [pc, #184] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
80018e6: 689b ldr r3, [r3, #8]
|
||
|
|
80018e8: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
||
|
|
80018ec: 687b ldr r3, [r7, #4]
|
||
|
|
80018ee: 689b ldr r3, [r3, #8]
|
||
|
|
80018f0: 492b ldr r1, [pc, #172] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
80018f2: 4313 orrs r3, r2
|
||
|
|
80018f4: 608b str r3, [r1, #8]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
|
||
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
||
|
|
80018f6: 4b29 ldr r3, [pc, #164] ; (800199c <HAL_RCC_ClockConfig+0x1ec>)
|
||
|
|
80018f8: 681b ldr r3, [r3, #0]
|
||
|
|
80018fa: f003 0307 and.w r3, r3, #7
|
||
|
|
80018fe: 683a ldr r2, [r7, #0]
|
||
|
|
8001900: 429a cmp r2, r3
|
||
|
|
8001902: d210 bcs.n 8001926 <HAL_RCC_ClockConfig+0x176>
|
||
|
|
{
|
||
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
||
|
|
8001904: 4b25 ldr r3, [pc, #148] ; (800199c <HAL_RCC_ClockConfig+0x1ec>)
|
||
|
|
8001906: 681b ldr r3, [r3, #0]
|
||
|
|
8001908: f023 0207 bic.w r2, r3, #7
|
||
|
|
800190c: 4923 ldr r1, [pc, #140] ; (800199c <HAL_RCC_ClockConfig+0x1ec>)
|
||
|
|
800190e: 683b ldr r3, [r7, #0]
|
||
|
|
8001910: 4313 orrs r3, r2
|
||
|
|
8001912: 600b str r3, [r1, #0]
|
||
|
|
|
||
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
||
|
|
memory by reading the FLASH_ACR register */
|
||
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
||
|
|
8001914: 4b21 ldr r3, [pc, #132] ; (800199c <HAL_RCC_ClockConfig+0x1ec>)
|
||
|
|
8001916: 681b ldr r3, [r3, #0]
|
||
|
|
8001918: f003 0307 and.w r3, r3, #7
|
||
|
|
800191c: 683a ldr r2, [r7, #0]
|
||
|
|
800191e: 429a cmp r2, r3
|
||
|
|
8001920: d001 beq.n 8001926 <HAL_RCC_ClockConfig+0x176>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001922: 2301 movs r3, #1
|
||
|
|
8001924: e036 b.n 8001994 <HAL_RCC_ClockConfig+0x1e4>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
||
|
|
8001926: 687b ldr r3, [r7, #4]
|
||
|
|
8001928: 681b ldr r3, [r3, #0]
|
||
|
|
800192a: f003 0304 and.w r3, r3, #4
|
||
|
|
800192e: 2b00 cmp r3, #0
|
||
|
|
8001930: d008 beq.n 8001944 <HAL_RCC_ClockConfig+0x194>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
||
|
|
8001932: 4b1b ldr r3, [pc, #108] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001934: 689b ldr r3, [r3, #8]
|
||
|
|
8001936: f423 62e0 bic.w r2, r3, #1792 ; 0x700
|
||
|
|
800193a: 687b ldr r3, [r7, #4]
|
||
|
|
800193c: 68db ldr r3, [r3, #12]
|
||
|
|
800193e: 4918 ldr r1, [pc, #96] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001940: 4313 orrs r3, r2
|
||
|
|
8001942: 608b str r3, [r1, #8]
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
||
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
||
|
|
8001944: 687b ldr r3, [r7, #4]
|
||
|
|
8001946: 681b ldr r3, [r3, #0]
|
||
|
|
8001948: f003 0308 and.w r3, r3, #8
|
||
|
|
800194c: 2b00 cmp r3, #0
|
||
|
|
800194e: d009 beq.n 8001964 <HAL_RCC_ClockConfig+0x1b4>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
||
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
||
|
|
8001950: 4b13 ldr r3, [pc, #76] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001952: 689b ldr r3, [r3, #8]
|
||
|
|
8001954: f423 5260 bic.w r2, r3, #14336 ; 0x3800
|
||
|
|
8001958: 687b ldr r3, [r7, #4]
|
||
|
|
800195a: 691b ldr r3, [r3, #16]
|
||
|
|
800195c: 00db lsls r3, r3, #3
|
||
|
|
800195e: 4910 ldr r1, [pc, #64] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
8001960: 4313 orrs r3, r2
|
||
|
|
8001962: 608b str r3, [r1, #8]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Update the SystemCoreClock global variable */
|
||
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
||
|
|
8001964: f000 f824 bl 80019b0 <HAL_RCC_GetSysClockFreq>
|
||
|
|
8001968: 4602 mov r2, r0
|
||
|
|
800196a: 4b0d ldr r3, [pc, #52] ; (80019a0 <HAL_RCC_ClockConfig+0x1f0>)
|
||
|
|
800196c: 689b ldr r3, [r3, #8]
|
||
|
|
800196e: 091b lsrs r3, r3, #4
|
||
|
|
8001970: f003 030f and.w r3, r3, #15
|
||
|
|
8001974: 490b ldr r1, [pc, #44] ; (80019a4 <HAL_RCC_ClockConfig+0x1f4>)
|
||
|
|
8001976: 5ccb ldrb r3, [r1, r3]
|
||
|
|
8001978: f003 031f and.w r3, r3, #31
|
||
|
|
800197c: fa22 f303 lsr.w r3, r2, r3
|
||
|
|
8001980: 4a09 ldr r2, [pc, #36] ; (80019a8 <HAL_RCC_ClockConfig+0x1f8>)
|
||
|
|
8001982: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Configure the source of time base considering new system clocks settings*/
|
||
|
|
status = HAL_InitTick(uwTickPrio);
|
||
|
|
8001984: 4b09 ldr r3, [pc, #36] ; (80019ac <HAL_RCC_ClockConfig+0x1fc>)
|
||
|
|
8001986: 681b ldr r3, [r3, #0]
|
||
|
|
8001988: 4618 mov r0, r3
|
||
|
|
800198a: f7fe ffcd bl 8000928 <HAL_InitTick>
|
||
|
|
800198e: 4603 mov r3, r0
|
||
|
|
8001990: 72fb strb r3, [r7, #11]
|
||
|
|
|
||
|
|
return status;
|
||
|
|
8001992: 7afb ldrb r3, [r7, #11]
|
||
|
|
}
|
||
|
|
8001994: 4618 mov r0, r3
|
||
|
|
8001996: 3710 adds r7, #16
|
||
|
|
8001998: 46bd mov sp, r7
|
||
|
|
800199a: bd80 pop {r7, pc}
|
||
|
|
800199c: 40022000 .word 0x40022000
|
||
|
|
80019a0: 40021000 .word 0x40021000
|
||
|
|
80019a4: 08005d28 .word 0x08005d28
|
||
|
|
80019a8: 20000000 .word 0x20000000
|
||
|
|
80019ac: 20000004 .word 0x20000004
|
||
|
|
|
||
|
|
080019b0 <HAL_RCC_GetSysClockFreq>:
|
||
|
|
*
|
||
|
|
*
|
||
|
|
* @retval SYSCLK frequency
|
||
|
|
*/
|
||
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
||
|
|
{
|
||
|
|
80019b0: b480 push {r7}
|
||
|
|
80019b2: b089 sub sp, #36 ; 0x24
|
||
|
|
80019b4: af00 add r7, sp, #0
|
||
|
|
uint32_t msirange = 0U, sysclockfreq = 0U;
|
||
|
|
80019b6: 2300 movs r3, #0
|
||
|
|
80019b8: 61fb str r3, [r7, #28]
|
||
|
|
80019ba: 2300 movs r3, #0
|
||
|
|
80019bc: 61bb str r3, [r7, #24]
|
||
|
|
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
|
||
|
|
uint32_t sysclk_source, pll_oscsource;
|
||
|
|
|
||
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
||
|
|
80019be: 4b3e ldr r3, [pc, #248] ; (8001ab8 <HAL_RCC_GetSysClockFreq+0x108>)
|
||
|
|
80019c0: 689b ldr r3, [r3, #8]
|
||
|
|
80019c2: f003 030c and.w r3, r3, #12
|
||
|
|
80019c6: 613b str r3, [r7, #16]
|
||
|
|
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
|
||
|
|
80019c8: 4b3b ldr r3, [pc, #236] ; (8001ab8 <HAL_RCC_GetSysClockFreq+0x108>)
|
||
|
|
80019ca: 68db ldr r3, [r3, #12]
|
||
|
|
80019cc: f003 0303 and.w r3, r3, #3
|
||
|
|
80019d0: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
||
|
|
80019d2: 693b ldr r3, [r7, #16]
|
||
|
|
80019d4: 2b00 cmp r3, #0
|
||
|
|
80019d6: d005 beq.n 80019e4 <HAL_RCC_GetSysClockFreq+0x34>
|
||
|
|
80019d8: 693b ldr r3, [r7, #16]
|
||
|
|
80019da: 2b0c cmp r3, #12
|
||
|
|
80019dc: d121 bne.n 8001a22 <HAL_RCC_GetSysClockFreq+0x72>
|
||
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
|
||
|
|
80019de: 68fb ldr r3, [r7, #12]
|
||
|
|
80019e0: 2b01 cmp r3, #1
|
||
|
|
80019e2: d11e bne.n 8001a22 <HAL_RCC_GetSysClockFreq+0x72>
|
||
|
|
{
|
||
|
|
/* MSI or PLL with MSI source used as system clock source */
|
||
|
|
|
||
|
|
/* Get SYSCLK source */
|
||
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
|
||
|
|
80019e4: 4b34 ldr r3, [pc, #208] ; (8001ab8 <HAL_RCC_GetSysClockFreq+0x108>)
|
||
|
|
80019e6: 681b ldr r3, [r3, #0]
|
||
|
|
80019e8: f003 0308 and.w r3, r3, #8
|
||
|
|
80019ec: 2b00 cmp r3, #0
|
||
|
|
80019ee: d107 bne.n 8001a00 <HAL_RCC_GetSysClockFreq+0x50>
|
||
|
|
{ /* MSISRANGE from RCC_CSR applies */
|
||
|
|
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
|
||
|
|
80019f0: 4b31 ldr r3, [pc, #196] ; (8001ab8 <HAL_RCC_GetSysClockFreq+0x108>)
|
||
|
|
80019f2: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
||
|
|
80019f6: 0a1b lsrs r3, r3, #8
|
||
|
|
80019f8: f003 030f and.w r3, r3, #15
|
||
|
|
80019fc: 61fb str r3, [r7, #28]
|
||
|
|
80019fe: e005 b.n 8001a0c <HAL_RCC_GetSysClockFreq+0x5c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{ /* MSIRANGE from RCC_CR applies */
|
||
|
|
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
|
||
|
|
8001a00: 4b2d ldr r3, [pc, #180] ; (8001ab8 <HAL_RCC_GetSysClockFreq+0x108>)
|
||
|
|
8001a02: 681b ldr r3, [r3, #0]
|
||
|
|
8001a04: 091b lsrs r3, r3, #4
|
||
|
|
8001a06: f003 030f and.w r3, r3, #15
|
||
|
|
8001a0a: 61fb str r3, [r7, #28]
|
||
|
|
}
|
||
|
|
/*MSI frequency range in HZ*/
|
||
|
|
msirange = MSIRangeTable[msirange];
|
||
|
|
8001a0c: 4a2b ldr r2, [pc, #172] ; (8001abc <HAL_RCC_GetSysClockFreq+0x10c>)
|
||
|
|
8001a0e: 69fb ldr r3, [r7, #28]
|
||
|
|
8001a10: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
||
|
|
8001a14: 61fb str r3, [r7, #28]
|
||
|
|
|
||
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
||
|
|
8001a16: 693b ldr r3, [r7, #16]
|
||
|
|
8001a18: 2b00 cmp r3, #0
|
||
|
|
8001a1a: d10d bne.n 8001a38 <HAL_RCC_GetSysClockFreq+0x88>
|
||
|
|
{
|
||
|
|
/* MSI used as system clock source */
|
||
|
|
sysclockfreq = msirange;
|
||
|
|
8001a1c: 69fb ldr r3, [r7, #28]
|
||
|
|
8001a1e: 61bb str r3, [r7, #24]
|
||
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
||
|
|
8001a20: e00a b.n 8001a38 <HAL_RCC_GetSysClockFreq+0x88>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSI)
|
||
|
|
8001a22: 693b ldr r3, [r7, #16]
|
||
|
|
8001a24: 2b04 cmp r3, #4
|
||
|
|
8001a26: d102 bne.n 8001a2e <HAL_RCC_GetSysClockFreq+0x7e>
|
||
|
|
{
|
||
|
|
/* HSI used as system clock source */
|
||
|
|
sysclockfreq = HSI_VALUE;
|
||
|
|
8001a28: 4b25 ldr r3, [pc, #148] ; (8001ac0 <HAL_RCC_GetSysClockFreq+0x110>)
|
||
|
|
8001a2a: 61bb str r3, [r7, #24]
|
||
|
|
8001a2c: e004 b.n 8001a38 <HAL_RCC_GetSysClockFreq+0x88>
|
||
|
|
}
|
||
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSE)
|
||
|
|
8001a2e: 693b ldr r3, [r7, #16]
|
||
|
|
8001a30: 2b08 cmp r3, #8
|
||
|
|
8001a32: d101 bne.n 8001a38 <HAL_RCC_GetSysClockFreq+0x88>
|
||
|
|
{
|
||
|
|
/* HSE used as system clock source */
|
||
|
|
sysclockfreq = HSE_VALUE;
|
||
|
|
8001a34: 4b23 ldr r3, [pc, #140] ; (8001ac4 <HAL_RCC_GetSysClockFreq+0x114>)
|
||
|
|
8001a36: 61bb str r3, [r7, #24]
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* unexpected case: sysclockfreq at 0 */
|
||
|
|
}
|
||
|
|
|
||
|
|
if(sysclk_source == RCC_CFGR_SWS_PLL)
|
||
|
|
8001a38: 693b ldr r3, [r7, #16]
|
||
|
|
8001a3a: 2b0c cmp r3, #12
|
||
|
|
8001a3c: d134 bne.n 8001aa8 <HAL_RCC_GetSysClockFreq+0xf8>
|
||
|
|
/* PLL used as system clock source */
|
||
|
|
|
||
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
|
||
|
|
SYSCLK = PLL_VCO / PLLR
|
||
|
|
*/
|
||
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
||
|
|
8001a3e: 4b1e ldr r3, [pc, #120] ; (8001ab8 <HAL_RCC_GetSysClockFreq+0x108>)
|
||
|
|
8001a40: 68db ldr r3, [r3, #12]
|
||
|
|
8001a42: f003 0303 and.w r3, r3, #3
|
||
|
|
8001a46: 60bb str r3, [r7, #8]
|
||
|
|
|
||
|
|
switch (pllsource)
|
||
|
|
8001a48: 68bb ldr r3, [r7, #8]
|
||
|
|
8001a4a: 2b02 cmp r3, #2
|
||
|
|
8001a4c: d003 beq.n 8001a56 <HAL_RCC_GetSysClockFreq+0xa6>
|
||
|
|
8001a4e: 68bb ldr r3, [r7, #8]
|
||
|
|
8001a50: 2b03 cmp r3, #3
|
||
|
|
8001a52: d003 beq.n 8001a5c <HAL_RCC_GetSysClockFreq+0xac>
|
||
|
|
8001a54: e005 b.n 8001a62 <HAL_RCC_GetSysClockFreq+0xb2>
|
||
|
|
{
|
||
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
||
|
|
pllvco = HSI_VALUE;
|
||
|
|
8001a56: 4b1a ldr r3, [pc, #104] ; (8001ac0 <HAL_RCC_GetSysClockFreq+0x110>)
|
||
|
|
8001a58: 617b str r3, [r7, #20]
|
||
|
|
break;
|
||
|
|
8001a5a: e005 b.n 8001a68 <HAL_RCC_GetSysClockFreq+0xb8>
|
||
|
|
|
||
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
||
|
|
pllvco = HSE_VALUE;
|
||
|
|
8001a5c: 4b19 ldr r3, [pc, #100] ; (8001ac4 <HAL_RCC_GetSysClockFreq+0x114>)
|
||
|
|
8001a5e: 617b str r3, [r7, #20]
|
||
|
|
break;
|
||
|
|
8001a60: e002 b.n 8001a68 <HAL_RCC_GetSysClockFreq+0xb8>
|
||
|
|
|
||
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
||
|
|
default:
|
||
|
|
pllvco = msirange;
|
||
|
|
8001a62: 69fb ldr r3, [r7, #28]
|
||
|
|
8001a64: 617b str r3, [r7, #20]
|
||
|
|
break;
|
||
|
|
8001a66: bf00 nop
|
||
|
|
}
|
||
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
||
|
|
8001a68: 4b13 ldr r3, [pc, #76] ; (8001ab8 <HAL_RCC_GetSysClockFreq+0x108>)
|
||
|
|
8001a6a: 68db ldr r3, [r3, #12]
|
||
|
|
8001a6c: 091b lsrs r3, r3, #4
|
||
|
|
8001a6e: f003 0307 and.w r3, r3, #7
|
||
|
|
8001a72: 3301 adds r3, #1
|
||
|
|
8001a74: 607b str r3, [r7, #4]
|
||
|
|
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
|
||
|
|
8001a76: 4b10 ldr r3, [pc, #64] ; (8001ab8 <HAL_RCC_GetSysClockFreq+0x108>)
|
||
|
|
8001a78: 68db ldr r3, [r3, #12]
|
||
|
|
8001a7a: 0a1b lsrs r3, r3, #8
|
||
|
|
8001a7c: f003 037f and.w r3, r3, #127 ; 0x7f
|
||
|
|
8001a80: 697a ldr r2, [r7, #20]
|
||
|
|
8001a82: fb03 f202 mul.w r2, r3, r2
|
||
|
|
8001a86: 687b ldr r3, [r7, #4]
|
||
|
|
8001a88: fbb2 f3f3 udiv r3, r2, r3
|
||
|
|
8001a8c: 617b str r3, [r7, #20]
|
||
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
||
|
|
8001a8e: 4b0a ldr r3, [pc, #40] ; (8001ab8 <HAL_RCC_GetSysClockFreq+0x108>)
|
||
|
|
8001a90: 68db ldr r3, [r3, #12]
|
||
|
|
8001a92: 0e5b lsrs r3, r3, #25
|
||
|
|
8001a94: f003 0303 and.w r3, r3, #3
|
||
|
|
8001a98: 3301 adds r3, #1
|
||
|
|
8001a9a: 005b lsls r3, r3, #1
|
||
|
|
8001a9c: 603b str r3, [r7, #0]
|
||
|
|
sysclockfreq = pllvco / pllr;
|
||
|
|
8001a9e: 697a ldr r2, [r7, #20]
|
||
|
|
8001aa0: 683b ldr r3, [r7, #0]
|
||
|
|
8001aa2: fbb2 f3f3 udiv r3, r2, r3
|
||
|
|
8001aa6: 61bb str r3, [r7, #24]
|
||
|
|
}
|
||
|
|
|
||
|
|
return sysclockfreq;
|
||
|
|
8001aa8: 69bb ldr r3, [r7, #24]
|
||
|
|
}
|
||
|
|
8001aaa: 4618 mov r0, r3
|
||
|
|
8001aac: 3724 adds r7, #36 ; 0x24
|
||
|
|
8001aae: 46bd mov sp, r7
|
||
|
|
8001ab0: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8001ab4: 4770 bx lr
|
||
|
|
8001ab6: bf00 nop
|
||
|
|
8001ab8: 40021000 .word 0x40021000
|
||
|
|
8001abc: 08005d40 .word 0x08005d40
|
||
|
|
8001ac0: 00f42400 .word 0x00f42400
|
||
|
|
8001ac4: 007a1200 .word 0x007a1200
|
||
|
|
|
||
|
|
08001ac8 <HAL_RCC_GetHCLKFreq>:
|
||
|
|
*
|
||
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
||
|
|
* @retval HCLK frequency in Hz
|
||
|
|
*/
|
||
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
||
|
|
{
|
||
|
|
8001ac8: b480 push {r7}
|
||
|
|
8001aca: af00 add r7, sp, #0
|
||
|
|
return SystemCoreClock;
|
||
|
|
8001acc: 4b03 ldr r3, [pc, #12] ; (8001adc <HAL_RCC_GetHCLKFreq+0x14>)
|
||
|
|
8001ace: 681b ldr r3, [r3, #0]
|
||
|
|
}
|
||
|
|
8001ad0: 4618 mov r0, r3
|
||
|
|
8001ad2: 46bd mov sp, r7
|
||
|
|
8001ad4: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8001ad8: 4770 bx lr
|
||
|
|
8001ada: bf00 nop
|
||
|
|
8001adc: 20000000 .word 0x20000000
|
||
|
|
|
||
|
|
08001ae0 <HAL_RCC_GetPCLK1Freq>:
|
||
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
||
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
||
|
|
* @retval PCLK1 frequency in Hz
|
||
|
|
*/
|
||
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
||
|
|
{
|
||
|
|
8001ae0: b580 push {r7, lr}
|
||
|
|
8001ae2: af00 add r7, sp, #0
|
||
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
||
|
|
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
|
||
|
|
8001ae4: f7ff fff0 bl 8001ac8 <HAL_RCC_GetHCLKFreq>
|
||
|
|
8001ae8: 4602 mov r2, r0
|
||
|
|
8001aea: 4b06 ldr r3, [pc, #24] ; (8001b04 <HAL_RCC_GetPCLK1Freq+0x24>)
|
||
|
|
8001aec: 689b ldr r3, [r3, #8]
|
||
|
|
8001aee: 0a1b lsrs r3, r3, #8
|
||
|
|
8001af0: f003 0307 and.w r3, r3, #7
|
||
|
|
8001af4: 4904 ldr r1, [pc, #16] ; (8001b08 <HAL_RCC_GetPCLK1Freq+0x28>)
|
||
|
|
8001af6: 5ccb ldrb r3, [r1, r3]
|
||
|
|
8001af8: f003 031f and.w r3, r3, #31
|
||
|
|
8001afc: fa22 f303 lsr.w r3, r2, r3
|
||
|
|
}
|
||
|
|
8001b00: 4618 mov r0, r3
|
||
|
|
8001b02: bd80 pop {r7, pc}
|
||
|
|
8001b04: 40021000 .word 0x40021000
|
||
|
|
8001b08: 08005d38 .word 0x08005d38
|
||
|
|
|
||
|
|
08001b0c <HAL_RCC_GetPCLK2Freq>:
|
||
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
||
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
||
|
|
* @retval PCLK2 frequency in Hz
|
||
|
|
*/
|
||
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
||
|
|
{
|
||
|
|
8001b0c: b580 push {r7, lr}
|
||
|
|
8001b0e: af00 add r7, sp, #0
|
||
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
||
|
|
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
|
||
|
|
8001b10: f7ff ffda bl 8001ac8 <HAL_RCC_GetHCLKFreq>
|
||
|
|
8001b14: 4602 mov r2, r0
|
||
|
|
8001b16: 4b06 ldr r3, [pc, #24] ; (8001b30 <HAL_RCC_GetPCLK2Freq+0x24>)
|
||
|
|
8001b18: 689b ldr r3, [r3, #8]
|
||
|
|
8001b1a: 0adb lsrs r3, r3, #11
|
||
|
|
8001b1c: f003 0307 and.w r3, r3, #7
|
||
|
|
8001b20: 4904 ldr r1, [pc, #16] ; (8001b34 <HAL_RCC_GetPCLK2Freq+0x28>)
|
||
|
|
8001b22: 5ccb ldrb r3, [r1, r3]
|
||
|
|
8001b24: f003 031f and.w r3, r3, #31
|
||
|
|
8001b28: fa22 f303 lsr.w r3, r2, r3
|
||
|
|
}
|
||
|
|
8001b2c: 4618 mov r0, r3
|
||
|
|
8001b2e: bd80 pop {r7, pc}
|
||
|
|
8001b30: 40021000 .word 0x40021000
|
||
|
|
8001b34: 08005d38 .word 0x08005d38
|
||
|
|
|
||
|
|
08001b38 <RCC_SetFlashLatencyFromMSIRange>:
|
||
|
|
voltage range.
|
||
|
|
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
|
||
|
|
{
|
||
|
|
8001b38: b580 push {r7, lr}
|
||
|
|
8001b3a: b086 sub sp, #24
|
||
|
|
8001b3c: af00 add r7, sp, #0
|
||
|
|
8001b3e: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t vos;
|
||
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
||
|
|
8001b40: 2300 movs r3, #0
|
||
|
|
8001b42: 613b str r3, [r7, #16]
|
||
|
|
|
||
|
|
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
|
||
|
|
8001b44: 4b2a ldr r3, [pc, #168] ; (8001bf0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
||
|
|
8001b46: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001b48: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001b4c: 2b00 cmp r3, #0
|
||
|
|
8001b4e: d003 beq.n 8001b58 <RCC_SetFlashLatencyFromMSIRange+0x20>
|
||
|
|
{
|
||
|
|
vos = HAL_PWREx_GetVoltageRange();
|
||
|
|
8001b50: f7ff f9ee bl 8000f30 <HAL_PWREx_GetVoltageRange>
|
||
|
|
8001b54: 6178 str r0, [r7, #20]
|
||
|
|
8001b56: e014 b.n 8001b82 <RCC_SetFlashLatencyFromMSIRange+0x4a>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||
|
|
8001b58: 4b25 ldr r3, [pc, #148] ; (8001bf0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
||
|
|
8001b5a: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001b5c: 4a24 ldr r2, [pc, #144] ; (8001bf0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
||
|
|
8001b5e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001b62: 6593 str r3, [r2, #88] ; 0x58
|
||
|
|
8001b64: 4b22 ldr r3, [pc, #136] ; (8001bf0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
||
|
|
8001b66: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001b68: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001b6c: 60fb str r3, [r7, #12]
|
||
|
|
8001b6e: 68fb ldr r3, [r7, #12]
|
||
|
|
vos = HAL_PWREx_GetVoltageRange();
|
||
|
|
8001b70: f7ff f9de bl 8000f30 <HAL_PWREx_GetVoltageRange>
|
||
|
|
8001b74: 6178 str r0, [r7, #20]
|
||
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
||
|
|
8001b76: 4b1e ldr r3, [pc, #120] ; (8001bf0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
||
|
|
8001b78: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001b7a: 4a1d ldr r2, [pc, #116] ; (8001bf0 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
||
|
|
8001b7c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001b80: 6593 str r3, [r2, #88] ; 0x58
|
||
|
|
}
|
||
|
|
|
||
|
|
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
|
||
|
|
8001b82: 697b ldr r3, [r7, #20]
|
||
|
|
8001b84: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
||
|
|
8001b88: d10b bne.n 8001ba2 <RCC_SetFlashLatencyFromMSIRange+0x6a>
|
||
|
|
{
|
||
|
|
if(msirange > RCC_MSIRANGE_8)
|
||
|
|
8001b8a: 687b ldr r3, [r7, #4]
|
||
|
|
8001b8c: 2b80 cmp r3, #128 ; 0x80
|
||
|
|
8001b8e: d919 bls.n 8001bc4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
||
|
|
{
|
||
|
|
/* MSI > 16Mhz */
|
||
|
|
if(msirange > RCC_MSIRANGE_10)
|
||
|
|
8001b90: 687b ldr r3, [r7, #4]
|
||
|
|
8001b92: 2ba0 cmp r3, #160 ; 0xa0
|
||
|
|
8001b94: d902 bls.n 8001b9c <RCC_SetFlashLatencyFromMSIRange+0x64>
|
||
|
|
{
|
||
|
|
/* MSI 48Mhz */
|
||
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
||
|
|
8001b96: 2302 movs r3, #2
|
||
|
|
8001b98: 613b str r3, [r7, #16]
|
||
|
|
8001b9a: e013 b.n 8001bc4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* MSI 24Mhz or 32Mhz */
|
||
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
||
|
|
8001b9c: 2301 movs r3, #1
|
||
|
|
8001b9e: 613b str r3, [r7, #16]
|
||
|
|
8001ba0: e010 b.n 8001bc4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
||
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
||
|
|
}
|
||
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
if(msirange > RCC_MSIRANGE_8)
|
||
|
|
8001ba2: 687b ldr r3, [r7, #4]
|
||
|
|
8001ba4: 2b80 cmp r3, #128 ; 0x80
|
||
|
|
8001ba6: d902 bls.n 8001bae <RCC_SetFlashLatencyFromMSIRange+0x76>
|
||
|
|
{
|
||
|
|
/* MSI > 16Mhz */
|
||
|
|
latency = FLASH_LATENCY_3; /* 3WS */
|
||
|
|
8001ba8: 2303 movs r3, #3
|
||
|
|
8001baa: 613b str r3, [r7, #16]
|
||
|
|
8001bac: e00a b.n 8001bc4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if(msirange == RCC_MSIRANGE_8)
|
||
|
|
8001bae: 687b ldr r3, [r7, #4]
|
||
|
|
8001bb0: 2b80 cmp r3, #128 ; 0x80
|
||
|
|
8001bb2: d102 bne.n 8001bba <RCC_SetFlashLatencyFromMSIRange+0x82>
|
||
|
|
{
|
||
|
|
/* MSI 16Mhz */
|
||
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
||
|
|
8001bb4: 2302 movs r3, #2
|
||
|
|
8001bb6: 613b str r3, [r7, #16]
|
||
|
|
8001bb8: e004 b.n 8001bc4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
||
|
|
}
|
||
|
|
else if(msirange == RCC_MSIRANGE_7)
|
||
|
|
8001bba: 687b ldr r3, [r7, #4]
|
||
|
|
8001bbc: 2b70 cmp r3, #112 ; 0x70
|
||
|
|
8001bbe: d101 bne.n 8001bc4 <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
||
|
|
{
|
||
|
|
/* MSI 8Mhz */
|
||
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
||
|
|
8001bc0: 2301 movs r3, #1
|
||
|
|
8001bc2: 613b str r3, [r7, #16]
|
||
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
||
|
|
8001bc4: 4b0b ldr r3, [pc, #44] ; (8001bf4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
||
|
|
8001bc6: 681b ldr r3, [r3, #0]
|
||
|
|
8001bc8: f023 0207 bic.w r2, r3, #7
|
||
|
|
8001bcc: 4909 ldr r1, [pc, #36] ; (8001bf4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
||
|
|
8001bce: 693b ldr r3, [r7, #16]
|
||
|
|
8001bd0: 4313 orrs r3, r2
|
||
|
|
8001bd2: 600b str r3, [r1, #0]
|
||
|
|
|
||
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
||
|
|
memory by reading the FLASH_ACR register */
|
||
|
|
if(__HAL_FLASH_GET_LATENCY() != latency)
|
||
|
|
8001bd4: 4b07 ldr r3, [pc, #28] ; (8001bf4 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
||
|
|
8001bd6: 681b ldr r3, [r3, #0]
|
||
|
|
8001bd8: f003 0307 and.w r3, r3, #7
|
||
|
|
8001bdc: 693a ldr r2, [r7, #16]
|
||
|
|
8001bde: 429a cmp r2, r3
|
||
|
|
8001be0: d001 beq.n 8001be6 <RCC_SetFlashLatencyFromMSIRange+0xae>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
8001be2: 2301 movs r3, #1
|
||
|
|
8001be4: e000 b.n 8001be8 <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
||
|
|
}
|
||
|
|
|
||
|
|
return HAL_OK;
|
||
|
|
8001be6: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8001be8: 4618 mov r0, r3
|
||
|
|
8001bea: 3718 adds r7, #24
|
||
|
|
8001bec: 46bd mov sp, r7
|
||
|
|
8001bee: bd80 pop {r7, pc}
|
||
|
|
8001bf0: 40021000 .word 0x40021000
|
||
|
|
8001bf4: 40022000 .word 0x40022000
|
||
|
|
|
||
|
|
08001bf8 <HAL_RCCEx_PeriphCLKConfig>:
|
||
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
||
|
|
*
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||
|
|
{
|
||
|
|
8001bf8: b580 push {r7, lr}
|
||
|
|
8001bfa: b086 sub sp, #24
|
||
|
|
8001bfc: af00 add r7, sp, #0
|
||
|
|
8001bfe: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t tmpregister, tickstart; /* no init needed */
|
||
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
||
|
|
8001c00: 2300 movs r3, #0
|
||
|
|
8001c02: 74fb strb r3, [r7, #19]
|
||
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
||
|
|
8001c04: 2300 movs r3, #0
|
||
|
|
8001c06: 74bb strb r3, [r7, #18]
|
||
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
||
|
|
|
||
|
|
#if defined(SAI1)
|
||
|
|
|
||
|
|
/*-------------------------- SAI1 clock source configuration ---------------------*/
|
||
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
|
||
|
|
8001c08: 687b ldr r3, [r7, #4]
|
||
|
|
8001c0a: 681b ldr r3, [r3, #0]
|
||
|
|
8001c0c: f403 6300 and.w r3, r3, #2048 ; 0x800
|
||
|
|
8001c10: 2b00 cmp r3, #0
|
||
|
|
8001c12: d041 beq.n 8001c98 <HAL_RCCEx_PeriphCLKConfig+0xa0>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
|
||
|
|
|
||
|
|
switch(PeriphClkInit->Sai1ClockSelection)
|
||
|
|
8001c14: 687b ldr r3, [r7, #4]
|
||
|
|
8001c16: 6e5b ldr r3, [r3, #100] ; 0x64
|
||
|
|
8001c18: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000
|
||
|
|
8001c1c: d02a beq.n 8001c74 <HAL_RCCEx_PeriphCLKConfig+0x7c>
|
||
|
|
8001c1e: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000
|
||
|
|
8001c22: d824 bhi.n 8001c6e <HAL_RCCEx_PeriphCLKConfig+0x76>
|
||
|
|
8001c24: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
|
||
|
|
8001c28: d008 beq.n 8001c3c <HAL_RCCEx_PeriphCLKConfig+0x44>
|
||
|
|
8001c2a: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
|
||
|
|
8001c2e: d81e bhi.n 8001c6e <HAL_RCCEx_PeriphCLKConfig+0x76>
|
||
|
|
8001c30: 2b00 cmp r3, #0
|
||
|
|
8001c32: d00a beq.n 8001c4a <HAL_RCCEx_PeriphCLKConfig+0x52>
|
||
|
|
8001c34: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
|
||
|
|
8001c38: d010 beq.n 8001c5c <HAL_RCCEx_PeriphCLKConfig+0x64>
|
||
|
|
8001c3a: e018 b.n 8001c6e <HAL_RCCEx_PeriphCLKConfig+0x76>
|
||
|
|
{
|
||
|
|
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
|
||
|
|
/* Enable SAI Clock output generated from System PLL . */
|
||
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
||
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
||
|
|
8001c3c: 4b86 ldr r3, [pc, #536] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001c3e: 68db ldr r3, [r3, #12]
|
||
|
|
8001c40: 4a85 ldr r2, [pc, #532] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001c42: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
||
|
|
8001c46: 60d3 str r3, [r2, #12]
|
||
|
|
#else
|
||
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
|
||
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
||
|
|
/* SAI1 clock source config set later after clock selection check */
|
||
|
|
break;
|
||
|
|
8001c48: e015 b.n 8001c76 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
||
|
|
|
||
|
|
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
|
||
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
||
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
||
|
|
8001c4a: 687b ldr r3, [r7, #4]
|
||
|
|
8001c4c: 3304 adds r3, #4
|
||
|
|
8001c4e: 2100 movs r1, #0
|
||
|
|
8001c50: 4618 mov r0, r3
|
||
|
|
8001c52: f000 fabb bl 80021cc <RCCEx_PLLSAI1_Config>
|
||
|
|
8001c56: 4603 mov r3, r0
|
||
|
|
8001c58: 74fb strb r3, [r7, #19]
|
||
|
|
/* SAI1 clock source config set later after clock selection check */
|
||
|
|
break;
|
||
|
|
8001c5a: e00c b.n 8001c76 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
||
|
|
|
||
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
||
|
|
|
||
|
|
case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
|
||
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
|
||
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
||
|
|
8001c5c: 687b ldr r3, [r7, #4]
|
||
|
|
8001c5e: 3320 adds r3, #32
|
||
|
|
8001c60: 2100 movs r1, #0
|
||
|
|
8001c62: 4618 mov r0, r3
|
||
|
|
8001c64: f000 fba6 bl 80023b4 <RCCEx_PLLSAI2_Config>
|
||
|
|
8001c68: 4603 mov r3, r0
|
||
|
|
8001c6a: 74fb strb r3, [r7, #19]
|
||
|
|
/* SAI1 clock source config set later after clock selection check */
|
||
|
|
break;
|
||
|
|
8001c6c: e003 b.n 8001c76 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
||
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
||
|
|
/* SAI1 clock source config set later after clock selection check */
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8001c6e: 2301 movs r3, #1
|
||
|
|
8001c70: 74fb strb r3, [r7, #19]
|
||
|
|
break;
|
||
|
|
8001c72: e000 b.n 8001c76 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
||
|
|
break;
|
||
|
|
8001c74: bf00 nop
|
||
|
|
}
|
||
|
|
|
||
|
|
if(ret == HAL_OK)
|
||
|
|
8001c76: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8001c78: 2b00 cmp r3, #0
|
||
|
|
8001c7a: d10b bne.n 8001c94 <HAL_RCCEx_PeriphCLKConfig+0x9c>
|
||
|
|
{
|
||
|
|
/* Set the source of SAI1 clock*/
|
||
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
||
|
|
8001c7c: 4b76 ldr r3, [pc, #472] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001c7e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001c82: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
|
||
|
|
8001c86: 687b ldr r3, [r7, #4]
|
||
|
|
8001c88: 6e5b ldr r3, [r3, #100] ; 0x64
|
||
|
|
8001c8a: 4973 ldr r1, [pc, #460] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001c8c: 4313 orrs r3, r2
|
||
|
|
8001c8e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
8001c92: e001 b.n 8001c98 <HAL_RCCEx_PeriphCLKConfig+0xa0>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* set overall return value */
|
||
|
|
status = ret;
|
||
|
|
8001c94: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8001c96: 74bb strb r3, [r7, #18]
|
||
|
|
#endif /* SAI1 */
|
||
|
|
|
||
|
|
#if defined(SAI2)
|
||
|
|
|
||
|
|
/*-------------------------- SAI2 clock source configuration ---------------------*/
|
||
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
|
||
|
|
8001c98: 687b ldr r3, [r7, #4]
|
||
|
|
8001c9a: 681b ldr r3, [r3, #0]
|
||
|
|
8001c9c: f403 5380 and.w r3, r3, #4096 ; 0x1000
|
||
|
|
8001ca0: 2b00 cmp r3, #0
|
||
|
|
8001ca2: d041 beq.n 8001d28 <HAL_RCCEx_PeriphCLKConfig+0x130>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
|
||
|
|
|
||
|
|
switch(PeriphClkInit->Sai2ClockSelection)
|
||
|
|
8001ca4: 687b ldr r3, [r7, #4]
|
||
|
|
8001ca6: 6e9b ldr r3, [r3, #104] ; 0x68
|
||
|
|
8001ca8: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000
|
||
|
|
8001cac: d02a beq.n 8001d04 <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
||
|
|
8001cae: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000
|
||
|
|
8001cb2: d824 bhi.n 8001cfe <HAL_RCCEx_PeriphCLKConfig+0x106>
|
||
|
|
8001cb4: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
|
||
|
|
8001cb8: d008 beq.n 8001ccc <HAL_RCCEx_PeriphCLKConfig+0xd4>
|
||
|
|
8001cba: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
|
||
|
|
8001cbe: d81e bhi.n 8001cfe <HAL_RCCEx_PeriphCLKConfig+0x106>
|
||
|
|
8001cc0: 2b00 cmp r3, #0
|
||
|
|
8001cc2: d00a beq.n 8001cda <HAL_RCCEx_PeriphCLKConfig+0xe2>
|
||
|
|
8001cc4: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
||
|
|
8001cc8: d010 beq.n 8001cec <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
||
|
|
8001cca: e018 b.n 8001cfe <HAL_RCCEx_PeriphCLKConfig+0x106>
|
||
|
|
{
|
||
|
|
case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
|
||
|
|
/* Enable SAI Clock output generated from System PLL . */
|
||
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
||
|
|
8001ccc: 4b62 ldr r3, [pc, #392] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001cce: 68db ldr r3, [r3, #12]
|
||
|
|
8001cd0: 4a61 ldr r2, [pc, #388] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001cd2: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
||
|
|
8001cd6: 60d3 str r3, [r2, #12]
|
||
|
|
/* SAI2 clock source config set later after clock selection check */
|
||
|
|
break;
|
||
|
|
8001cd8: e015 b.n 8001d06 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
||
|
|
|
||
|
|
case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
|
||
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
||
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
||
|
|
8001cda: 687b ldr r3, [r7, #4]
|
||
|
|
8001cdc: 3304 adds r3, #4
|
||
|
|
8001cde: 2100 movs r1, #0
|
||
|
|
8001ce0: 4618 mov r0, r3
|
||
|
|
8001ce2: f000 fa73 bl 80021cc <RCCEx_PLLSAI1_Config>
|
||
|
|
8001ce6: 4603 mov r3, r0
|
||
|
|
8001ce8: 74fb strb r3, [r7, #19]
|
||
|
|
/* SAI2 clock source config set later after clock selection check */
|
||
|
|
break;
|
||
|
|
8001cea: e00c b.n 8001d06 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
||
|
|
|
||
|
|
case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
|
||
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
|
||
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
||
|
|
8001cec: 687b ldr r3, [r7, #4]
|
||
|
|
8001cee: 3320 adds r3, #32
|
||
|
|
8001cf0: 2100 movs r1, #0
|
||
|
|
8001cf2: 4618 mov r0, r3
|
||
|
|
8001cf4: f000 fb5e bl 80023b4 <RCCEx_PLLSAI2_Config>
|
||
|
|
8001cf8: 4603 mov r3, r0
|
||
|
|
8001cfa: 74fb strb r3, [r7, #19]
|
||
|
|
/* SAI2 clock source config set later after clock selection check */
|
||
|
|
break;
|
||
|
|
8001cfc: e003 b.n 8001d06 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
||
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
||
|
|
/* SAI2 clock source config set later after clock selection check */
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8001cfe: 2301 movs r3, #1
|
||
|
|
8001d00: 74fb strb r3, [r7, #19]
|
||
|
|
break;
|
||
|
|
8001d02: e000 b.n 8001d06 <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
||
|
|
break;
|
||
|
|
8001d04: bf00 nop
|
||
|
|
}
|
||
|
|
|
||
|
|
if(ret == HAL_OK)
|
||
|
|
8001d06: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8001d08: 2b00 cmp r3, #0
|
||
|
|
8001d0a: d10b bne.n 8001d24 <HAL_RCCEx_PeriphCLKConfig+0x12c>
|
||
|
|
{
|
||
|
|
/* Set the source of SAI2 clock*/
|
||
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
||
|
|
8001d0c: 4b52 ldr r3, [pc, #328] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001d0e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001d12: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
|
||
|
|
8001d16: 687b ldr r3, [r7, #4]
|
||
|
|
8001d18: 6e9b ldr r3, [r3, #104] ; 0x68
|
||
|
|
8001d1a: 494f ldr r1, [pc, #316] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001d1c: 4313 orrs r3, r2
|
||
|
|
8001d1e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
8001d22: e001 b.n 8001d28 <HAL_RCCEx_PeriphCLKConfig+0x130>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* set overall return value */
|
||
|
|
status = ret;
|
||
|
|
8001d24: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8001d26: 74bb strb r3, [r7, #18]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* SAI2 */
|
||
|
|
|
||
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
||
|
|
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
||
|
|
8001d28: 687b ldr r3, [r7, #4]
|
||
|
|
8001d2a: 681b ldr r3, [r3, #0]
|
||
|
|
8001d2c: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
||
|
|
8001d30: 2b00 cmp r3, #0
|
||
|
|
8001d32: f000 80a0 beq.w 8001e76 <HAL_RCCEx_PeriphCLKConfig+0x27e>
|
||
|
|
{
|
||
|
|
FlagStatus pwrclkchanged = RESET;
|
||
|
|
8001d36: 2300 movs r3, #0
|
||
|
|
8001d38: 747b strb r3, [r7, #17]
|
||
|
|
|
||
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
||
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
||
|
|
|
||
|
|
/* Enable Power Clock */
|
||
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
||
|
|
8001d3a: 4b47 ldr r3, [pc, #284] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001d3c: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001d3e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001d42: 2b00 cmp r3, #0
|
||
|
|
8001d44: d101 bne.n 8001d4a <HAL_RCCEx_PeriphCLKConfig+0x152>
|
||
|
|
8001d46: 2301 movs r3, #1
|
||
|
|
8001d48: e000 b.n 8001d4c <HAL_RCCEx_PeriphCLKConfig+0x154>
|
||
|
|
8001d4a: 2300 movs r3, #0
|
||
|
|
8001d4c: 2b00 cmp r3, #0
|
||
|
|
8001d4e: d00d beq.n 8001d6c <HAL_RCCEx_PeriphCLKConfig+0x174>
|
||
|
|
{
|
||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||
|
|
8001d50: 4b41 ldr r3, [pc, #260] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001d52: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001d54: 4a40 ldr r2, [pc, #256] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001d56: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001d5a: 6593 str r3, [r2, #88] ; 0x58
|
||
|
|
8001d5c: 4b3e ldr r3, [pc, #248] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001d5e: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001d60: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001d64: 60bb str r3, [r7, #8]
|
||
|
|
8001d66: 68bb ldr r3, [r7, #8]
|
||
|
|
pwrclkchanged = SET;
|
||
|
|
8001d68: 2301 movs r3, #1
|
||
|
|
8001d6a: 747b strb r3, [r7, #17]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable write access to Backup domain */
|
||
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
||
|
|
8001d6c: 4b3b ldr r3, [pc, #236] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
||
|
|
8001d6e: 681b ldr r3, [r3, #0]
|
||
|
|
8001d70: 4a3a ldr r2, [pc, #232] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
||
|
|
8001d72: f443 7380 orr.w r3, r3, #256 ; 0x100
|
||
|
|
8001d76: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Wait for Backup domain Write protection disable */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001d78: f7fe fe26 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001d7c: 60f8 str r0, [r7, #12]
|
||
|
|
|
||
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
||
|
|
8001d7e: e009 b.n 8001d94 <HAL_RCCEx_PeriphCLKConfig+0x19c>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
||
|
|
8001d80: f7fe fe22 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001d84: 4602 mov r2, r0
|
||
|
|
8001d86: 68fb ldr r3, [r7, #12]
|
||
|
|
8001d88: 1ad3 subs r3, r2, r3
|
||
|
|
8001d8a: 2b02 cmp r3, #2
|
||
|
|
8001d8c: d902 bls.n 8001d94 <HAL_RCCEx_PeriphCLKConfig+0x19c>
|
||
|
|
{
|
||
|
|
ret = HAL_TIMEOUT;
|
||
|
|
8001d8e: 2303 movs r3, #3
|
||
|
|
8001d90: 74fb strb r3, [r7, #19]
|
||
|
|
break;
|
||
|
|
8001d92: e005 b.n 8001da0 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
|
||
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
||
|
|
8001d94: 4b31 ldr r3, [pc, #196] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
||
|
|
8001d96: 681b ldr r3, [r3, #0]
|
||
|
|
8001d98: f403 7380 and.w r3, r3, #256 ; 0x100
|
||
|
|
8001d9c: 2b00 cmp r3, #0
|
||
|
|
8001d9e: d0ef beq.n 8001d80 <HAL_RCCEx_PeriphCLKConfig+0x188>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(ret == HAL_OK)
|
||
|
|
8001da0: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8001da2: 2b00 cmp r3, #0
|
||
|
|
8001da4: d15c bne.n 8001e60 <HAL_RCCEx_PeriphCLKConfig+0x268>
|
||
|
|
{
|
||
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
|
||
|
|
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
|
||
|
|
8001da6: 4b2c ldr r3, [pc, #176] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001da8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
8001dac: f403 7340 and.w r3, r3, #768 ; 0x300
|
||
|
|
8001db0: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
||
|
|
8001db2: 697b ldr r3, [r7, #20]
|
||
|
|
8001db4: 2b00 cmp r3, #0
|
||
|
|
8001db6: d01f beq.n 8001df8 <HAL_RCCEx_PeriphCLKConfig+0x200>
|
||
|
|
8001db8: 687b ldr r3, [r7, #4]
|
||
|
|
8001dba: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
||
|
|
8001dbe: 697a ldr r2, [r7, #20]
|
||
|
|
8001dc0: 429a cmp r2, r3
|
||
|
|
8001dc2: d019 beq.n 8001df8 <HAL_RCCEx_PeriphCLKConfig+0x200>
|
||
|
|
{
|
||
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
||
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
||
|
|
8001dc4: 4b24 ldr r3, [pc, #144] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001dc6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
8001dca: f423 7340 bic.w r3, r3, #768 ; 0x300
|
||
|
|
8001dce: 617b str r3, [r7, #20]
|
||
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
||
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
||
|
|
8001dd0: 4b21 ldr r3, [pc, #132] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001dd2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
8001dd6: 4a20 ldr r2, [pc, #128] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001dd8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
||
|
|
8001ddc: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
||
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
||
|
|
8001de0: 4b1d ldr r3, [pc, #116] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001de2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
8001de6: 4a1c ldr r2, [pc, #112] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001de8: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
||
|
|
8001dec: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
||
|
|
/* Restore the Content of BDCR register */
|
||
|
|
RCC->BDCR = tmpregister;
|
||
|
|
8001df0: 4a19 ldr r2, [pc, #100] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001df2: 697b ldr r3, [r7, #20]
|
||
|
|
8001df4: f8c2 3090 str.w r3, [r2, #144] ; 0x90
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
||
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
|
||
|
|
8001df8: 697b ldr r3, [r7, #20]
|
||
|
|
8001dfa: f003 0301 and.w r3, r3, #1
|
||
|
|
8001dfe: 2b00 cmp r3, #0
|
||
|
|
8001e00: d016 beq.n 8001e30 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
||
|
|
{
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8001e02: f7fe fde1 bl 80009c8 <HAL_GetTick>
|
||
|
|
8001e06: 60f8 str r0, [r7, #12]
|
||
|
|
|
||
|
|
/* Wait till LSE is ready */
|
||
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
||
|
|
8001e08: e00b b.n 8001e22 <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
||
|
|
8001e0a: f7fe fddd bl 80009c8 <HAL_GetTick>
|
||
|
|
8001e0e: 4602 mov r2, r0
|
||
|
|
8001e10: 68fb ldr r3, [r7, #12]
|
||
|
|
8001e12: 1ad3 subs r3, r2, r3
|
||
|
|
8001e14: f241 3288 movw r2, #5000 ; 0x1388
|
||
|
|
8001e18: 4293 cmp r3, r2
|
||
|
|
8001e1a: d902 bls.n 8001e22 <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
||
|
|
{
|
||
|
|
ret = HAL_TIMEOUT;
|
||
|
|
8001e1c: 2303 movs r3, #3
|
||
|
|
8001e1e: 74fb strb r3, [r7, #19]
|
||
|
|
break;
|
||
|
|
8001e20: e006 b.n 8001e30 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
||
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
||
|
|
8001e22: 4b0d ldr r3, [pc, #52] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001e24: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
8001e28: f003 0302 and.w r3, r3, #2
|
||
|
|
8001e2c: 2b00 cmp r3, #0
|
||
|
|
8001e2e: d0ec beq.n 8001e0a <HAL_RCCEx_PeriphCLKConfig+0x212>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(ret == HAL_OK)
|
||
|
|
8001e30: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8001e32: 2b00 cmp r3, #0
|
||
|
|
8001e34: d10c bne.n 8001e50 <HAL_RCCEx_PeriphCLKConfig+0x258>
|
||
|
|
{
|
||
|
|
/* Apply new RTC clock source selection */
|
||
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||
|
|
8001e36: 4b08 ldr r3, [pc, #32] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001e38: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
||
|
|
8001e3c: f423 7240 bic.w r2, r3, #768 ; 0x300
|
||
|
|
8001e40: 687b ldr r3, [r7, #4]
|
||
|
|
8001e42: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
||
|
|
8001e46: 4904 ldr r1, [pc, #16] ; (8001e58 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
||
|
|
8001e48: 4313 orrs r3, r2
|
||
|
|
8001e4a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
||
|
|
8001e4e: e009 b.n 8001e64 <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* set overall return value */
|
||
|
|
status = ret;
|
||
|
|
8001e50: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8001e52: 74bb strb r3, [r7, #18]
|
||
|
|
8001e54: e006 b.n 8001e64 <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
||
|
|
8001e56: bf00 nop
|
||
|
|
8001e58: 40021000 .word 0x40021000
|
||
|
|
8001e5c: 40007000 .word 0x40007000
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* set overall return value */
|
||
|
|
status = ret;
|
||
|
|
8001e60: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8001e62: 74bb strb r3, [r7, #18]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Restore clock configuration if changed */
|
||
|
|
if(pwrclkchanged == SET)
|
||
|
|
8001e64: 7c7b ldrb r3, [r7, #17]
|
||
|
|
8001e66: 2b01 cmp r3, #1
|
||
|
|
8001e68: d105 bne.n 8001e76 <HAL_RCCEx_PeriphCLKConfig+0x27e>
|
||
|
|
{
|
||
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
||
|
|
8001e6a: 4b9e ldr r3, [pc, #632] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001e6c: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001e6e: 4a9d ldr r2, [pc, #628] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001e70: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8001e74: 6593 str r3, [r2, #88] ; 0x58
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
||
|
|
8001e76: 687b ldr r3, [r7, #4]
|
||
|
|
8001e78: 681b ldr r3, [r3, #0]
|
||
|
|
8001e7a: f003 0301 and.w r3, r3, #1
|
||
|
|
8001e7e: 2b00 cmp r3, #0
|
||
|
|
8001e80: d00a beq.n 8001e98 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the USART1 clock source */
|
||
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
||
|
|
8001e82: 4b98 ldr r3, [pc, #608] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001e84: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001e88: f023 0203 bic.w r2, r3, #3
|
||
|
|
8001e8c: 687b ldr r3, [r7, #4]
|
||
|
|
8001e8e: 6b9b ldr r3, [r3, #56] ; 0x38
|
||
|
|
8001e90: 4994 ldr r1, [pc, #592] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001e92: 4313 orrs r3, r2
|
||
|
|
8001e94: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- USART2 clock source configuration -------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
||
|
|
8001e98: 687b ldr r3, [r7, #4]
|
||
|
|
8001e9a: 681b ldr r3, [r3, #0]
|
||
|
|
8001e9c: f003 0302 and.w r3, r3, #2
|
||
|
|
8001ea0: 2b00 cmp r3, #0
|
||
|
|
8001ea2: d00a beq.n 8001eba <HAL_RCCEx_PeriphCLKConfig+0x2c2>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the USART2 clock source */
|
||
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
||
|
|
8001ea4: 4b8f ldr r3, [pc, #572] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001ea6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001eaa: f023 020c bic.w r2, r3, #12
|
||
|
|
8001eae: 687b ldr r3, [r7, #4]
|
||
|
|
8001eb0: 6bdb ldr r3, [r3, #60] ; 0x3c
|
||
|
|
8001eb2: 498c ldr r1, [pc, #560] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001eb4: 4313 orrs r3, r2
|
||
|
|
8001eb6: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(USART3)
|
||
|
|
|
||
|
|
/*-------------------------- USART3 clock source configuration -------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
||
|
|
8001eba: 687b ldr r3, [r7, #4]
|
||
|
|
8001ebc: 681b ldr r3, [r3, #0]
|
||
|
|
8001ebe: f003 0304 and.w r3, r3, #4
|
||
|
|
8001ec2: 2b00 cmp r3, #0
|
||
|
|
8001ec4: d00a beq.n 8001edc <HAL_RCCEx_PeriphCLKConfig+0x2e4>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the USART3 clock source */
|
||
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
||
|
|
8001ec6: 4b87 ldr r3, [pc, #540] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001ec8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001ecc: f023 0230 bic.w r2, r3, #48 ; 0x30
|
||
|
|
8001ed0: 687b ldr r3, [r7, #4]
|
||
|
|
8001ed2: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8001ed4: 4983 ldr r1, [pc, #524] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001ed6: 4313 orrs r3, r2
|
||
|
|
8001ed8: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
#endif /* USART3 */
|
||
|
|
|
||
|
|
#if defined(UART4)
|
||
|
|
|
||
|
|
/*-------------------------- UART4 clock source configuration --------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
||
|
|
8001edc: 687b ldr r3, [r7, #4]
|
||
|
|
8001ede: 681b ldr r3, [r3, #0]
|
||
|
|
8001ee0: f003 0308 and.w r3, r3, #8
|
||
|
|
8001ee4: 2b00 cmp r3, #0
|
||
|
|
8001ee6: d00a beq.n 8001efe <HAL_RCCEx_PeriphCLKConfig+0x306>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the UART4 clock source */
|
||
|
|
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
||
|
|
8001ee8: 4b7e ldr r3, [pc, #504] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001eea: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001eee: f023 02c0 bic.w r2, r3, #192 ; 0xc0
|
||
|
|
8001ef2: 687b ldr r3, [r7, #4]
|
||
|
|
8001ef4: 6c5b ldr r3, [r3, #68] ; 0x44
|
||
|
|
8001ef6: 497b ldr r1, [pc, #492] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001ef8: 4313 orrs r3, r2
|
||
|
|
8001efa: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
#endif /* UART4 */
|
||
|
|
|
||
|
|
#if defined(UART5)
|
||
|
|
|
||
|
|
/*-------------------------- UART5 clock source configuration --------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
|
||
|
|
8001efe: 687b ldr r3, [r7, #4]
|
||
|
|
8001f00: 681b ldr r3, [r3, #0]
|
||
|
|
8001f02: f003 0310 and.w r3, r3, #16
|
||
|
|
8001f06: 2b00 cmp r3, #0
|
||
|
|
8001f08: d00a beq.n 8001f20 <HAL_RCCEx_PeriphCLKConfig+0x328>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the UART5 clock source */
|
||
|
|
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
|
||
|
|
8001f0a: 4b76 ldr r3, [pc, #472] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001f0c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001f10: f423 7240 bic.w r2, r3, #768 ; 0x300
|
||
|
|
8001f14: 687b ldr r3, [r7, #4]
|
||
|
|
8001f16: 6c9b ldr r3, [r3, #72] ; 0x48
|
||
|
|
8001f18: 4972 ldr r1, [pc, #456] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001f1a: 4313 orrs r3, r2
|
||
|
|
8001f1c: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* UART5 */
|
||
|
|
|
||
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
||
|
|
8001f20: 687b ldr r3, [r7, #4]
|
||
|
|
8001f22: 681b ldr r3, [r3, #0]
|
||
|
|
8001f24: f003 0320 and.w r3, r3, #32
|
||
|
|
8001f28: 2b00 cmp r3, #0
|
||
|
|
8001f2a: d00a beq.n 8001f42 <HAL_RCCEx_PeriphCLKConfig+0x34a>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the LPUART1 clock source */
|
||
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
||
|
|
8001f2c: 4b6d ldr r3, [pc, #436] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001f2e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001f32: f423 6240 bic.w r2, r3, #3072 ; 0xc00
|
||
|
|
8001f36: 687b ldr r3, [r7, #4]
|
||
|
|
8001f38: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8001f3a: 496a ldr r1, [pc, #424] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001f3c: 4313 orrs r3, r2
|
||
|
|
8001f3e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- LPTIM1 clock source configuration -------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
||
|
|
8001f42: 687b ldr r3, [r7, #4]
|
||
|
|
8001f44: 681b ldr r3, [r3, #0]
|
||
|
|
8001f46: f403 7300 and.w r3, r3, #512 ; 0x200
|
||
|
|
8001f4a: 2b00 cmp r3, #0
|
||
|
|
8001f4c: d00a beq.n 8001f64 <HAL_RCCEx_PeriphCLKConfig+0x36c>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
|
||
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
||
|
|
8001f4e: 4b65 ldr r3, [pc, #404] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001f50: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001f54: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
|
||
|
|
8001f58: 687b ldr r3, [r7, #4]
|
||
|
|
8001f5a: 6ddb ldr r3, [r3, #92] ; 0x5c
|
||
|
|
8001f5c: 4961 ldr r1, [pc, #388] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001f5e: 4313 orrs r3, r2
|
||
|
|
8001f60: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- LPTIM2 clock source configuration -------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
|
||
|
|
8001f64: 687b ldr r3, [r7, #4]
|
||
|
|
8001f66: 681b ldr r3, [r3, #0]
|
||
|
|
8001f68: f403 6380 and.w r3, r3, #1024 ; 0x400
|
||
|
|
8001f6c: 2b00 cmp r3, #0
|
||
|
|
8001f6e: d00a beq.n 8001f86 <HAL_RCCEx_PeriphCLKConfig+0x38e>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
|
||
|
|
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
|
||
|
|
8001f70: 4b5c ldr r3, [pc, #368] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001f72: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001f76: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
|
||
|
|
8001f7a: 687b ldr r3, [r7, #4]
|
||
|
|
8001f7c: 6e1b ldr r3, [r3, #96] ; 0x60
|
||
|
|
8001f7e: 4959 ldr r1, [pc, #356] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001f80: 4313 orrs r3, r2
|
||
|
|
8001f82: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
||
|
|
8001f86: 687b ldr r3, [r7, #4]
|
||
|
|
8001f88: 681b ldr r3, [r3, #0]
|
||
|
|
8001f8a: f003 0340 and.w r3, r3, #64 ; 0x40
|
||
|
|
8001f8e: 2b00 cmp r3, #0
|
||
|
|
8001f90: d00a beq.n 8001fa8 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the I2C1 clock source */
|
||
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
||
|
|
8001f92: 4b54 ldr r3, [pc, #336] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001f94: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001f98: f423 5240 bic.w r2, r3, #12288 ; 0x3000
|
||
|
|
8001f9c: 687b ldr r3, [r7, #4]
|
||
|
|
8001f9e: 6d1b ldr r3, [r3, #80] ; 0x50
|
||
|
|
8001fa0: 4950 ldr r1, [pc, #320] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001fa2: 4313 orrs r3, r2
|
||
|
|
8001fa4: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(I2C2)
|
||
|
|
|
||
|
|
/*-------------------------- I2C2 clock source configuration ---------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
||
|
|
8001fa8: 687b ldr r3, [r7, #4]
|
||
|
|
8001faa: 681b ldr r3, [r3, #0]
|
||
|
|
8001fac: f003 0380 and.w r3, r3, #128 ; 0x80
|
||
|
|
8001fb0: 2b00 cmp r3, #0
|
||
|
|
8001fb2: d00a beq.n 8001fca <HAL_RCCEx_PeriphCLKConfig+0x3d2>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the I2C2 clock source */
|
||
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
||
|
|
8001fb4: 4b4b ldr r3, [pc, #300] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001fb6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001fba: f423 4240 bic.w r2, r3, #49152 ; 0xc000
|
||
|
|
8001fbe: 687b ldr r3, [r7, #4]
|
||
|
|
8001fc0: 6d5b ldr r3, [r3, #84] ; 0x54
|
||
|
|
8001fc2: 4948 ldr r1, [pc, #288] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001fc4: 4313 orrs r3, r2
|
||
|
|
8001fc6: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* I2C2 */
|
||
|
|
|
||
|
|
/*-------------------------- I2C3 clock source configuration ---------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
||
|
|
8001fca: 687b ldr r3, [r7, #4]
|
||
|
|
8001fcc: 681b ldr r3, [r3, #0]
|
||
|
|
8001fce: f403 7380 and.w r3, r3, #256 ; 0x100
|
||
|
|
8001fd2: 2b00 cmp r3, #0
|
||
|
|
8001fd4: d00a beq.n 8001fec <HAL_RCCEx_PeriphCLKConfig+0x3f4>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the I2C3 clock source */
|
||
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
||
|
|
8001fd6: 4b43 ldr r3, [pc, #268] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001fd8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001fdc: f423 3240 bic.w r2, r3, #196608 ; 0x30000
|
||
|
|
8001fe0: 687b ldr r3, [r7, #4]
|
||
|
|
8001fe2: 6d9b ldr r3, [r3, #88] ; 0x58
|
||
|
|
8001fe4: 493f ldr r1, [pc, #252] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001fe6: 4313 orrs r3, r2
|
||
|
|
8001fe8: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
#endif /* I2C4 */
|
||
|
|
|
||
|
|
#if defined(USB_OTG_FS) || defined(USB)
|
||
|
|
|
||
|
|
/*-------------------------- USB clock source configuration ----------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
||
|
|
8001fec: 687b ldr r3, [r7, #4]
|
||
|
|
8001fee: 681b ldr r3, [r3, #0]
|
||
|
|
8001ff0: f403 5300 and.w r3, r3, #8192 ; 0x2000
|
||
|
|
8001ff4: 2b00 cmp r3, #0
|
||
|
|
8001ff6: d028 beq.n 800204a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
||
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
||
|
|
8001ff8: 4b3a ldr r3, [pc, #232] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8001ffa: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8001ffe: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
|
||
|
|
8002002: 687b ldr r3, [r7, #4]
|
||
|
|
8002004: 6edb ldr r3, [r3, #108] ; 0x6c
|
||
|
|
8002006: 4937 ldr r1, [pc, #220] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8002008: 4313 orrs r3, r2
|
||
|
|
800200a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
|
||
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
|
||
|
|
800200e: 687b ldr r3, [r7, #4]
|
||
|
|
8002010: 6edb ldr r3, [r3, #108] ; 0x6c
|
||
|
|
8002012: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
|
||
|
|
8002016: d106 bne.n 8002026 <HAL_RCCEx_PeriphCLKConfig+0x42e>
|
||
|
|
{
|
||
|
|
/* Enable PLL48M1CLK output clock */
|
||
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
||
|
|
8002018: 4b32 ldr r3, [pc, #200] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
800201a: 68db ldr r3, [r3, #12]
|
||
|
|
800201c: 4a31 ldr r2, [pc, #196] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
800201e: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
|
||
|
|
8002022: 60d3 str r3, [r2, #12]
|
||
|
|
8002024: e011 b.n 800204a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
||
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
|
||
|
|
8002026: 687b ldr r3, [r7, #4]
|
||
|
|
8002028: 6edb ldr r3, [r3, #108] ; 0x6c
|
||
|
|
800202a: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
|
||
|
|
800202e: d10c bne.n 800204a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
||
|
|
{
|
||
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
||
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
||
|
|
8002030: 687b ldr r3, [r7, #4]
|
||
|
|
8002032: 3304 adds r3, #4
|
||
|
|
8002034: 2101 movs r1, #1
|
||
|
|
8002036: 4618 mov r0, r3
|
||
|
|
8002038: f000 f8c8 bl 80021cc <RCCEx_PLLSAI1_Config>
|
||
|
|
800203c: 4603 mov r3, r0
|
||
|
|
800203e: 74fb strb r3, [r7, #19]
|
||
|
|
|
||
|
|
if(ret != HAL_OK)
|
||
|
|
8002040: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8002042: 2b00 cmp r3, #0
|
||
|
|
8002044: d001 beq.n 800204a <HAL_RCCEx_PeriphCLKConfig+0x452>
|
||
|
|
{
|
||
|
|
/* set overall return value */
|
||
|
|
status = ret;
|
||
|
|
8002046: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8002048: 74bb strb r3, [r7, #18]
|
||
|
|
#endif /* USB_OTG_FS || USB */
|
||
|
|
|
||
|
|
#if defined(SDMMC1)
|
||
|
|
|
||
|
|
/*-------------------------- SDMMC1 clock source configuration -------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
|
||
|
|
800204a: 687b ldr r3, [r7, #4]
|
||
|
|
800204c: 681b ldr r3, [r3, #0]
|
||
|
|
800204e: f403 2300 and.w r3, r3, #524288 ; 0x80000
|
||
|
|
8002052: 2b00 cmp r3, #0
|
||
|
|
8002054: d028 beq.n 80020a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
|
||
|
|
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
|
||
|
|
8002056: 4b23 ldr r3, [pc, #140] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8002058: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
800205c: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
|
||
|
|
8002060: 687b ldr r3, [r7, #4]
|
||
|
|
8002062: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
8002064: 491f ldr r1, [pc, #124] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8002066: 4313 orrs r3, r2
|
||
|
|
8002068: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
|
||
|
|
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
|
||
|
|
800206c: 687b ldr r3, [r7, #4]
|
||
|
|
800206e: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
8002070: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
|
||
|
|
8002074: d106 bne.n 8002084 <HAL_RCCEx_PeriphCLKConfig+0x48c>
|
||
|
|
{
|
||
|
|
/* Enable PLL48M1CLK output clock */
|
||
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
||
|
|
8002076: 4b1b ldr r3, [pc, #108] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
8002078: 68db ldr r3, [r3, #12]
|
||
|
|
800207a: 4a1a ldr r2, [pc, #104] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
800207c: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
|
||
|
|
8002080: 60d3 str r3, [r2, #12]
|
||
|
|
8002082: e011 b.n 80020a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
||
|
|
{
|
||
|
|
/* Enable PLLSAI3CLK output */
|
||
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
|
||
|
|
8002084: 687b ldr r3, [r7, #4]
|
||
|
|
8002086: 6f1b ldr r3, [r3, #112] ; 0x70
|
||
|
|
8002088: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
|
||
|
|
800208c: d10c bne.n 80020a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
||
|
|
{
|
||
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
||
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
||
|
|
800208e: 687b ldr r3, [r7, #4]
|
||
|
|
8002090: 3304 adds r3, #4
|
||
|
|
8002092: 2101 movs r1, #1
|
||
|
|
8002094: 4618 mov r0, r3
|
||
|
|
8002096: f000 f899 bl 80021cc <RCCEx_PLLSAI1_Config>
|
||
|
|
800209a: 4603 mov r3, r0
|
||
|
|
800209c: 74fb strb r3, [r7, #19]
|
||
|
|
|
||
|
|
if(ret != HAL_OK)
|
||
|
|
800209e: 7cfb ldrb r3, [r7, #19]
|
||
|
|
80020a0: 2b00 cmp r3, #0
|
||
|
|
80020a2: d001 beq.n 80020a8 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
||
|
|
{
|
||
|
|
/* set overall return value */
|
||
|
|
status = ret;
|
||
|
|
80020a4: 7cfb ldrb r3, [r7, #19]
|
||
|
|
80020a6: 74bb strb r3, [r7, #18]
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* SDMMC1 */
|
||
|
|
|
||
|
|
/*-------------------------- RNG clock source configuration ----------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
||
|
|
80020a8: 687b ldr r3, [r7, #4]
|
||
|
|
80020aa: 681b ldr r3, [r3, #0]
|
||
|
|
80020ac: f403 2380 and.w r3, r3, #262144 ; 0x40000
|
||
|
|
80020b0: 2b00 cmp r3, #0
|
||
|
|
80020b2: d02b beq.n 800210c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
||
|
|
{
|
||
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
||
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
||
|
|
80020b4: 4b0b ldr r3, [pc, #44] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
80020b6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
80020ba: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
|
||
|
|
80020be: 687b ldr r3, [r7, #4]
|
||
|
|
80020c0: 6f5b ldr r3, [r3, #116] ; 0x74
|
||
|
|
80020c2: 4908 ldr r1, [pc, #32] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
80020c4: 4313 orrs r3, r2
|
||
|
|
80020c6: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
|
||
|
|
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
||
|
|
80020ca: 687b ldr r3, [r7, #4]
|
||
|
|
80020cc: 6f5b ldr r3, [r3, #116] ; 0x74
|
||
|
|
80020ce: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
|
||
|
|
80020d2: d109 bne.n 80020e8 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
|
||
|
|
{
|
||
|
|
/* Enable PLL48M1CLK output clock */
|
||
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
||
|
|
80020d4: 4b03 ldr r3, [pc, #12] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
80020d6: 68db ldr r3, [r3, #12]
|
||
|
|
80020d8: 4a02 ldr r2, [pc, #8] ; (80020e4 <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
||
|
|
80020da: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
|
||
|
|
80020de: 60d3 str r3, [r2, #12]
|
||
|
|
80020e0: e014 b.n 800210c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
||
|
|
80020e2: bf00 nop
|
||
|
|
80020e4: 40021000 .word 0x40021000
|
||
|
|
}
|
||
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
||
|
|
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
|
||
|
|
80020e8: 687b ldr r3, [r7, #4]
|
||
|
|
80020ea: 6f5b ldr r3, [r3, #116] ; 0x74
|
||
|
|
80020ec: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
|
||
|
|
80020f0: d10c bne.n 800210c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
||
|
|
{
|
||
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
||
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
||
|
|
80020f2: 687b ldr r3, [r7, #4]
|
||
|
|
80020f4: 3304 adds r3, #4
|
||
|
|
80020f6: 2101 movs r1, #1
|
||
|
|
80020f8: 4618 mov r0, r3
|
||
|
|
80020fa: f000 f867 bl 80021cc <RCCEx_PLLSAI1_Config>
|
||
|
|
80020fe: 4603 mov r3, r0
|
||
|
|
8002100: 74fb strb r3, [r7, #19]
|
||
|
|
|
||
|
|
if(ret != HAL_OK)
|
||
|
|
8002102: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8002104: 2b00 cmp r3, #0
|
||
|
|
8002106: d001 beq.n 800210c <HAL_RCCEx_PeriphCLKConfig+0x514>
|
||
|
|
{
|
||
|
|
/* set overall return value */
|
||
|
|
status = ret;
|
||
|
|
8002108: 7cfb ldrb r3, [r7, #19]
|
||
|
|
800210a: 74bb strb r3, [r7, #18]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*-------------------------- ADC clock source configuration ----------------------*/
|
||
|
|
#if !defined(STM32L412xx) && !defined(STM32L422xx)
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
||
|
|
800210c: 687b ldr r3, [r7, #4]
|
||
|
|
800210e: 681b ldr r3, [r3, #0]
|
||
|
|
8002110: f403 4380 and.w r3, r3, #16384 ; 0x4000
|
||
|
|
8002114: 2b00 cmp r3, #0
|
||
|
|
8002116: d02f beq.n 8002178 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
||
|
|
|
||
|
|
/* Configure the ADC interface clock source */
|
||
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
||
|
|
8002118: 4b2b ldr r3, [pc, #172] ; (80021c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
||
|
|
800211a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
800211e: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000
|
||
|
|
8002122: 687b ldr r3, [r7, #4]
|
||
|
|
8002124: 6f9b ldr r3, [r3, #120] ; 0x78
|
||
|
|
8002126: 4928 ldr r1, [pc, #160] ; (80021c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
||
|
|
8002128: 4313 orrs r3, r2
|
||
|
|
800212a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
|
||
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
||
|
|
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
|
||
|
|
800212e: 687b ldr r3, [r7, #4]
|
||
|
|
8002130: 6f9b ldr r3, [r3, #120] ; 0x78
|
||
|
|
8002132: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
|
||
|
|
8002136: d10d bne.n 8002154 <HAL_RCCEx_PeriphCLKConfig+0x55c>
|
||
|
|
{
|
||
|
|
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
|
||
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
|
||
|
|
8002138: 687b ldr r3, [r7, #4]
|
||
|
|
800213a: 3304 adds r3, #4
|
||
|
|
800213c: 2102 movs r1, #2
|
||
|
|
800213e: 4618 mov r0, r3
|
||
|
|
8002140: f000 f844 bl 80021cc <RCCEx_PLLSAI1_Config>
|
||
|
|
8002144: 4603 mov r3, r0
|
||
|
|
8002146: 74fb strb r3, [r7, #19]
|
||
|
|
|
||
|
|
if(ret != HAL_OK)
|
||
|
|
8002148: 7cfb ldrb r3, [r7, #19]
|
||
|
|
800214a: 2b00 cmp r3, #0
|
||
|
|
800214c: d014 beq.n 8002178 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
||
|
|
{
|
||
|
|
/* set overall return value */
|
||
|
|
status = ret;
|
||
|
|
800214e: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8002150: 74bb strb r3, [r7, #18]
|
||
|
|
8002152: e011 b.n 8002178 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
||
|
|
}
|
||
|
|
#endif /* RCC_PLLSAI1_SUPPORT */
|
||
|
|
|
||
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
|
||
|
|
|
||
|
|
else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
|
||
|
|
8002154: 687b ldr r3, [r7, #4]
|
||
|
|
8002156: 6f9b ldr r3, [r3, #120] ; 0x78
|
||
|
|
8002158: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
||
|
|
800215c: d10c bne.n 8002178 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
||
|
|
{
|
||
|
|
/* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
|
||
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
|
||
|
|
800215e: 687b ldr r3, [r7, #4]
|
||
|
|
8002160: 3320 adds r3, #32
|
||
|
|
8002162: 2102 movs r1, #2
|
||
|
|
8002164: 4618 mov r0, r3
|
||
|
|
8002166: f000 f925 bl 80023b4 <RCCEx_PLLSAI2_Config>
|
||
|
|
800216a: 4603 mov r3, r0
|
||
|
|
800216c: 74fb strb r3, [r7, #19]
|
||
|
|
|
||
|
|
if(ret != HAL_OK)
|
||
|
|
800216e: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8002170: 2b00 cmp r3, #0
|
||
|
|
8002172: d001 beq.n 8002178 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
||
|
|
{
|
||
|
|
/* set overall return value */
|
||
|
|
status = ret;
|
||
|
|
8002174: 7cfb ldrb r3, [r7, #19]
|
||
|
|
8002176: 74bb strb r3, [r7, #18]
|
||
|
|
#endif /* !STM32L412xx && !STM32L422xx */
|
||
|
|
|
||
|
|
#if defined(SWPMI1)
|
||
|
|
|
||
|
|
/*-------------------------- SWPMI1 clock source configuration -------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
|
||
|
|
8002178: 687b ldr r3, [r7, #4]
|
||
|
|
800217a: 681b ldr r3, [r3, #0]
|
||
|
|
800217c: f403 4300 and.w r3, r3, #32768 ; 0x8000
|
||
|
|
8002180: 2b00 cmp r3, #0
|
||
|
|
8002182: d00a beq.n 800219a <HAL_RCCEx_PeriphCLKConfig+0x5a2>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the SWPMI1 clock source */
|
||
|
|
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
|
||
|
|
8002184: 4b10 ldr r3, [pc, #64] ; (80021c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
||
|
|
8002186: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
800218a: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000
|
||
|
|
800218e: 687b ldr r3, [r7, #4]
|
||
|
|
8002190: 6fdb ldr r3, [r3, #124] ; 0x7c
|
||
|
|
8002192: 490d ldr r1, [pc, #52] ; (80021c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
||
|
|
8002194: 4313 orrs r3, r2
|
||
|
|
8002196: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
#endif /* SWPMI1 */
|
||
|
|
|
||
|
|
#if defined(DFSDM1_Filter0)
|
||
|
|
|
||
|
|
/*-------------------------- DFSDM1 clock source configuration -------------------*/
|
||
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
|
||
|
|
800219a: 687b ldr r3, [r7, #4]
|
||
|
|
800219c: 681b ldr r3, [r3, #0]
|
||
|
|
800219e: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
||
|
|
80021a2: 2b00 cmp r3, #0
|
||
|
|
80021a4: d00b beq.n 80021be <HAL_RCCEx_PeriphCLKConfig+0x5c6>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
|
||
|
|
|
||
|
|
/* Configure the DFSDM1 interface clock source */
|
||
|
|
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
|
||
|
|
80021a6: 4b08 ldr r3, [pc, #32] ; (80021c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
||
|
|
80021a8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
80021ac: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000
|
||
|
|
80021b0: 687b ldr r3, [r7, #4]
|
||
|
|
80021b2: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
||
|
|
80021b6: 4904 ldr r1, [pc, #16] ; (80021c8 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
||
|
|
80021b8: 4313 orrs r3, r2
|
||
|
|
80021ba: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* OCTOSPI1 || OCTOSPI2 */
|
||
|
|
|
||
|
|
return status;
|
||
|
|
80021be: 7cbb ldrb r3, [r7, #18]
|
||
|
|
}
|
||
|
|
80021c0: 4618 mov r0, r3
|
||
|
|
80021c2: 3718 adds r7, #24
|
||
|
|
80021c4: 46bd mov sp, r7
|
||
|
|
80021c6: bd80 pop {r7, pc}
|
||
|
|
80021c8: 40021000 .word 0x40021000
|
||
|
|
|
||
|
|
080021cc <RCCEx_PLLSAI1_Config>:
|
||
|
|
* @note PLLSAI1 is temporary disable to apply new parameters
|
||
|
|
*
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
|
||
|
|
{
|
||
|
|
80021cc: b580 push {r7, lr}
|
||
|
|
80021ce: b084 sub sp, #16
|
||
|
|
80021d0: af00 add r7, sp, #0
|
||
|
|
80021d2: 6078 str r0, [r7, #4]
|
||
|
|
80021d4: 6039 str r1, [r7, #0]
|
||
|
|
uint32_t tickstart;
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
80021d6: 2300 movs r3, #0
|
||
|
|
80021d8: 73fb strb r3, [r7, #15]
|
||
|
|
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
|
||
|
|
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
|
||
|
|
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
|
||
|
|
|
||
|
|
/* Check that PLLSAI1 clock source and divider M can be applied */
|
||
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
||
|
|
80021da: 4b75 ldr r3, [pc, #468] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
80021dc: 68db ldr r3, [r3, #12]
|
||
|
|
80021de: f003 0303 and.w r3, r3, #3
|
||
|
|
80021e2: 2b00 cmp r3, #0
|
||
|
|
80021e4: d018 beq.n 8002218 <RCCEx_PLLSAI1_Config+0x4c>
|
||
|
|
{
|
||
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
||
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
|
||
|
|
80021e6: 4b72 ldr r3, [pc, #456] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
80021e8: 68db ldr r3, [r3, #12]
|
||
|
|
80021ea: f003 0203 and.w r2, r3, #3
|
||
|
|
80021ee: 687b ldr r3, [r7, #4]
|
||
|
|
80021f0: 681b ldr r3, [r3, #0]
|
||
|
|
80021f2: 429a cmp r2, r3
|
||
|
|
80021f4: d10d bne.n 8002212 <RCCEx_PLLSAI1_Config+0x46>
|
||
|
|
||
|
||
|
|
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
|
||
|
|
80021f6: 687b ldr r3, [r7, #4]
|
||
|
|
80021f8: 681b ldr r3, [r3, #0]
|
||
|
|
||
|
||
|
|
80021fa: 2b00 cmp r3, #0
|
||
|
|
80021fc: d009 beq.n 8002212 <RCCEx_PLLSAI1_Config+0x46>
|
||
|
|
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
||
|
|
||
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
|
||
|
|
80021fe: 4b6c ldr r3, [pc, #432] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002200: 68db ldr r3, [r3, #12]
|
||
|
|
8002202: 091b lsrs r3, r3, #4
|
||
|
|
8002204: f003 0307 and.w r3, r3, #7
|
||
|
|
8002208: 1c5a adds r2, r3, #1
|
||
|
|
800220a: 687b ldr r3, [r7, #4]
|
||
|
|
800220c: 685b ldr r3, [r3, #4]
|
||
|
|
||
|
||
|
|
800220e: 429a cmp r2, r3
|
||
|
|
8002210: d047 beq.n 80022a2 <RCCEx_PLLSAI1_Config+0xd6>
|
||
|
|
#endif
|
||
|
|
)
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
8002212: 2301 movs r3, #1
|
||
|
|
8002214: 73fb strb r3, [r7, #15]
|
||
|
|
8002216: e044 b.n 80022a2 <RCCEx_PLLSAI1_Config+0xd6>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Check PLLSAI1 clock source availability */
|
||
|
|
switch(PllSai1->PLLSAI1Source)
|
||
|
|
8002218: 687b ldr r3, [r7, #4]
|
||
|
|
800221a: 681b ldr r3, [r3, #0]
|
||
|
|
800221c: 2b03 cmp r3, #3
|
||
|
|
800221e: d018 beq.n 8002252 <RCCEx_PLLSAI1_Config+0x86>
|
||
|
|
8002220: 2b03 cmp r3, #3
|
||
|
|
8002222: d825 bhi.n 8002270 <RCCEx_PLLSAI1_Config+0xa4>
|
||
|
|
8002224: 2b01 cmp r3, #1
|
||
|
|
8002226: d002 beq.n 800222e <RCCEx_PLLSAI1_Config+0x62>
|
||
|
|
8002228: 2b02 cmp r3, #2
|
||
|
|
800222a: d009 beq.n 8002240 <RCCEx_PLLSAI1_Config+0x74>
|
||
|
|
800222c: e020 b.n 8002270 <RCCEx_PLLSAI1_Config+0xa4>
|
||
|
|
{
|
||
|
|
case RCC_PLLSOURCE_MSI:
|
||
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
||
|
|
800222e: 4b60 ldr r3, [pc, #384] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002230: 681b ldr r3, [r3, #0]
|
||
|
|
8002232: f003 0302 and.w r3, r3, #2
|
||
|
|
8002236: 2b00 cmp r3, #0
|
||
|
|
8002238: d11d bne.n 8002276 <RCCEx_PLLSAI1_Config+0xaa>
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
800223a: 2301 movs r3, #1
|
||
|
|
800223c: 73fb strb r3, [r7, #15]
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
800223e: e01a b.n 8002276 <RCCEx_PLLSAI1_Config+0xaa>
|
||
|
|
case RCC_PLLSOURCE_HSI:
|
||
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
||
|
|
8002240: 4b5b ldr r3, [pc, #364] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002242: 681b ldr r3, [r3, #0]
|
||
|
|
8002244: f403 6380 and.w r3, r3, #1024 ; 0x400
|
||
|
|
8002248: 2b00 cmp r3, #0
|
||
|
|
800224a: d116 bne.n 800227a <RCCEx_PLLSAI1_Config+0xae>
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
800224c: 2301 movs r3, #1
|
||
|
|
800224e: 73fb strb r3, [r7, #15]
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
8002250: e013 b.n 800227a <RCCEx_PLLSAI1_Config+0xae>
|
||
|
|
case RCC_PLLSOURCE_HSE:
|
||
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
||
|
|
8002252: 4b57 ldr r3, [pc, #348] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002254: 681b ldr r3, [r3, #0]
|
||
|
|
8002256: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
||
|
|
800225a: 2b00 cmp r3, #0
|
||
|
|
800225c: d10f bne.n 800227e <RCCEx_PLLSAI1_Config+0xb2>
|
||
|
|
{
|
||
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
||
|
|
800225e: 4b54 ldr r3, [pc, #336] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002260: 681b ldr r3, [r3, #0]
|
||
|
|
8002262: f403 2380 and.w r3, r3, #262144 ; 0x40000
|
||
|
|
8002266: 2b00 cmp r3, #0
|
||
|
|
8002268: d109 bne.n 800227e <RCCEx_PLLSAI1_Config+0xb2>
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
800226a: 2301 movs r3, #1
|
||
|
|
800226c: 73fb strb r3, [r7, #15]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
800226e: e006 b.n 800227e <RCCEx_PLLSAI1_Config+0xb2>
|
||
|
|
default:
|
||
|
|
status = HAL_ERROR;
|
||
|
|
8002270: 2301 movs r3, #1
|
||
|
|
8002272: 73fb strb r3, [r7, #15]
|
||
|
|
break;
|
||
|
|
8002274: e004 b.n 8002280 <RCCEx_PLLSAI1_Config+0xb4>
|
||
|
|
break;
|
||
|
|
8002276: bf00 nop
|
||
|
|
8002278: e002 b.n 8002280 <RCCEx_PLLSAI1_Config+0xb4>
|
||
|
|
break;
|
||
|
|
800227a: bf00 nop
|
||
|
|
800227c: e000 b.n 8002280 <RCCEx_PLLSAI1_Config+0xb4>
|
||
|
|
break;
|
||
|
|
800227e: bf00 nop
|
||
|
|
}
|
||
|
|
|
||
|
|
if(status == HAL_OK)
|
||
|
|
8002280: 7bfb ldrb r3, [r7, #15]
|
||
|
|
8002282: 2b00 cmp r3, #0
|
||
|
|
8002284: d10d bne.n 80022a2 <RCCEx_PLLSAI1_Config+0xd6>
|
||
|
|
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
||
|
|
/* Set PLLSAI1 clock source */
|
||
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
|
||
|
|
#else
|
||
|
|
/* Set PLLSAI1 clock source and divider M */
|
||
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
||
|
|
8002286: 4b4a ldr r3, [pc, #296] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002288: 68db ldr r3, [r3, #12]
|
||
|
|
800228a: f023 0273 bic.w r2, r3, #115 ; 0x73
|
||
|
|
800228e: 687b ldr r3, [r7, #4]
|
||
|
|
8002290: 6819 ldr r1, [r3, #0]
|
||
|
|
8002292: 687b ldr r3, [r7, #4]
|
||
|
|
8002294: 685b ldr r3, [r3, #4]
|
||
|
|
8002296: 3b01 subs r3, #1
|
||
|
|
8002298: 011b lsls r3, r3, #4
|
||
|
|
800229a: 430b orrs r3, r1
|
||
|
|
800229c: 4944 ldr r1, [pc, #272] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
800229e: 4313 orrs r3, r2
|
||
|
|
80022a0: 60cb str r3, [r1, #12]
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(status == HAL_OK)
|
||
|
|
80022a2: 7bfb ldrb r3, [r7, #15]
|
||
|
|
80022a4: 2b00 cmp r3, #0
|
||
|
|
80022a6: d17d bne.n 80023a4 <RCCEx_PLLSAI1_Config+0x1d8>
|
||
|
|
{
|
||
|
|
/* Disable the PLLSAI1 */
|
||
|
|
__HAL_RCC_PLLSAI1_DISABLE();
|
||
|
|
80022a8: 4b41 ldr r3, [pc, #260] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
80022aa: 681b ldr r3, [r3, #0]
|
||
|
|
80022ac: 4a40 ldr r2, [pc, #256] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
80022ae: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
|
||
|
|
80022b2: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
80022b4: f7fe fb88 bl 80009c8 <HAL_GetTick>
|
||
|
|
80022b8: 60b8 str r0, [r7, #8]
|
||
|
|
|
||
|
|
/* Wait till PLLSAI1 is ready to be updated */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
||
|
|
80022ba: e009 b.n 80022d0 <RCCEx_PLLSAI1_Config+0x104>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
||
|
|
80022bc: f7fe fb84 bl 80009c8 <HAL_GetTick>
|
||
|
|
80022c0: 4602 mov r2, r0
|
||
|
|
80022c2: 68bb ldr r3, [r7, #8]
|
||
|
|
80022c4: 1ad3 subs r3, r2, r3
|
||
|
|
80022c6: 2b02 cmp r3, #2
|
||
|
|
80022c8: d902 bls.n 80022d0 <RCCEx_PLLSAI1_Config+0x104>
|
||
|
|
{
|
||
|
|
status = HAL_TIMEOUT;
|
||
|
|
80022ca: 2303 movs r3, #3
|
||
|
|
80022cc: 73fb strb r3, [r7, #15]
|
||
|
|
break;
|
||
|
|
80022ce: e005 b.n 80022dc <RCCEx_PLLSAI1_Config+0x110>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
||
|
|
80022d0: 4b37 ldr r3, [pc, #220] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
80022d2: 681b ldr r3, [r3, #0]
|
||
|
|
80022d4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
|
||
|
|
80022d8: 2b00 cmp r3, #0
|
||
|
|
80022da: d1ef bne.n 80022bc <RCCEx_PLLSAI1_Config+0xf0>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(status == HAL_OK)
|
||
|
|
80022dc: 7bfb ldrb r3, [r7, #15]
|
||
|
|
80022de: 2b00 cmp r3, #0
|
||
|
|
80022e0: d160 bne.n 80023a4 <RCCEx_PLLSAI1_Config+0x1d8>
|
||
|
|
{
|
||
|
|
if(Divider == DIVIDER_P_UPDATE)
|
||
|
|
80022e2: 683b ldr r3, [r7, #0]
|
||
|
|
80022e4: 2b00 cmp r3, #0
|
||
|
|
80022e6: d111 bne.n 800230c <RCCEx_PLLSAI1_Config+0x140>
|
||
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
||
|
|
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
|
||
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
||
|
|
(PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
|
||
|
|
#else
|
||
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
||
|
|
80022e8: 4b31 ldr r3, [pc, #196] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
80022ea: 691b ldr r3, [r3, #16]
|
||
|
|
80022ec: f423 331f bic.w r3, r3, #162816 ; 0x27c00
|
||
|
|
80022f0: f423 7340 bic.w r3, r3, #768 ; 0x300
|
||
|
|
80022f4: 687a ldr r2, [r7, #4]
|
||
|
|
80022f6: 6892 ldr r2, [r2, #8]
|
||
|
|
80022f8: 0211 lsls r1, r2, #8
|
||
|
|
80022fa: 687a ldr r2, [r7, #4]
|
||
|
|
80022fc: 68d2 ldr r2, [r2, #12]
|
||
|
|
80022fe: 0912 lsrs r2, r2, #4
|
||
|
|
8002300: 0452 lsls r2, r2, #17
|
||
|
|
8002302: 430a orrs r2, r1
|
||
|
|
8002304: 492a ldr r1, [pc, #168] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002306: 4313 orrs r3, r2
|
||
|
|
8002308: 610b str r3, [r1, #16]
|
||
|
|
800230a: e027 b.n 800235c <RCCEx_PLLSAI1_Config+0x190>
|
||
|
|
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
|
||
|
|
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
||
|
|
|
||
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
||
|
|
}
|
||
|
|
else if(Divider == DIVIDER_Q_UPDATE)
|
||
|
|
800230c: 683b ldr r3, [r7, #0]
|
||
|
|
800230e: 2b01 cmp r3, #1
|
||
|
|
8002310: d112 bne.n 8002338 <RCCEx_PLLSAI1_Config+0x16c>
|
||
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
||
|
|
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
|
||
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
||
|
|
#else
|
||
|
|
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
|
||
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
||
|
|
8002312: 4b27 ldr r3, [pc, #156] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002314: 691b ldr r3, [r3, #16]
|
||
|
|
8002316: f423 03c0 bic.w r3, r3, #6291456 ; 0x600000
|
||
|
|
800231a: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
|
||
|
|
800231e: 687a ldr r2, [r7, #4]
|
||
|
|
8002320: 6892 ldr r2, [r2, #8]
|
||
|
|
8002322: 0211 lsls r1, r2, #8
|
||
|
|
8002324: 687a ldr r2, [r7, #4]
|
||
|
|
8002326: 6912 ldr r2, [r2, #16]
|
||
|
|
8002328: 0852 lsrs r2, r2, #1
|
||
|
|
800232a: 3a01 subs r2, #1
|
||
|
|
800232c: 0552 lsls r2, r2, #21
|
||
|
|
800232e: 430a orrs r2, r1
|
||
|
|
8002330: 491f ldr r1, [pc, #124] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002332: 4313 orrs r3, r2
|
||
|
|
8002334: 610b str r3, [r1, #16]
|
||
|
|
8002336: e011 b.n 800235c <RCCEx_PLLSAI1_Config+0x190>
|
||
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
||
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
|
||
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
||
|
|
#else
|
||
|
|
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
|
||
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
||
|
|
8002338: 4b1d ldr r3, [pc, #116] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
800233a: 691b ldr r3, [r3, #16]
|
||
|
|
800233c: f023 63c0 bic.w r3, r3, #100663296 ; 0x6000000
|
||
|
|
8002340: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
|
||
|
|
8002344: 687a ldr r2, [r7, #4]
|
||
|
|
8002346: 6892 ldr r2, [r2, #8]
|
||
|
|
8002348: 0211 lsls r1, r2, #8
|
||
|
|
800234a: 687a ldr r2, [r7, #4]
|
||
|
|
800234c: 6952 ldr r2, [r2, #20]
|
||
|
|
800234e: 0852 lsrs r2, r2, #1
|
||
|
|
8002350: 3a01 subs r2, #1
|
||
|
|
8002352: 0652 lsls r2, r2, #25
|
||
|
|
8002354: 430a orrs r2, r1
|
||
|
|
8002356: 4916 ldr r1, [pc, #88] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002358: 4313 orrs r3, r2
|
||
|
|
800235a: 610b str r3, [r1, #16]
|
||
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
|
||
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
|
||
|
|
__HAL_RCC_PLLSAI1_ENABLE();
|
||
|
|
800235c: 4b14 ldr r3, [pc, #80] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
800235e: 681b ldr r3, [r3, #0]
|
||
|
|
8002360: 4a13 ldr r2, [pc, #76] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002362: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
|
||
|
|
8002366: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8002368: f7fe fb2e bl 80009c8 <HAL_GetTick>
|
||
|
|
800236c: 60b8 str r0, [r7, #8]
|
||
|
|
|
||
|
|
/* Wait till PLLSAI1 is ready */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
||
|
|
800236e: e009 b.n 8002384 <RCCEx_PLLSAI1_Config+0x1b8>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
||
|
|
8002370: f7fe fb2a bl 80009c8 <HAL_GetTick>
|
||
|
|
8002374: 4602 mov r2, r0
|
||
|
|
8002376: 68bb ldr r3, [r7, #8]
|
||
|
|
8002378: 1ad3 subs r3, r2, r3
|
||
|
|
800237a: 2b02 cmp r3, #2
|
||
|
|
800237c: d902 bls.n 8002384 <RCCEx_PLLSAI1_Config+0x1b8>
|
||
|
|
{
|
||
|
|
status = HAL_TIMEOUT;
|
||
|
|
800237e: 2303 movs r3, #3
|
||
|
|
8002380: 73fb strb r3, [r7, #15]
|
||
|
|
break;
|
||
|
|
8002382: e005 b.n 8002390 <RCCEx_PLLSAI1_Config+0x1c4>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
||
|
|
8002384: 4b0a ldr r3, [pc, #40] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002386: 681b ldr r3, [r3, #0]
|
||
|
|
8002388: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
|
||
|
|
800238c: 2b00 cmp r3, #0
|
||
|
|
800238e: d0ef beq.n 8002370 <RCCEx_PLLSAI1_Config+0x1a4>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(status == HAL_OK)
|
||
|
|
8002390: 7bfb ldrb r3, [r7, #15]
|
||
|
|
8002392: 2b00 cmp r3, #0
|
||
|
|
8002394: d106 bne.n 80023a4 <RCCEx_PLLSAI1_Config+0x1d8>
|
||
|
|
{
|
||
|
|
/* Configure the PLLSAI1 Clock output(s) */
|
||
|
|
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
|
||
|
|
8002396: 4b06 ldr r3, [pc, #24] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
8002398: 691a ldr r2, [r3, #16]
|
||
|
|
800239a: 687b ldr r3, [r7, #4]
|
||
|
|
800239c: 699b ldr r3, [r3, #24]
|
||
|
|
800239e: 4904 ldr r1, [pc, #16] ; (80023b0 <RCCEx_PLLSAI1_Config+0x1e4>)
|
||
|
|
80023a0: 4313 orrs r3, r2
|
||
|
|
80023a2: 610b str r3, [r1, #16]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return status;
|
||
|
|
80023a4: 7bfb ldrb r3, [r7, #15]
|
||
|
|
}
|
||
|
|
80023a6: 4618 mov r0, r3
|
||
|
|
80023a8: 3710 adds r7, #16
|
||
|
|
80023aa: 46bd mov sp, r7
|
||
|
|
80023ac: bd80 pop {r7, pc}
|
||
|
|
80023ae: bf00 nop
|
||
|
|
80023b0: 40021000 .word 0x40021000
|
||
|
|
|
||
|
|
080023b4 <RCCEx_PLLSAI2_Config>:
|
||
|
|
* @note PLLSAI2 is temporary disable to apply new parameters
|
||
|
|
*
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
|
||
|
|
{
|
||
|
|
80023b4: b580 push {r7, lr}
|
||
|
|
80023b6: b084 sub sp, #16
|
||
|
|
80023b8: af00 add r7, sp, #0
|
||
|
|
80023ba: 6078 str r0, [r7, #4]
|
||
|
|
80023bc: 6039 str r1, [r7, #0]
|
||
|
|
uint32_t tickstart;
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
80023be: 2300 movs r3, #0
|
||
|
|
80023c0: 73fb strb r3, [r7, #15]
|
||
|
|
assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
|
||
|
|
assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
|
||
|
|
assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
|
||
|
|
|
||
|
|
/* Check that PLLSAI2 clock source and divider M can be applied */
|
||
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
||
|
|
80023c2: 4b6a ldr r3, [pc, #424] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
80023c4: 68db ldr r3, [r3, #12]
|
||
|
|
80023c6: f003 0303 and.w r3, r3, #3
|
||
|
|
80023ca: 2b00 cmp r3, #0
|
||
|
|
80023cc: d018 beq.n 8002400 <RCCEx_PLLSAI2_Config+0x4c>
|
||
|
|
{
|
||
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
||
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
|
||
|
|
80023ce: 4b67 ldr r3, [pc, #412] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
80023d0: 68db ldr r3, [r3, #12]
|
||
|
|
80023d2: f003 0203 and.w r2, r3, #3
|
||
|
|
80023d6: 687b ldr r3, [r7, #4]
|
||
|
|
80023d8: 681b ldr r3, [r3, #0]
|
||
|
|
80023da: 429a cmp r2, r3
|
||
|
|
80023dc: d10d bne.n 80023fa <RCCEx_PLLSAI2_Config+0x46>
|
||
|
|
||
|
||
|
|
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
|
||
|
|
80023de: 687b ldr r3, [r7, #4]
|
||
|
|
80023e0: 681b ldr r3, [r3, #0]
|
||
|
|
||
|
||
|
|
80023e2: 2b00 cmp r3, #0
|
||
|
|
80023e4: d009 beq.n 80023fa <RCCEx_PLLSAI2_Config+0x46>
|
||
|
|
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
||
|
|
||
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
|
||
|
|
80023e6: 4b61 ldr r3, [pc, #388] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
80023e8: 68db ldr r3, [r3, #12]
|
||
|
|
80023ea: 091b lsrs r3, r3, #4
|
||
|
|
80023ec: f003 0307 and.w r3, r3, #7
|
||
|
|
80023f0: 1c5a adds r2, r3, #1
|
||
|
|
80023f2: 687b ldr r3, [r7, #4]
|
||
|
|
80023f4: 685b ldr r3, [r3, #4]
|
||
|
|
||
|
||
|
|
80023f6: 429a cmp r2, r3
|
||
|
|
80023f8: d047 beq.n 800248a <RCCEx_PLLSAI2_Config+0xd6>
|
||
|
|
#endif
|
||
|
|
)
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
80023fa: 2301 movs r3, #1
|
||
|
|
80023fc: 73fb strb r3, [r7, #15]
|
||
|
|
80023fe: e044 b.n 800248a <RCCEx_PLLSAI2_Config+0xd6>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Check PLLSAI2 clock source availability */
|
||
|
|
switch(PllSai2->PLLSAI2Source)
|
||
|
|
8002400: 687b ldr r3, [r7, #4]
|
||
|
|
8002402: 681b ldr r3, [r3, #0]
|
||
|
|
8002404: 2b03 cmp r3, #3
|
||
|
|
8002406: d018 beq.n 800243a <RCCEx_PLLSAI2_Config+0x86>
|
||
|
|
8002408: 2b03 cmp r3, #3
|
||
|
|
800240a: d825 bhi.n 8002458 <RCCEx_PLLSAI2_Config+0xa4>
|
||
|
|
800240c: 2b01 cmp r3, #1
|
||
|
|
800240e: d002 beq.n 8002416 <RCCEx_PLLSAI2_Config+0x62>
|
||
|
|
8002410: 2b02 cmp r3, #2
|
||
|
|
8002412: d009 beq.n 8002428 <RCCEx_PLLSAI2_Config+0x74>
|
||
|
|
8002414: e020 b.n 8002458 <RCCEx_PLLSAI2_Config+0xa4>
|
||
|
|
{
|
||
|
|
case RCC_PLLSOURCE_MSI:
|
||
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
||
|
|
8002416: 4b55 ldr r3, [pc, #340] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
8002418: 681b ldr r3, [r3, #0]
|
||
|
|
800241a: f003 0302 and.w r3, r3, #2
|
||
|
|
800241e: 2b00 cmp r3, #0
|
||
|
|
8002420: d11d bne.n 800245e <RCCEx_PLLSAI2_Config+0xaa>
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
8002422: 2301 movs r3, #1
|
||
|
|
8002424: 73fb strb r3, [r7, #15]
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
8002426: e01a b.n 800245e <RCCEx_PLLSAI2_Config+0xaa>
|
||
|
|
case RCC_PLLSOURCE_HSI:
|
||
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
||
|
|
8002428: 4b50 ldr r3, [pc, #320] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
800242a: 681b ldr r3, [r3, #0]
|
||
|
|
800242c: f403 6380 and.w r3, r3, #1024 ; 0x400
|
||
|
|
8002430: 2b00 cmp r3, #0
|
||
|
|
8002432: d116 bne.n 8002462 <RCCEx_PLLSAI2_Config+0xae>
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
8002434: 2301 movs r3, #1
|
||
|
|
8002436: 73fb strb r3, [r7, #15]
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
8002438: e013 b.n 8002462 <RCCEx_PLLSAI2_Config+0xae>
|
||
|
|
case RCC_PLLSOURCE_HSE:
|
||
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
||
|
|
800243a: 4b4c ldr r3, [pc, #304] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
800243c: 681b ldr r3, [r3, #0]
|
||
|
|
800243e: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
||
|
|
8002442: 2b00 cmp r3, #0
|
||
|
|
8002444: d10f bne.n 8002466 <RCCEx_PLLSAI2_Config+0xb2>
|
||
|
|
{
|
||
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
||
|
|
8002446: 4b49 ldr r3, [pc, #292] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
8002448: 681b ldr r3, [r3, #0]
|
||
|
|
800244a: f403 2380 and.w r3, r3, #262144 ; 0x40000
|
||
|
|
800244e: 2b00 cmp r3, #0
|
||
|
|
8002450: d109 bne.n 8002466 <RCCEx_PLLSAI2_Config+0xb2>
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
8002452: 2301 movs r3, #1
|
||
|
|
8002454: 73fb strb r3, [r7, #15]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
8002456: e006 b.n 8002466 <RCCEx_PLLSAI2_Config+0xb2>
|
||
|
|
default:
|
||
|
|
status = HAL_ERROR;
|
||
|
|
8002458: 2301 movs r3, #1
|
||
|
|
800245a: 73fb strb r3, [r7, #15]
|
||
|
|
break;
|
||
|
|
800245c: e004 b.n 8002468 <RCCEx_PLLSAI2_Config+0xb4>
|
||
|
|
break;
|
||
|
|
800245e: bf00 nop
|
||
|
|
8002460: e002 b.n 8002468 <RCCEx_PLLSAI2_Config+0xb4>
|
||
|
|
break;
|
||
|
|
8002462: bf00 nop
|
||
|
|
8002464: e000 b.n 8002468 <RCCEx_PLLSAI2_Config+0xb4>
|
||
|
|
break;
|
||
|
|
8002466: bf00 nop
|
||
|
|
}
|
||
|
|
|
||
|
|
if(status == HAL_OK)
|
||
|
|
8002468: 7bfb ldrb r3, [r7, #15]
|
||
|
|
800246a: 2b00 cmp r3, #0
|
||
|
|
800246c: d10d bne.n 800248a <RCCEx_PLLSAI2_Config+0xd6>
|
||
|
|
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
||
|
|
/* Set PLLSAI2 clock source */
|
||
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
|
||
|
|
#else
|
||
|
|
/* Set PLLSAI2 clock source and divider M */
|
||
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
||
|
|
800246e: 4b3f ldr r3, [pc, #252] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
8002470: 68db ldr r3, [r3, #12]
|
||
|
|
8002472: f023 0273 bic.w r2, r3, #115 ; 0x73
|
||
|
|
8002476: 687b ldr r3, [r7, #4]
|
||
|
|
8002478: 6819 ldr r1, [r3, #0]
|
||
|
|
800247a: 687b ldr r3, [r7, #4]
|
||
|
|
800247c: 685b ldr r3, [r3, #4]
|
||
|
|
800247e: 3b01 subs r3, #1
|
||
|
|
8002480: 011b lsls r3, r3, #4
|
||
|
|
8002482: 430b orrs r3, r1
|
||
|
|
8002484: 4939 ldr r1, [pc, #228] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
8002486: 4313 orrs r3, r2
|
||
|
|
8002488: 60cb str r3, [r1, #12]
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(status == HAL_OK)
|
||
|
|
800248a: 7bfb ldrb r3, [r7, #15]
|
||
|
|
800248c: 2b00 cmp r3, #0
|
||
|
|
800248e: d167 bne.n 8002560 <RCCEx_PLLSAI2_Config+0x1ac>
|
||
|
|
{
|
||
|
|
/* Disable the PLLSAI2 */
|
||
|
|
__HAL_RCC_PLLSAI2_DISABLE();
|
||
|
|
8002490: 4b36 ldr r3, [pc, #216] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
8002492: 681b ldr r3, [r3, #0]
|
||
|
|
8002494: 4a35 ldr r2, [pc, #212] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
8002496: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
800249a: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
800249c: f7fe fa94 bl 80009c8 <HAL_GetTick>
|
||
|
|
80024a0: 60b8 str r0, [r7, #8]
|
||
|
|
|
||
|
|
/* Wait till PLLSAI2 is ready to be updated */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
||
|
|
80024a2: e009 b.n 80024b8 <RCCEx_PLLSAI2_Config+0x104>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
||
|
|
80024a4: f7fe fa90 bl 80009c8 <HAL_GetTick>
|
||
|
|
80024a8: 4602 mov r2, r0
|
||
|
|
80024aa: 68bb ldr r3, [r7, #8]
|
||
|
|
80024ac: 1ad3 subs r3, r2, r3
|
||
|
|
80024ae: 2b02 cmp r3, #2
|
||
|
|
80024b0: d902 bls.n 80024b8 <RCCEx_PLLSAI2_Config+0x104>
|
||
|
|
{
|
||
|
|
status = HAL_TIMEOUT;
|
||
|
|
80024b2: 2303 movs r3, #3
|
||
|
|
80024b4: 73fb strb r3, [r7, #15]
|
||
|
|
break;
|
||
|
|
80024b6: e005 b.n 80024c4 <RCCEx_PLLSAI2_Config+0x110>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
||
|
|
80024b8: 4b2c ldr r3, [pc, #176] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
80024ba: 681b ldr r3, [r3, #0]
|
||
|
|
80024bc: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
|
||
|
|
80024c0: 2b00 cmp r3, #0
|
||
|
|
80024c2: d1ef bne.n 80024a4 <RCCEx_PLLSAI2_Config+0xf0>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(status == HAL_OK)
|
||
|
|
80024c4: 7bfb ldrb r3, [r7, #15]
|
||
|
|
80024c6: 2b00 cmp r3, #0
|
||
|
|
80024c8: d14a bne.n 8002560 <RCCEx_PLLSAI2_Config+0x1ac>
|
||
|
|
{
|
||
|
|
if(Divider == DIVIDER_P_UPDATE)
|
||
|
|
80024ca: 683b ldr r3, [r7, #0]
|
||
|
|
80024cc: 2b00 cmp r3, #0
|
||
|
|
80024ce: d111 bne.n 80024f4 <RCCEx_PLLSAI2_Config+0x140>
|
||
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
||
|
|
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
|
||
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
||
|
|
(PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
|
||
|
|
#else
|
||
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
||
|
|
80024d0: 4b26 ldr r3, [pc, #152] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
80024d2: 695b ldr r3, [r3, #20]
|
||
|
|
80024d4: f423 331f bic.w r3, r3, #162816 ; 0x27c00
|
||
|
|
80024d8: f423 7340 bic.w r3, r3, #768 ; 0x300
|
||
|
|
80024dc: 687a ldr r2, [r7, #4]
|
||
|
|
80024de: 6892 ldr r2, [r2, #8]
|
||
|
|
80024e0: 0211 lsls r1, r2, #8
|
||
|
|
80024e2: 687a ldr r2, [r7, #4]
|
||
|
|
80024e4: 68d2 ldr r2, [r2, #12]
|
||
|
|
80024e6: 0912 lsrs r2, r2, #4
|
||
|
|
80024e8: 0452 lsls r2, r2, #17
|
||
|
|
80024ea: 430a orrs r2, r1
|
||
|
|
80024ec: 491f ldr r1, [pc, #124] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
80024ee: 4313 orrs r3, r2
|
||
|
|
80024f0: 614b str r3, [r1, #20]
|
||
|
|
80024f2: e011 b.n 8002518 <RCCEx_PLLSAI2_Config+0x164>
|
||
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
||
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
|
||
|
|
((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
|
||
|
|
#else
|
||
|
|
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
|
||
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
||
|
|
80024f4: 4b1d ldr r3, [pc, #116] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
80024f6: 695b ldr r3, [r3, #20]
|
||
|
|
80024f8: f023 63c0 bic.w r3, r3, #100663296 ; 0x6000000
|
||
|
|
80024fc: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
|
||
|
|
8002500: 687a ldr r2, [r7, #4]
|
||
|
|
8002502: 6892 ldr r2, [r2, #8]
|
||
|
|
8002504: 0211 lsls r1, r2, #8
|
||
|
|
8002506: 687a ldr r2, [r7, #4]
|
||
|
|
8002508: 6912 ldr r2, [r2, #16]
|
||
|
|
800250a: 0852 lsrs r2, r2, #1
|
||
|
|
800250c: 3a01 subs r2, #1
|
||
|
|
800250e: 0652 lsls r2, r2, #25
|
||
|
|
8002510: 430a orrs r2, r1
|
||
|
|
8002512: 4916 ldr r1, [pc, #88] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
8002514: 4313 orrs r3, r2
|
||
|
|
8002516: 614b str r3, [r1, #20]
|
||
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
|
||
|
|
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
|
||
|
|
__HAL_RCC_PLLSAI2_ENABLE();
|
||
|
|
8002518: 4b14 ldr r3, [pc, #80] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
800251a: 681b ldr r3, [r3, #0]
|
||
|
|
800251c: 4a13 ldr r2, [pc, #76] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
800251e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
||
|
|
8002522: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Get Start Tick*/
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8002524: f7fe fa50 bl 80009c8 <HAL_GetTick>
|
||
|
|
8002528: 60b8 str r0, [r7, #8]
|
||
|
|
|
||
|
|
/* Wait till PLLSAI2 is ready */
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
||
|
|
800252a: e009 b.n 8002540 <RCCEx_PLLSAI2_Config+0x18c>
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
||
|
|
800252c: f7fe fa4c bl 80009c8 <HAL_GetTick>
|
||
|
|
8002530: 4602 mov r2, r0
|
||
|
|
8002532: 68bb ldr r3, [r7, #8]
|
||
|
|
8002534: 1ad3 subs r3, r2, r3
|
||
|
|
8002536: 2b02 cmp r3, #2
|
||
|
|
8002538: d902 bls.n 8002540 <RCCEx_PLLSAI2_Config+0x18c>
|
||
|
|
{
|
||
|
|
status = HAL_TIMEOUT;
|
||
|
|
800253a: 2303 movs r3, #3
|
||
|
|
800253c: 73fb strb r3, [r7, #15]
|
||
|
|
break;
|
||
|
|
800253e: e005 b.n 800254c <RCCEx_PLLSAI2_Config+0x198>
|
||
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
||
|
|
8002540: 4b0a ldr r3, [pc, #40] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
8002542: 681b ldr r3, [r3, #0]
|
||
|
|
8002544: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
|
||
|
|
8002548: 2b00 cmp r3, #0
|
||
|
|
800254a: d0ef beq.n 800252c <RCCEx_PLLSAI2_Config+0x178>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(status == HAL_OK)
|
||
|
|
800254c: 7bfb ldrb r3, [r7, #15]
|
||
|
|
800254e: 2b00 cmp r3, #0
|
||
|
|
8002550: d106 bne.n 8002560 <RCCEx_PLLSAI2_Config+0x1ac>
|
||
|
|
{
|
||
|
|
/* Configure the PLLSAI2 Clock output(s) */
|
||
|
|
__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
|
||
|
|
8002552: 4b06 ldr r3, [pc, #24] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
8002554: 695a ldr r2, [r3, #20]
|
||
|
|
8002556: 687b ldr r3, [r7, #4]
|
||
|
|
8002558: 695b ldr r3, [r3, #20]
|
||
|
|
800255a: 4904 ldr r1, [pc, #16] ; (800256c <RCCEx_PLLSAI2_Config+0x1b8>)
|
||
|
|
800255c: 4313 orrs r3, r2
|
||
|
|
800255e: 614b str r3, [r1, #20]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return status;
|
||
|
|
8002560: 7bfb ldrb r3, [r7, #15]
|
||
|
|
}
|
||
|
|
8002562: 4618 mov r0, r3
|
||
|
|
8002564: 3710 adds r7, #16
|
||
|
|
8002566: 46bd mov sp, r7
|
||
|
|
8002568: bd80 pop {r7, pc}
|
||
|
|
800256a: bf00 nop
|
||
|
|
800256c: 40021000 .word 0x40021000
|
||
|
|
|
||
|
|
08002570 <HAL_UART_Init>:
|
||
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8002570: b580 push {r7, lr}
|
||
|
|
8002572: b082 sub sp, #8
|
||
|
|
8002574: af00 add r7, sp, #0
|
||
|
|
8002576: 6078 str r0, [r7, #4]
|
||
|
|
/* Check the UART handle allocation */
|
||
|
|
if (huart == NULL)
|
||
|
|
8002578: 687b ldr r3, [r7, #4]
|
||
|
|
800257a: 2b00 cmp r3, #0
|
||
|
|
800257c: d101 bne.n 8002582 <HAL_UART_Init+0x12>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
800257e: 2301 movs r3, #1
|
||
|
|
8002580: e040 b.n 8002604 <HAL_UART_Init+0x94>
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
||
|
|
}
|
||
|
|
|
||
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
||
|
|
8002582: 687b ldr r3, [r7, #4]
|
||
|
|
8002584: 6f9b ldr r3, [r3, #120] ; 0x78
|
||
|
|
8002586: 2b00 cmp r3, #0
|
||
|
|
8002588: d106 bne.n 8002598 <HAL_UART_Init+0x28>
|
||
|
|
{
|
||
|
|
/* Allocate lock resource and initialize it */
|
||
|
|
huart->Lock = HAL_UNLOCKED;
|
||
|
|
800258a: 687b ldr r3, [r7, #4]
|
||
|
|
800258c: 2200 movs r2, #0
|
||
|
|
800258e: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
||
|
|
|
||
|
|
/* Init the low level hardware */
|
||
|
|
huart->MspInitCallback(huart);
|
||
|
|
#else
|
||
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
||
|
|
HAL_UART_MspInit(huart);
|
||
|
|
8002592: 6878 ldr r0, [r7, #4]
|
||
|
|
8002594: f7fe f922 bl 80007dc <HAL_UART_MspInit>
|
||
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||
|
|
}
|
||
|
|
|
||
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
||
|
|
8002598: 687b ldr r3, [r7, #4]
|
||
|
|
800259a: 2224 movs r2, #36 ; 0x24
|
||
|
|
800259c: 679a str r2, [r3, #120] ; 0x78
|
||
|
|
|
||
|
|
__HAL_UART_DISABLE(huart);
|
||
|
|
800259e: 687b ldr r3, [r7, #4]
|
||
|
|
80025a0: 681b ldr r3, [r3, #0]
|
||
|
|
80025a2: 681a ldr r2, [r3, #0]
|
||
|
|
80025a4: 687b ldr r3, [r7, #4]
|
||
|
|
80025a6: 681b ldr r3, [r3, #0]
|
||
|
|
80025a8: f022 0201 bic.w r2, r2, #1
|
||
|
|
80025ac: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Set the UART Communication parameters */
|
||
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
||
|
|
80025ae: 6878 ldr r0, [r7, #4]
|
||
|
|
80025b0: f000 f82c bl 800260c <UART_SetConfig>
|
||
|
|
80025b4: 4603 mov r3, r0
|
||
|
|
80025b6: 2b01 cmp r3, #1
|
||
|
|
80025b8: d101 bne.n 80025be <HAL_UART_Init+0x4e>
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
80025ba: 2301 movs r3, #1
|
||
|
|
80025bc: e022 b.n 8002604 <HAL_UART_Init+0x94>
|
||
|
|
}
|
||
|
|
|
||
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||
|
|
80025be: 687b ldr r3, [r7, #4]
|
||
|
|
80025c0: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
80025c2: 2b00 cmp r3, #0
|
||
|
|
80025c4: d002 beq.n 80025cc <HAL_UART_Init+0x5c>
|
||
|
|
{
|
||
|
|
UART_AdvFeatureConfig(huart);
|
||
|
|
80025c6: 6878 ldr r0, [r7, #4]
|
||
|
|
80025c8: f000 fad8 bl 8002b7c <UART_AdvFeatureConfig>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
||
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
||
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
||
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
||
|
|
80025cc: 687b ldr r3, [r7, #4]
|
||
|
|
80025ce: 681b ldr r3, [r3, #0]
|
||
|
|
80025d0: 685a ldr r2, [r3, #4]
|
||
|
|
80025d2: 687b ldr r3, [r7, #4]
|
||
|
|
80025d4: 681b ldr r3, [r3, #0]
|
||
|
|
80025d6: f422 4290 bic.w r2, r2, #18432 ; 0x4800
|
||
|
|
80025da: 605a str r2, [r3, #4]
|
||
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
||
|
|
80025dc: 687b ldr r3, [r7, #4]
|
||
|
|
80025de: 681b ldr r3, [r3, #0]
|
||
|
|
80025e0: 689a ldr r2, [r3, #8]
|
||
|
|
80025e2: 687b ldr r3, [r7, #4]
|
||
|
|
80025e4: 681b ldr r3, [r3, #0]
|
||
|
|
80025e6: f022 022a bic.w r2, r2, #42 ; 0x2a
|
||
|
|
80025ea: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
__HAL_UART_ENABLE(huart);
|
||
|
|
80025ec: 687b ldr r3, [r7, #4]
|
||
|
|
80025ee: 681b ldr r3, [r3, #0]
|
||
|
|
80025f0: 681a ldr r2, [r3, #0]
|
||
|
|
80025f2: 687b ldr r3, [r7, #4]
|
||
|
|
80025f4: 681b ldr r3, [r3, #0]
|
||
|
|
80025f6: f042 0201 orr.w r2, r2, #1
|
||
|
|
80025fa: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
||
|
|
return (UART_CheckIdleState(huart));
|
||
|
|
80025fc: 6878 ldr r0, [r7, #4]
|
||
|
|
80025fe: f000 fb5f bl 8002cc0 <UART_CheckIdleState>
|
||
|
|
8002602: 4603 mov r3, r0
|
||
|
|
}
|
||
|
|
8002604: 4618 mov r0, r3
|
||
|
|
8002606: 3708 adds r7, #8
|
||
|
|
8002608: 46bd mov sp, r7
|
||
|
|
800260a: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
0800260c <UART_SetConfig>:
|
||
|
|
* @brief Configure the UART peripheral.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
800260c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
||
|
|
8002610: b08a sub sp, #40 ; 0x28
|
||
|
|
8002612: af00 add r7, sp, #0
|
||
|
|
8002614: 60f8 str r0, [r7, #12]
|
||
|
|
uint32_t tmpreg;
|
||
|
|
uint16_t brrtemp;
|
||
|
|
UART_ClockSourceTypeDef clocksource;
|
||
|
|
uint32_t usartdiv;
|
||
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
||
|
|
8002616: 2300 movs r3, #0
|
||
|
|
8002618: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
||
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
||
|
|
* set the M bits according to huart->Init.WordLength value
|
||
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
||
|
|
* set TE and RE bits according to huart->Init.Mode value
|
||
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
||
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
||
|
|
800261c: 68fb ldr r3, [r7, #12]
|
||
|
|
800261e: 689a ldr r2, [r3, #8]
|
||
|
|
8002620: 68fb ldr r3, [r7, #12]
|
||
|
|
8002622: 691b ldr r3, [r3, #16]
|
||
|
|
8002624: 431a orrs r2, r3
|
||
|
|
8002626: 68fb ldr r3, [r7, #12]
|
||
|
|
8002628: 695b ldr r3, [r3, #20]
|
||
|
|
800262a: 431a orrs r2, r3
|
||
|
|
800262c: 68fb ldr r3, [r7, #12]
|
||
|
|
800262e: 69db ldr r3, [r3, #28]
|
||
|
|
8002630: 4313 orrs r3, r2
|
||
|
|
8002632: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
||
|
|
8002634: 68fb ldr r3, [r7, #12]
|
||
|
|
8002636: 681b ldr r3, [r3, #0]
|
||
|
|
8002638: 681a ldr r2, [r3, #0]
|
||
|
|
800263a: 4ba4 ldr r3, [pc, #656] ; (80028cc <UART_SetConfig+0x2c0>)
|
||
|
|
800263c: 4013 ands r3, r2
|
||
|
|
800263e: 68fa ldr r2, [r7, #12]
|
||
|
|
8002640: 6812 ldr r2, [r2, #0]
|
||
|
|
8002642: 6a79 ldr r1, [r7, #36] ; 0x24
|
||
|
|
8002644: 430b orrs r3, r1
|
||
|
|
8002646: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
||
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
||
|
|
* to huart->Init.StopBits value */
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
||
|
|
8002648: 68fb ldr r3, [r7, #12]
|
||
|
|
800264a: 681b ldr r3, [r3, #0]
|
||
|
|
800264c: 685b ldr r3, [r3, #4]
|
||
|
|
800264e: f423 5140 bic.w r1, r3, #12288 ; 0x3000
|
||
|
|
8002652: 68fb ldr r3, [r7, #12]
|
||
|
|
8002654: 68da ldr r2, [r3, #12]
|
||
|
|
8002656: 68fb ldr r3, [r7, #12]
|
||
|
|
8002658: 681b ldr r3, [r3, #0]
|
||
|
|
800265a: 430a orrs r2, r1
|
||
|
|
800265c: 605a str r2, [r3, #4]
|
||
|
|
/* Configure
|
||
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
||
|
|
* to huart->Init.HwFlowCtl value
|
||
|
|
* - one-bit sampling method versus three samples' majority rule according
|
||
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
||
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
||
|
|
800265e: 68fb ldr r3, [r7, #12]
|
||
|
|
8002660: 699b ldr r3, [r3, #24]
|
||
|
|
8002662: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
|
||
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
||
|
|
8002664: 68fb ldr r3, [r7, #12]
|
||
|
|
8002666: 681b ldr r3, [r3, #0]
|
||
|
|
8002668: 4a99 ldr r2, [pc, #612] ; (80028d0 <UART_SetConfig+0x2c4>)
|
||
|
|
800266a: 4293 cmp r3, r2
|
||
|
|
800266c: d004 beq.n 8002678 <UART_SetConfig+0x6c>
|
||
|
|
{
|
||
|
|
tmpreg |= huart->Init.OneBitSampling;
|
||
|
|
800266e: 68fb ldr r3, [r7, #12]
|
||
|
|
8002670: 6a1b ldr r3, [r3, #32]
|
||
|
|
8002672: 6a7a ldr r2, [r7, #36] ; 0x24
|
||
|
|
8002674: 4313 orrs r3, r2
|
||
|
|
8002676: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
}
|
||
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
||
|
|
8002678: 68fb ldr r3, [r7, #12]
|
||
|
|
800267a: 681b ldr r3, [r3, #0]
|
||
|
|
800267c: 689b ldr r3, [r3, #8]
|
||
|
|
800267e: f423 6130 bic.w r1, r3, #2816 ; 0xb00
|
||
|
|
8002682: 68fb ldr r3, [r7, #12]
|
||
|
|
8002684: 681b ldr r3, [r3, #0]
|
||
|
|
8002686: 6a7a ldr r2, [r7, #36] ; 0x24
|
||
|
|
8002688: 430a orrs r2, r1
|
||
|
|
800268a: 609a str r2, [r3, #8]
|
||
|
|
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
|
||
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
||
|
|
#endif /* USART_PRESC_PRESCALER */
|
||
|
|
|
||
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
||
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
||
|
|
800268c: 68fb ldr r3, [r7, #12]
|
||
|
|
800268e: 681b ldr r3, [r3, #0]
|
||
|
|
8002690: 4a90 ldr r2, [pc, #576] ; (80028d4 <UART_SetConfig+0x2c8>)
|
||
|
|
8002692: 4293 cmp r3, r2
|
||
|
|
8002694: d126 bne.n 80026e4 <UART_SetConfig+0xd8>
|
||
|
|
8002696: 4b90 ldr r3, [pc, #576] ; (80028d8 <UART_SetConfig+0x2cc>)
|
||
|
|
8002698: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
800269c: f003 0303 and.w r3, r3, #3
|
||
|
|
80026a0: 2b03 cmp r3, #3
|
||
|
|
80026a2: d81b bhi.n 80026dc <UART_SetConfig+0xd0>
|
||
|
|
80026a4: a201 add r2, pc, #4 ; (adr r2, 80026ac <UART_SetConfig+0xa0>)
|
||
|
|
80026a6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
||
|
|
80026aa: bf00 nop
|
||
|
|
80026ac: 080026bd .word 0x080026bd
|
||
|
|
80026b0: 080026cd .word 0x080026cd
|
||
|
|
80026b4: 080026c5 .word 0x080026c5
|
||
|
|
80026b8: 080026d5 .word 0x080026d5
|
||
|
|
80026bc: 2301 movs r3, #1
|
||
|
|
80026be: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80026c2: e116 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80026c4: 2302 movs r3, #2
|
||
|
|
80026c6: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80026ca: e112 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80026cc: 2304 movs r3, #4
|
||
|
|
80026ce: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80026d2: e10e b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80026d4: 2308 movs r3, #8
|
||
|
|
80026d6: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80026da: e10a b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80026dc: 2310 movs r3, #16
|
||
|
|
80026de: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80026e2: e106 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80026e4: 68fb ldr r3, [r7, #12]
|
||
|
|
80026e6: 681b ldr r3, [r3, #0]
|
||
|
|
80026e8: 4a7c ldr r2, [pc, #496] ; (80028dc <UART_SetConfig+0x2d0>)
|
||
|
|
80026ea: 4293 cmp r3, r2
|
||
|
|
80026ec: d138 bne.n 8002760 <UART_SetConfig+0x154>
|
||
|
|
80026ee: 4b7a ldr r3, [pc, #488] ; (80028d8 <UART_SetConfig+0x2cc>)
|
||
|
|
80026f0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
80026f4: f003 030c and.w r3, r3, #12
|
||
|
|
80026f8: 2b0c cmp r3, #12
|
||
|
|
80026fa: d82d bhi.n 8002758 <UART_SetConfig+0x14c>
|
||
|
|
80026fc: a201 add r2, pc, #4 ; (adr r2, 8002704 <UART_SetConfig+0xf8>)
|
||
|
|
80026fe: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
||
|
|
8002702: bf00 nop
|
||
|
|
8002704: 08002739 .word 0x08002739
|
||
|
|
8002708: 08002759 .word 0x08002759
|
||
|
|
800270c: 08002759 .word 0x08002759
|
||
|
|
8002710: 08002759 .word 0x08002759
|
||
|
|
8002714: 08002749 .word 0x08002749
|
||
|
|
8002718: 08002759 .word 0x08002759
|
||
|
|
800271c: 08002759 .word 0x08002759
|
||
|
|
8002720: 08002759 .word 0x08002759
|
||
|
|
8002724: 08002741 .word 0x08002741
|
||
|
|
8002728: 08002759 .word 0x08002759
|
||
|
|
800272c: 08002759 .word 0x08002759
|
||
|
|
8002730: 08002759 .word 0x08002759
|
||
|
|
8002734: 08002751 .word 0x08002751
|
||
|
|
8002738: 2300 movs r3, #0
|
||
|
|
800273a: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
800273e: e0d8 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
8002740: 2302 movs r3, #2
|
||
|
|
8002742: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
8002746: e0d4 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
8002748: 2304 movs r3, #4
|
||
|
|
800274a: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
800274e: e0d0 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
8002750: 2308 movs r3, #8
|
||
|
|
8002752: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
8002756: e0cc b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
8002758: 2310 movs r3, #16
|
||
|
|
800275a: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
800275e: e0c8 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
8002760: 68fb ldr r3, [r7, #12]
|
||
|
|
8002762: 681b ldr r3, [r3, #0]
|
||
|
|
8002764: 4a5e ldr r2, [pc, #376] ; (80028e0 <UART_SetConfig+0x2d4>)
|
||
|
|
8002766: 4293 cmp r3, r2
|
||
|
|
8002768: d125 bne.n 80027b6 <UART_SetConfig+0x1aa>
|
||
|
|
800276a: 4b5b ldr r3, [pc, #364] ; (80028d8 <UART_SetConfig+0x2cc>)
|
||
|
|
800276c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
8002770: f003 0330 and.w r3, r3, #48 ; 0x30
|
||
|
|
8002774: 2b30 cmp r3, #48 ; 0x30
|
||
|
|
8002776: d016 beq.n 80027a6 <UART_SetConfig+0x19a>
|
||
|
|
8002778: 2b30 cmp r3, #48 ; 0x30
|
||
|
|
800277a: d818 bhi.n 80027ae <UART_SetConfig+0x1a2>
|
||
|
|
800277c: 2b20 cmp r3, #32
|
||
|
|
800277e: d00a beq.n 8002796 <UART_SetConfig+0x18a>
|
||
|
|
8002780: 2b20 cmp r3, #32
|
||
|
|
8002782: d814 bhi.n 80027ae <UART_SetConfig+0x1a2>
|
||
|
|
8002784: 2b00 cmp r3, #0
|
||
|
|
8002786: d002 beq.n 800278e <UART_SetConfig+0x182>
|
||
|
|
8002788: 2b10 cmp r3, #16
|
||
|
|
800278a: d008 beq.n 800279e <UART_SetConfig+0x192>
|
||
|
|
800278c: e00f b.n 80027ae <UART_SetConfig+0x1a2>
|
||
|
|
800278e: 2300 movs r3, #0
|
||
|
|
8002790: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
8002794: e0ad b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
8002796: 2302 movs r3, #2
|
||
|
|
8002798: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
800279c: e0a9 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
800279e: 2304 movs r3, #4
|
||
|
|
80027a0: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80027a4: e0a5 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80027a6: 2308 movs r3, #8
|
||
|
|
80027a8: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80027ac: e0a1 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80027ae: 2310 movs r3, #16
|
||
|
|
80027b0: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80027b4: e09d b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80027b6: 68fb ldr r3, [r7, #12]
|
||
|
|
80027b8: 681b ldr r3, [r3, #0]
|
||
|
|
80027ba: 4a4a ldr r2, [pc, #296] ; (80028e4 <UART_SetConfig+0x2d8>)
|
||
|
|
80027bc: 4293 cmp r3, r2
|
||
|
|
80027be: d125 bne.n 800280c <UART_SetConfig+0x200>
|
||
|
|
80027c0: 4b45 ldr r3, [pc, #276] ; (80028d8 <UART_SetConfig+0x2cc>)
|
||
|
|
80027c2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
80027c6: f003 03c0 and.w r3, r3, #192 ; 0xc0
|
||
|
|
80027ca: 2bc0 cmp r3, #192 ; 0xc0
|
||
|
|
80027cc: d016 beq.n 80027fc <UART_SetConfig+0x1f0>
|
||
|
|
80027ce: 2bc0 cmp r3, #192 ; 0xc0
|
||
|
|
80027d0: d818 bhi.n 8002804 <UART_SetConfig+0x1f8>
|
||
|
|
80027d2: 2b80 cmp r3, #128 ; 0x80
|
||
|
|
80027d4: d00a beq.n 80027ec <UART_SetConfig+0x1e0>
|
||
|
|
80027d6: 2b80 cmp r3, #128 ; 0x80
|
||
|
|
80027d8: d814 bhi.n 8002804 <UART_SetConfig+0x1f8>
|
||
|
|
80027da: 2b00 cmp r3, #0
|
||
|
|
80027dc: d002 beq.n 80027e4 <UART_SetConfig+0x1d8>
|
||
|
|
80027de: 2b40 cmp r3, #64 ; 0x40
|
||
|
|
80027e0: d008 beq.n 80027f4 <UART_SetConfig+0x1e8>
|
||
|
|
80027e2: e00f b.n 8002804 <UART_SetConfig+0x1f8>
|
||
|
|
80027e4: 2300 movs r3, #0
|
||
|
|
80027e6: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80027ea: e082 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80027ec: 2302 movs r3, #2
|
||
|
|
80027ee: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80027f2: e07e b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80027f4: 2304 movs r3, #4
|
||
|
|
80027f6: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80027fa: e07a b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80027fc: 2308 movs r3, #8
|
||
|
|
80027fe: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
8002802: e076 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
8002804: 2310 movs r3, #16
|
||
|
|
8002806: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
800280a: e072 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
800280c: 68fb ldr r3, [r7, #12]
|
||
|
|
800280e: 681b ldr r3, [r3, #0]
|
||
|
|
8002810: 4a35 ldr r2, [pc, #212] ; (80028e8 <UART_SetConfig+0x2dc>)
|
||
|
|
8002812: 4293 cmp r3, r2
|
||
|
|
8002814: d12a bne.n 800286c <UART_SetConfig+0x260>
|
||
|
|
8002816: 4b30 ldr r3, [pc, #192] ; (80028d8 <UART_SetConfig+0x2cc>)
|
||
|
|
8002818: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
800281c: f403 7340 and.w r3, r3, #768 ; 0x300
|
||
|
|
8002820: f5b3 7f40 cmp.w r3, #768 ; 0x300
|
||
|
|
8002824: d01a beq.n 800285c <UART_SetConfig+0x250>
|
||
|
|
8002826: f5b3 7f40 cmp.w r3, #768 ; 0x300
|
||
|
|
800282a: d81b bhi.n 8002864 <UART_SetConfig+0x258>
|
||
|
|
800282c: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
||
|
|
8002830: d00c beq.n 800284c <UART_SetConfig+0x240>
|
||
|
|
8002832: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
||
|
|
8002836: d815 bhi.n 8002864 <UART_SetConfig+0x258>
|
||
|
|
8002838: 2b00 cmp r3, #0
|
||
|
|
800283a: d003 beq.n 8002844 <UART_SetConfig+0x238>
|
||
|
|
800283c: f5b3 7f80 cmp.w r3, #256 ; 0x100
|
||
|
|
8002840: d008 beq.n 8002854 <UART_SetConfig+0x248>
|
||
|
|
8002842: e00f b.n 8002864 <UART_SetConfig+0x258>
|
||
|
|
8002844: 2300 movs r3, #0
|
||
|
|
8002846: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
800284a: e052 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
800284c: 2302 movs r3, #2
|
||
|
|
800284e: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
8002852: e04e b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
8002854: 2304 movs r3, #4
|
||
|
|
8002856: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
800285a: e04a b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
800285c: 2308 movs r3, #8
|
||
|
|
800285e: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
8002862: e046 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
8002864: 2310 movs r3, #16
|
||
|
|
8002866: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
800286a: e042 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
800286c: 68fb ldr r3, [r7, #12]
|
||
|
|
800286e: 681b ldr r3, [r3, #0]
|
||
|
|
8002870: 4a17 ldr r2, [pc, #92] ; (80028d0 <UART_SetConfig+0x2c4>)
|
||
|
|
8002872: 4293 cmp r3, r2
|
||
|
|
8002874: d13a bne.n 80028ec <UART_SetConfig+0x2e0>
|
||
|
|
8002876: 4b18 ldr r3, [pc, #96] ; (80028d8 <UART_SetConfig+0x2cc>)
|
||
|
|
8002878: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
||
|
|
800287c: f403 6340 and.w r3, r3, #3072 ; 0xc00
|
||
|
|
8002880: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
|
||
|
|
8002884: d01a beq.n 80028bc <UART_SetConfig+0x2b0>
|
||
|
|
8002886: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
|
||
|
|
800288a: d81b bhi.n 80028c4 <UART_SetConfig+0x2b8>
|
||
|
|
800288c: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
||
|
|
8002890: d00c beq.n 80028ac <UART_SetConfig+0x2a0>
|
||
|
|
8002892: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
||
|
|
8002896: d815 bhi.n 80028c4 <UART_SetConfig+0x2b8>
|
||
|
|
8002898: 2b00 cmp r3, #0
|
||
|
|
800289a: d003 beq.n 80028a4 <UART_SetConfig+0x298>
|
||
|
|
800289c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
||
|
|
80028a0: d008 beq.n 80028b4 <UART_SetConfig+0x2a8>
|
||
|
|
80028a2: e00f b.n 80028c4 <UART_SetConfig+0x2b8>
|
||
|
|
80028a4: 2300 movs r3, #0
|
||
|
|
80028a6: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80028aa: e022 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80028ac: 2302 movs r3, #2
|
||
|
|
80028ae: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80028b2: e01e b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80028b4: 2304 movs r3, #4
|
||
|
|
80028b6: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80028ba: e01a b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80028bc: 2308 movs r3, #8
|
||
|
|
80028be: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80028c2: e016 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80028c4: 2310 movs r3, #16
|
||
|
|
80028c6: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
80028ca: e012 b.n 80028f2 <UART_SetConfig+0x2e6>
|
||
|
|
80028cc: efff69f3 .word 0xefff69f3
|
||
|
|
80028d0: 40008000 .word 0x40008000
|
||
|
|
80028d4: 40013800 .word 0x40013800
|
||
|
|
80028d8: 40021000 .word 0x40021000
|
||
|
|
80028dc: 40004400 .word 0x40004400
|
||
|
|
80028e0: 40004800 .word 0x40004800
|
||
|
|
80028e4: 40004c00 .word 0x40004c00
|
||
|
|
80028e8: 40005000 .word 0x40005000
|
||
|
|
80028ec: 2310 movs r3, #16
|
||
|
|
80028ee: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
||
|
|
|
||
|
|
/* Check LPUART instance */
|
||
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
||
|
|
80028f2: 68fb ldr r3, [r7, #12]
|
||
|
|
80028f4: 681b ldr r3, [r3, #0]
|
||
|
|
80028f6: 4a9f ldr r2, [pc, #636] ; (8002b74 <UART_SetConfig+0x568>)
|
||
|
|
80028f8: 4293 cmp r3, r2
|
||
|
|
80028fa: d17a bne.n 80029f2 <UART_SetConfig+0x3e6>
|
||
|
|
{
|
||
|
|
/* Retrieve frequency clock */
|
||
|
|
switch (clocksource)
|
||
|
|
80028fc: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
|
||
|
|
8002900: 2b08 cmp r3, #8
|
||
|
|
8002902: d824 bhi.n 800294e <UART_SetConfig+0x342>
|
||
|
|
8002904: a201 add r2, pc, #4 ; (adr r2, 800290c <UART_SetConfig+0x300>)
|
||
|
|
8002906: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
||
|
|
800290a: bf00 nop
|
||
|
|
800290c: 08002931 .word 0x08002931
|
||
|
|
8002910: 0800294f .word 0x0800294f
|
||
|
|
8002914: 08002939 .word 0x08002939
|
||
|
|
8002918: 0800294f .word 0x0800294f
|
||
|
|
800291c: 0800293f .word 0x0800293f
|
||
|
|
8002920: 0800294f .word 0x0800294f
|
||
|
|
8002924: 0800294f .word 0x0800294f
|
||
|
|
8002928: 0800294f .word 0x0800294f
|
||
|
|
800292c: 08002947 .word 0x08002947
|
||
|
|
{
|
||
|
|
case UART_CLOCKSOURCE_PCLK1:
|
||
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
||
|
|
8002930: f7ff f8d6 bl 8001ae0 <HAL_RCC_GetPCLK1Freq>
|
||
|
|
8002934: 61f8 str r0, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002936: e010 b.n 800295a <UART_SetConfig+0x34e>
|
||
|
|
case UART_CLOCKSOURCE_HSI:
|
||
|
|
pclk = (uint32_t) HSI_VALUE;
|
||
|
|
8002938: 4b8f ldr r3, [pc, #572] ; (8002b78 <UART_SetConfig+0x56c>)
|
||
|
|
800293a: 61fb str r3, [r7, #28]
|
||
|
|
break;
|
||
|
|
800293c: e00d b.n 800295a <UART_SetConfig+0x34e>
|
||
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
||
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
||
|
|
800293e: f7ff f837 bl 80019b0 <HAL_RCC_GetSysClockFreq>
|
||
|
|
8002942: 61f8 str r0, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002944: e009 b.n 800295a <UART_SetConfig+0x34e>
|
||
|
|
case UART_CLOCKSOURCE_LSE:
|
||
|
|
pclk = (uint32_t) LSE_VALUE;
|
||
|
|
8002946: f44f 4300 mov.w r3, #32768 ; 0x8000
|
||
|
|
800294a: 61fb str r3, [r7, #28]
|
||
|
|
break;
|
||
|
|
800294c: e005 b.n 800295a <UART_SetConfig+0x34e>
|
||
|
|
default:
|
||
|
|
pclk = 0U;
|
||
|
|
800294e: 2300 movs r3, #0
|
||
|
|
8002950: 61fb str r3, [r7, #28]
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8002952: 2301 movs r3, #1
|
||
|
|
8002954: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
||
|
|
break;
|
||
|
|
8002958: bf00 nop
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If proper clock source reported */
|
||
|
|
if (pclk != 0U)
|
||
|
|
800295a: 69fb ldr r3, [r7, #28]
|
||
|
|
800295c: 2b00 cmp r3, #0
|
||
|
|
800295e: f000 80fb beq.w 8002b58 <UART_SetConfig+0x54c>
|
||
|
|
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
|
||
|
|
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
|
||
|
|
#else
|
||
|
|
/* No Prescaler applicable */
|
||
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
||
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
||
|
|
8002962: 68fb ldr r3, [r7, #12]
|
||
|
|
8002964: 685a ldr r2, [r3, #4]
|
||
|
|
8002966: 4613 mov r3, r2
|
||
|
|
8002968: 005b lsls r3, r3, #1
|
||
|
|
800296a: 4413 add r3, r2
|
||
|
|
800296c: 69fa ldr r2, [r7, #28]
|
||
|
|
800296e: 429a cmp r2, r3
|
||
|
|
8002970: d305 bcc.n 800297e <UART_SetConfig+0x372>
|
||
|
|
(pclk > (4096U * huart->Init.BaudRate)))
|
||
|
|
8002972: 68fb ldr r3, [r7, #12]
|
||
|
|
8002974: 685b ldr r3, [r3, #4]
|
||
|
|
8002976: 031b lsls r3, r3, #12
|
||
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
||
|
|
8002978: 69fa ldr r2, [r7, #28]
|
||
|
|
800297a: 429a cmp r2, r3
|
||
|
|
800297c: d903 bls.n 8002986 <UART_SetConfig+0x37a>
|
||
|
|
{
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
800297e: 2301 movs r3, #1
|
||
|
|
8002980: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
||
|
|
8002984: e0e8 b.n 8002b58 <UART_SetConfig+0x54c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
|
||
|
|
8002986: 69fb ldr r3, [r7, #28]
|
||
|
|
8002988: 2200 movs r2, #0
|
||
|
|
800298a: 461c mov r4, r3
|
||
|
|
800298c: 4615 mov r5, r2
|
||
|
|
800298e: f04f 0200 mov.w r2, #0
|
||
|
|
8002992: f04f 0300 mov.w r3, #0
|
||
|
|
8002996: 022b lsls r3, r5, #8
|
||
|
|
8002998: ea43 6314 orr.w r3, r3, r4, lsr #24
|
||
|
|
800299c: 0222 lsls r2, r4, #8
|
||
|
|
800299e: 68f9 ldr r1, [r7, #12]
|
||
|
|
80029a0: 6849 ldr r1, [r1, #4]
|
||
|
|
80029a2: 0849 lsrs r1, r1, #1
|
||
|
|
80029a4: 2000 movs r0, #0
|
||
|
|
80029a6: 4688 mov r8, r1
|
||
|
|
80029a8: 4681 mov r9, r0
|
||
|
|
80029aa: eb12 0a08 adds.w sl, r2, r8
|
||
|
|
80029ae: eb43 0b09 adc.w fp, r3, r9
|
||
|
|
80029b2: 68fb ldr r3, [r7, #12]
|
||
|
|
80029b4: 685b ldr r3, [r3, #4]
|
||
|
|
80029b6: 2200 movs r2, #0
|
||
|
|
80029b8: 603b str r3, [r7, #0]
|
||
|
|
80029ba: 607a str r2, [r7, #4]
|
||
|
|
80029bc: e9d7 2300 ldrd r2, r3, [r7]
|
||
|
|
80029c0: 4650 mov r0, sl
|
||
|
|
80029c2: 4659 mov r1, fp
|
||
|
|
80029c4: f7fd fc04 bl 80001d0 <__aeabi_uldivmod>
|
||
|
|
80029c8: 4602 mov r2, r0
|
||
|
|
80029ca: 460b mov r3, r1
|
||
|
|
80029cc: 4613 mov r3, r2
|
||
|
|
80029ce: 61bb str r3, [r7, #24]
|
||
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
||
|
|
80029d0: 69bb ldr r3, [r7, #24]
|
||
|
|
80029d2: f5b3 7f40 cmp.w r3, #768 ; 0x300
|
||
|
|
80029d6: d308 bcc.n 80029ea <UART_SetConfig+0x3de>
|
||
|
|
80029d8: 69bb ldr r3, [r7, #24]
|
||
|
|
80029da: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
|
||
|
|
80029de: d204 bcs.n 80029ea <UART_SetConfig+0x3de>
|
||
|
|
{
|
||
|
|
huart->Instance->BRR = usartdiv;
|
||
|
|
80029e0: 68fb ldr r3, [r7, #12]
|
||
|
|
80029e2: 681b ldr r3, [r3, #0]
|
||
|
|
80029e4: 69ba ldr r2, [r7, #24]
|
||
|
|
80029e6: 60da str r2, [r3, #12]
|
||
|
|
80029e8: e0b6 b.n 8002b58 <UART_SetConfig+0x54c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
80029ea: 2301 movs r3, #1
|
||
|
|
80029ec: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
||
|
|
80029f0: e0b2 b.n 8002b58 <UART_SetConfig+0x54c>
|
||
|
|
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
|
||
|
|
#endif /* USART_PRESC_PRESCALER */
|
||
|
|
} /* if (pclk != 0) */
|
||
|
|
}
|
||
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
||
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
||
|
|
80029f2: 68fb ldr r3, [r7, #12]
|
||
|
|
80029f4: 69db ldr r3, [r3, #28]
|
||
|
|
80029f6: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
|
||
|
|
80029fa: d15e bne.n 8002aba <UART_SetConfig+0x4ae>
|
||
|
|
{
|
||
|
|
switch (clocksource)
|
||
|
|
80029fc: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
|
||
|
|
8002a00: 2b08 cmp r3, #8
|
||
|
|
8002a02: d828 bhi.n 8002a56 <UART_SetConfig+0x44a>
|
||
|
|
8002a04: a201 add r2, pc, #4 ; (adr r2, 8002a0c <UART_SetConfig+0x400>)
|
||
|
|
8002a06: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
||
|
|
8002a0a: bf00 nop
|
||
|
|
8002a0c: 08002a31 .word 0x08002a31
|
||
|
|
8002a10: 08002a39 .word 0x08002a39
|
||
|
|
8002a14: 08002a41 .word 0x08002a41
|
||
|
|
8002a18: 08002a57 .word 0x08002a57
|
||
|
|
8002a1c: 08002a47 .word 0x08002a47
|
||
|
|
8002a20: 08002a57 .word 0x08002a57
|
||
|
|
8002a24: 08002a57 .word 0x08002a57
|
||
|
|
8002a28: 08002a57 .word 0x08002a57
|
||
|
|
8002a2c: 08002a4f .word 0x08002a4f
|
||
|
|
{
|
||
|
|
case UART_CLOCKSOURCE_PCLK1:
|
||
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
||
|
|
8002a30: f7ff f856 bl 8001ae0 <HAL_RCC_GetPCLK1Freq>
|
||
|
|
8002a34: 61f8 str r0, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002a36: e014 b.n 8002a62 <UART_SetConfig+0x456>
|
||
|
|
case UART_CLOCKSOURCE_PCLK2:
|
||
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
||
|
|
8002a38: f7ff f868 bl 8001b0c <HAL_RCC_GetPCLK2Freq>
|
||
|
|
8002a3c: 61f8 str r0, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002a3e: e010 b.n 8002a62 <UART_SetConfig+0x456>
|
||
|
|
case UART_CLOCKSOURCE_HSI:
|
||
|
|
pclk = (uint32_t) HSI_VALUE;
|
||
|
|
8002a40: 4b4d ldr r3, [pc, #308] ; (8002b78 <UART_SetConfig+0x56c>)
|
||
|
|
8002a42: 61fb str r3, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002a44: e00d b.n 8002a62 <UART_SetConfig+0x456>
|
||
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
||
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
||
|
|
8002a46: f7fe ffb3 bl 80019b0 <HAL_RCC_GetSysClockFreq>
|
||
|
|
8002a4a: 61f8 str r0, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002a4c: e009 b.n 8002a62 <UART_SetConfig+0x456>
|
||
|
|
case UART_CLOCKSOURCE_LSE:
|
||
|
|
pclk = (uint32_t) LSE_VALUE;
|
||
|
|
8002a4e: f44f 4300 mov.w r3, #32768 ; 0x8000
|
||
|
|
8002a52: 61fb str r3, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002a54: e005 b.n 8002a62 <UART_SetConfig+0x456>
|
||
|
|
default:
|
||
|
|
pclk = 0U;
|
||
|
|
8002a56: 2300 movs r3, #0
|
||
|
|
8002a58: 61fb str r3, [r7, #28]
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8002a5a: 2301 movs r3, #1
|
||
|
|
8002a5c: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
||
|
|
break;
|
||
|
|
8002a60: bf00 nop
|
||
|
|
}
|
||
|
|
|
||
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
||
|
|
if (pclk != 0U)
|
||
|
|
8002a62: 69fb ldr r3, [r7, #28]
|
||
|
|
8002a64: 2b00 cmp r3, #0
|
||
|
|
8002a66: d077 beq.n 8002b58 <UART_SetConfig+0x54c>
|
||
|
|
{
|
||
|
|
#if defined(USART_PRESC_PRESCALER)
|
||
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
||
|
|
#else
|
||
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
||
|
|
8002a68: 69fb ldr r3, [r7, #28]
|
||
|
|
8002a6a: 005a lsls r2, r3, #1
|
||
|
|
8002a6c: 68fb ldr r3, [r7, #12]
|
||
|
|
8002a6e: 685b ldr r3, [r3, #4]
|
||
|
|
8002a70: 085b lsrs r3, r3, #1
|
||
|
|
8002a72: 441a add r2, r3
|
||
|
|
8002a74: 68fb ldr r3, [r7, #12]
|
||
|
|
8002a76: 685b ldr r3, [r3, #4]
|
||
|
|
8002a78: fbb2 f3f3 udiv r3, r2, r3
|
||
|
|
8002a7c: 61bb str r3, [r7, #24]
|
||
|
|
#endif /* USART_PRESC_PRESCALER */
|
||
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
||
|
|
8002a7e: 69bb ldr r3, [r7, #24]
|
||
|
|
8002a80: 2b0f cmp r3, #15
|
||
|
|
8002a82: d916 bls.n 8002ab2 <UART_SetConfig+0x4a6>
|
||
|
|
8002a84: 69bb ldr r3, [r7, #24]
|
||
|
|
8002a86: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
||
|
|
8002a8a: d212 bcs.n 8002ab2 <UART_SetConfig+0x4a6>
|
||
|
|
{
|
||
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
||
|
|
8002a8c: 69bb ldr r3, [r7, #24]
|
||
|
|
8002a8e: b29b uxth r3, r3
|
||
|
|
8002a90: f023 030f bic.w r3, r3, #15
|
||
|
|
8002a94: 82fb strh r3, [r7, #22]
|
||
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
||
|
|
8002a96: 69bb ldr r3, [r7, #24]
|
||
|
|
8002a98: 085b lsrs r3, r3, #1
|
||
|
|
8002a9a: b29b uxth r3, r3
|
||
|
|
8002a9c: f003 0307 and.w r3, r3, #7
|
||
|
|
8002aa0: b29a uxth r2, r3
|
||
|
|
8002aa2: 8afb ldrh r3, [r7, #22]
|
||
|
|
8002aa4: 4313 orrs r3, r2
|
||
|
|
8002aa6: 82fb strh r3, [r7, #22]
|
||
|
|
huart->Instance->BRR = brrtemp;
|
||
|
|
8002aa8: 68fb ldr r3, [r7, #12]
|
||
|
|
8002aaa: 681b ldr r3, [r3, #0]
|
||
|
|
8002aac: 8afa ldrh r2, [r7, #22]
|
||
|
|
8002aae: 60da str r2, [r3, #12]
|
||
|
|
8002ab0: e052 b.n 8002b58 <UART_SetConfig+0x54c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8002ab2: 2301 movs r3, #1
|
||
|
|
8002ab4: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
||
|
|
8002ab8: e04e b.n 8002b58 <UART_SetConfig+0x54c>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
switch (clocksource)
|
||
|
|
8002aba: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
|
||
|
|
8002abe: 2b08 cmp r3, #8
|
||
|
|
8002ac0: d827 bhi.n 8002b12 <UART_SetConfig+0x506>
|
||
|
|
8002ac2: a201 add r2, pc, #4 ; (adr r2, 8002ac8 <UART_SetConfig+0x4bc>)
|
||
|
|
8002ac4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
||
|
|
8002ac8: 08002aed .word 0x08002aed
|
||
|
|
8002acc: 08002af5 .word 0x08002af5
|
||
|
|
8002ad0: 08002afd .word 0x08002afd
|
||
|
|
8002ad4: 08002b13 .word 0x08002b13
|
||
|
|
8002ad8: 08002b03 .word 0x08002b03
|
||
|
|
8002adc: 08002b13 .word 0x08002b13
|
||
|
|
8002ae0: 08002b13 .word 0x08002b13
|
||
|
|
8002ae4: 08002b13 .word 0x08002b13
|
||
|
|
8002ae8: 08002b0b .word 0x08002b0b
|
||
|
|
{
|
||
|
|
case UART_CLOCKSOURCE_PCLK1:
|
||
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
||
|
|
8002aec: f7fe fff8 bl 8001ae0 <HAL_RCC_GetPCLK1Freq>
|
||
|
|
8002af0: 61f8 str r0, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002af2: e014 b.n 8002b1e <UART_SetConfig+0x512>
|
||
|
|
case UART_CLOCKSOURCE_PCLK2:
|
||
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
||
|
|
8002af4: f7ff f80a bl 8001b0c <HAL_RCC_GetPCLK2Freq>
|
||
|
|
8002af8: 61f8 str r0, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002afa: e010 b.n 8002b1e <UART_SetConfig+0x512>
|
||
|
|
case UART_CLOCKSOURCE_HSI:
|
||
|
|
pclk = (uint32_t) HSI_VALUE;
|
||
|
|
8002afc: 4b1e ldr r3, [pc, #120] ; (8002b78 <UART_SetConfig+0x56c>)
|
||
|
|
8002afe: 61fb str r3, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002b00: e00d b.n 8002b1e <UART_SetConfig+0x512>
|
||
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
||
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
||
|
|
8002b02: f7fe ff55 bl 80019b0 <HAL_RCC_GetSysClockFreq>
|
||
|
|
8002b06: 61f8 str r0, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002b08: e009 b.n 8002b1e <UART_SetConfig+0x512>
|
||
|
|
case UART_CLOCKSOURCE_LSE:
|
||
|
|
pclk = (uint32_t) LSE_VALUE;
|
||
|
|
8002b0a: f44f 4300 mov.w r3, #32768 ; 0x8000
|
||
|
|
8002b0e: 61fb str r3, [r7, #28]
|
||
|
|
break;
|
||
|
|
8002b10: e005 b.n 8002b1e <UART_SetConfig+0x512>
|
||
|
|
default:
|
||
|
|
pclk = 0U;
|
||
|
|
8002b12: 2300 movs r3, #0
|
||
|
|
8002b14: 61fb str r3, [r7, #28]
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8002b16: 2301 movs r3, #1
|
||
|
|
8002b18: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
||
|
|
break;
|
||
|
|
8002b1c: bf00 nop
|
||
|
|
}
|
||
|
|
|
||
|
|
if (pclk != 0U)
|
||
|
|
8002b1e: 69fb ldr r3, [r7, #28]
|
||
|
|
8002b20: 2b00 cmp r3, #0
|
||
|
|
8002b22: d019 beq.n 8002b58 <UART_SetConfig+0x54c>
|
||
|
|
{
|
||
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
||
|
|
#if defined(USART_PRESC_PRESCALER)
|
||
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
||
|
|
#else
|
||
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
||
|
|
8002b24: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b26: 685b ldr r3, [r3, #4]
|
||
|
|
8002b28: 085a lsrs r2, r3, #1
|
||
|
|
8002b2a: 69fb ldr r3, [r7, #28]
|
||
|
|
8002b2c: 441a add r2, r3
|
||
|
|
8002b2e: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b30: 685b ldr r3, [r3, #4]
|
||
|
|
8002b32: fbb2 f3f3 udiv r3, r2, r3
|
||
|
|
8002b36: 61bb str r3, [r7, #24]
|
||
|
|
#endif /* USART_PRESC_PRESCALER */
|
||
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
||
|
|
8002b38: 69bb ldr r3, [r7, #24]
|
||
|
|
8002b3a: 2b0f cmp r3, #15
|
||
|
|
8002b3c: d909 bls.n 8002b52 <UART_SetConfig+0x546>
|
||
|
|
8002b3e: 69bb ldr r3, [r7, #24]
|
||
|
|
8002b40: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
||
|
|
8002b44: d205 bcs.n 8002b52 <UART_SetConfig+0x546>
|
||
|
|
{
|
||
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
||
|
|
8002b46: 69bb ldr r3, [r7, #24]
|
||
|
|
8002b48: b29a uxth r2, r3
|
||
|
|
8002b4a: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b4c: 681b ldr r3, [r3, #0]
|
||
|
|
8002b4e: 60da str r2, [r3, #12]
|
||
|
|
8002b50: e002 b.n 8002b58 <UART_SetConfig+0x54c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ret = HAL_ERROR;
|
||
|
|
8002b52: 2301 movs r3, #1
|
||
|
|
8002b54: f887 3022 strb.w r3, [r7, #34] ; 0x22
|
||
|
|
huart->NbTxDataToProcess = 1;
|
||
|
|
huart->NbRxDataToProcess = 1;
|
||
|
|
#endif /* USART_CR1_FIFOEN */
|
||
|
|
|
||
|
|
/* Clear ISR function pointers */
|
||
|
|
huart->RxISR = NULL;
|
||
|
|
8002b58: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b5a: 2200 movs r2, #0
|
||
|
|
8002b5c: 665a str r2, [r3, #100] ; 0x64
|
||
|
|
huart->TxISR = NULL;
|
||
|
|
8002b5e: 68fb ldr r3, [r7, #12]
|
||
|
|
8002b60: 2200 movs r2, #0
|
||
|
|
8002b62: 669a str r2, [r3, #104] ; 0x68
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
8002b64: f897 3022 ldrb.w r3, [r7, #34] ; 0x22
|
||
|
|
}
|
||
|
|
8002b68: 4618 mov r0, r3
|
||
|
|
8002b6a: 3728 adds r7, #40 ; 0x28
|
||
|
|
8002b6c: 46bd mov sp, r7
|
||
|
|
8002b6e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
||
|
|
8002b72: bf00 nop
|
||
|
|
8002b74: 40008000 .word 0x40008000
|
||
|
|
8002b78: 00f42400 .word 0x00f42400
|
||
|
|
|
||
|
|
08002b7c <UART_AdvFeatureConfig>:
|
||
|
|
* @brief Configure the UART peripheral advanced features.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8002b7c: b480 push {r7}
|
||
|
|
8002b7e: b083 sub sp, #12
|
||
|
|
8002b80: af00 add r7, sp, #0
|
||
|
|
8002b82: 6078 str r0, [r7, #4]
|
||
|
|
/* Check whether the set of advanced features to configure is properly set */
|
||
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
||
|
|
|
||
|
|
/* if required, configure TX pin active level inversion */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
||
|
|
8002b84: 687b ldr r3, [r7, #4]
|
||
|
|
8002b86: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8002b88: f003 0301 and.w r3, r3, #1
|
||
|
|
8002b8c: 2b00 cmp r3, #0
|
||
|
|
8002b8e: d00a beq.n 8002ba6 <UART_AdvFeatureConfig+0x2a>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
||
|
|
8002b90: 687b ldr r3, [r7, #4]
|
||
|
|
8002b92: 681b ldr r3, [r3, #0]
|
||
|
|
8002b94: 685b ldr r3, [r3, #4]
|
||
|
|
8002b96: f423 3100 bic.w r1, r3, #131072 ; 0x20000
|
||
|
|
8002b9a: 687b ldr r3, [r7, #4]
|
||
|
|
8002b9c: 6a9a ldr r2, [r3, #40] ; 0x28
|
||
|
|
8002b9e: 687b ldr r3, [r7, #4]
|
||
|
|
8002ba0: 681b ldr r3, [r3, #0]
|
||
|
|
8002ba2: 430a orrs r2, r1
|
||
|
|
8002ba4: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure RX pin active level inversion */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
||
|
|
8002ba6: 687b ldr r3, [r7, #4]
|
||
|
|
8002ba8: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8002baa: f003 0302 and.w r3, r3, #2
|
||
|
|
8002bae: 2b00 cmp r3, #0
|
||
|
|
8002bb0: d00a beq.n 8002bc8 <UART_AdvFeatureConfig+0x4c>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
||
|
|
8002bb2: 687b ldr r3, [r7, #4]
|
||
|
|
8002bb4: 681b ldr r3, [r3, #0]
|
||
|
|
8002bb6: 685b ldr r3, [r3, #4]
|
||
|
|
8002bb8: f423 3180 bic.w r1, r3, #65536 ; 0x10000
|
||
|
|
8002bbc: 687b ldr r3, [r7, #4]
|
||
|
|
8002bbe: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8002bc0: 687b ldr r3, [r7, #4]
|
||
|
|
8002bc2: 681b ldr r3, [r3, #0]
|
||
|
|
8002bc4: 430a orrs r2, r1
|
||
|
|
8002bc6: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure data inversion */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
||
|
|
8002bc8: 687b ldr r3, [r7, #4]
|
||
|
|
8002bca: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8002bcc: f003 0304 and.w r3, r3, #4
|
||
|
|
8002bd0: 2b00 cmp r3, #0
|
||
|
|
8002bd2: d00a beq.n 8002bea <UART_AdvFeatureConfig+0x6e>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
||
|
|
8002bd4: 687b ldr r3, [r7, #4]
|
||
|
|
8002bd6: 681b ldr r3, [r3, #0]
|
||
|
|
8002bd8: 685b ldr r3, [r3, #4]
|
||
|
|
8002bda: f423 2180 bic.w r1, r3, #262144 ; 0x40000
|
||
|
|
8002bde: 687b ldr r3, [r7, #4]
|
||
|
|
8002be0: 6b1a ldr r2, [r3, #48] ; 0x30
|
||
|
|
8002be2: 687b ldr r3, [r7, #4]
|
||
|
|
8002be4: 681b ldr r3, [r3, #0]
|
||
|
|
8002be6: 430a orrs r2, r1
|
||
|
|
8002be8: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure RX/TX pins swap */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
||
|
|
8002bea: 687b ldr r3, [r7, #4]
|
||
|
|
8002bec: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8002bee: f003 0308 and.w r3, r3, #8
|
||
|
|
8002bf2: 2b00 cmp r3, #0
|
||
|
|
8002bf4: d00a beq.n 8002c0c <UART_AdvFeatureConfig+0x90>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
||
|
|
8002bf6: 687b ldr r3, [r7, #4]
|
||
|
|
8002bf8: 681b ldr r3, [r3, #0]
|
||
|
|
8002bfa: 685b ldr r3, [r3, #4]
|
||
|
|
8002bfc: f423 4100 bic.w r1, r3, #32768 ; 0x8000
|
||
|
|
8002c00: 687b ldr r3, [r7, #4]
|
||
|
|
8002c02: 6b5a ldr r2, [r3, #52] ; 0x34
|
||
|
|
8002c04: 687b ldr r3, [r7, #4]
|
||
|
|
8002c06: 681b ldr r3, [r3, #0]
|
||
|
|
8002c08: 430a orrs r2, r1
|
||
|
|
8002c0a: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure RX overrun detection disabling */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
||
|
|
8002c0c: 687b ldr r3, [r7, #4]
|
||
|
|
8002c0e: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8002c10: f003 0310 and.w r3, r3, #16
|
||
|
|
8002c14: 2b00 cmp r3, #0
|
||
|
|
8002c16: d00a beq.n 8002c2e <UART_AdvFeatureConfig+0xb2>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
||
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
||
|
|
8002c18: 687b ldr r3, [r7, #4]
|
||
|
|
8002c1a: 681b ldr r3, [r3, #0]
|
||
|
|
8002c1c: 689b ldr r3, [r3, #8]
|
||
|
|
8002c1e: f423 5180 bic.w r1, r3, #4096 ; 0x1000
|
||
|
|
8002c22: 687b ldr r3, [r7, #4]
|
||
|
|
8002c24: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
8002c26: 687b ldr r3, [r7, #4]
|
||
|
|
8002c28: 681b ldr r3, [r3, #0]
|
||
|
|
8002c2a: 430a orrs r2, r1
|
||
|
|
8002c2c: 609a str r2, [r3, #8]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure DMA disabling on reception error */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
||
|
|
8002c2e: 687b ldr r3, [r7, #4]
|
||
|
|
8002c30: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8002c32: f003 0320 and.w r3, r3, #32
|
||
|
|
8002c36: 2b00 cmp r3, #0
|
||
|
|
8002c38: d00a beq.n 8002c50 <UART_AdvFeatureConfig+0xd4>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
||
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
||
|
|
8002c3a: 687b ldr r3, [r7, #4]
|
||
|
|
8002c3c: 681b ldr r3, [r3, #0]
|
||
|
|
8002c3e: 689b ldr r3, [r3, #8]
|
||
|
|
8002c40: f423 5100 bic.w r1, r3, #8192 ; 0x2000
|
||
|
|
8002c44: 687b ldr r3, [r7, #4]
|
||
|
|
8002c46: 6bda ldr r2, [r3, #60] ; 0x3c
|
||
|
|
8002c48: 687b ldr r3, [r7, #4]
|
||
|
|
8002c4a: 681b ldr r3, [r3, #0]
|
||
|
|
8002c4c: 430a orrs r2, r1
|
||
|
|
8002c4e: 609a str r2, [r3, #8]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure auto Baud rate detection scheme */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
||
|
|
8002c50: 687b ldr r3, [r7, #4]
|
||
|
|
8002c52: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8002c54: f003 0340 and.w r3, r3, #64 ; 0x40
|
||
|
|
8002c58: 2b00 cmp r3, #0
|
||
|
|
8002c5a: d01a beq.n 8002c92 <UART_AdvFeatureConfig+0x116>
|
||
|
|
{
|
||
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
||
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
||
|
|
8002c5c: 687b ldr r3, [r7, #4]
|
||
|
|
8002c5e: 681b ldr r3, [r3, #0]
|
||
|
|
8002c60: 685b ldr r3, [r3, #4]
|
||
|
|
8002c62: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
|
||
|
|
8002c66: 687b ldr r3, [r7, #4]
|
||
|
|
8002c68: 6c1a ldr r2, [r3, #64] ; 0x40
|
||
|
|
8002c6a: 687b ldr r3, [r7, #4]
|
||
|
|
8002c6c: 681b ldr r3, [r3, #0]
|
||
|
|
8002c6e: 430a orrs r2, r1
|
||
|
|
8002c70: 605a str r2, [r3, #4]
|
||
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
||
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
||
|
|
8002c72: 687b ldr r3, [r7, #4]
|
||
|
|
8002c74: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8002c76: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
|
||
|
|
8002c7a: d10a bne.n 8002c92 <UART_AdvFeatureConfig+0x116>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
||
|
|
8002c7c: 687b ldr r3, [r7, #4]
|
||
|
|
8002c7e: 681b ldr r3, [r3, #0]
|
||
|
|
8002c80: 685b ldr r3, [r3, #4]
|
||
|
|
8002c82: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
|
||
|
|
8002c86: 687b ldr r3, [r7, #4]
|
||
|
|
8002c88: 6c5a ldr r2, [r3, #68] ; 0x44
|
||
|
|
8002c8a: 687b ldr r3, [r7, #4]
|
||
|
|
8002c8c: 681b ldr r3, [r3, #0]
|
||
|
|
8002c8e: 430a orrs r2, r1
|
||
|
|
8002c90: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* if required, configure MSB first on communication line */
|
||
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
||
|
|
8002c92: 687b ldr r3, [r7, #4]
|
||
|
|
8002c94: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8002c96: f003 0380 and.w r3, r3, #128 ; 0x80
|
||
|
|
8002c9a: 2b00 cmp r3, #0
|
||
|
|
8002c9c: d00a beq.n 8002cb4 <UART_AdvFeatureConfig+0x138>
|
||
|
|
{
|
||
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
||
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
||
|
|
8002c9e: 687b ldr r3, [r7, #4]
|
||
|
|
8002ca0: 681b ldr r3, [r3, #0]
|
||
|
|
8002ca2: 685b ldr r3, [r3, #4]
|
||
|
|
8002ca4: f423 2100 bic.w r1, r3, #524288 ; 0x80000
|
||
|
|
8002ca8: 687b ldr r3, [r7, #4]
|
||
|
|
8002caa: 6c9a ldr r2, [r3, #72] ; 0x48
|
||
|
|
8002cac: 687b ldr r3, [r7, #4]
|
||
|
|
8002cae: 681b ldr r3, [r3, #0]
|
||
|
|
8002cb0: 430a orrs r2, r1
|
||
|
|
8002cb2: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8002cb4: bf00 nop
|
||
|
|
8002cb6: 370c adds r7, #12
|
||
|
|
8002cb8: 46bd mov sp, r7
|
||
|
|
8002cba: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8002cbe: 4770 bx lr
|
||
|
|
|
||
|
|
08002cc0 <UART_CheckIdleState>:
|
||
|
|
* @brief Check the UART Idle State.
|
||
|
|
* @param huart UART handle.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
||
|
|
{
|
||
|
|
8002cc0: b580 push {r7, lr}
|
||
|
|
8002cc2: b086 sub sp, #24
|
||
|
|
8002cc4: af02 add r7, sp, #8
|
||
|
|
8002cc6: 6078 str r0, [r7, #4]
|
||
|
|
uint32_t tickstart;
|
||
|
|
|
||
|
|
/* Initialize the UART ErrorCode */
|
||
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
||
|
|
8002cc8: 687b ldr r3, [r7, #4]
|
||
|
|
8002cca: 2200 movs r2, #0
|
||
|
|
8002ccc: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
||
|
|
|
||
|
|
/* Init tickstart for timeout management */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
8002cd0: f7fd fe7a bl 80009c8 <HAL_GetTick>
|
||
|
|
8002cd4: 60f8 str r0, [r7, #12]
|
||
|
|
|
||
|
|
/* Check if the Transmitter is enabled */
|
||
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
||
|
|
8002cd6: 687b ldr r3, [r7, #4]
|
||
|
|
8002cd8: 681b ldr r3, [r3, #0]
|
||
|
|
8002cda: 681b ldr r3, [r3, #0]
|
||
|
|
8002cdc: f003 0308 and.w r3, r3, #8
|
||
|
|
8002ce0: 2b08 cmp r3, #8
|
||
|
|
8002ce2: d10e bne.n 8002d02 <UART_CheckIdleState+0x42>
|
||
|
|
{
|
||
|
|
/* Wait until TEACK flag is set */
|
||
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
||
|
|
8002ce4: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
|
||
|
|
8002ce8: 9300 str r3, [sp, #0]
|
||
|
|
8002cea: 68fb ldr r3, [r7, #12]
|
||
|
|
8002cec: 2200 movs r2, #0
|
||
|
|
8002cee: f44f 1100 mov.w r1, #2097152 ; 0x200000
|
||
|
|
8002cf2: 6878 ldr r0, [r7, #4]
|
||
|
|
8002cf4: f000 f82d bl 8002d52 <UART_WaitOnFlagUntilTimeout>
|
||
|
|
8002cf8: 4603 mov r3, r0
|
||
|
|
8002cfa: 2b00 cmp r3, #0
|
||
|
|
8002cfc: d001 beq.n 8002d02 <UART_CheckIdleState+0x42>
|
||
|
|
{
|
||
|
|
/* Timeout occurred */
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8002cfe: 2303 movs r3, #3
|
||
|
|
8002d00: e023 b.n 8002d4a <UART_CheckIdleState+0x8a>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check if the Receiver is enabled */
|
||
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
||
|
|
8002d02: 687b ldr r3, [r7, #4]
|
||
|
|
8002d04: 681b ldr r3, [r3, #0]
|
||
|
|
8002d06: 681b ldr r3, [r3, #0]
|
||
|
|
8002d08: f003 0304 and.w r3, r3, #4
|
||
|
|
8002d0c: 2b04 cmp r3, #4
|
||
|
|
8002d0e: d10e bne.n 8002d2e <UART_CheckIdleState+0x6e>
|
||
|
|
{
|
||
|
|
/* Wait until REACK flag is set */
|
||
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
||
|
|
8002d10: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
|
||
|
|
8002d14: 9300 str r3, [sp, #0]
|
||
|
|
8002d16: 68fb ldr r3, [r7, #12]
|
||
|
|
8002d18: 2200 movs r2, #0
|
||
|
|
8002d1a: f44f 0180 mov.w r1, #4194304 ; 0x400000
|
||
|
|
8002d1e: 6878 ldr r0, [r7, #4]
|
||
|
|
8002d20: f000 f817 bl 8002d52 <UART_WaitOnFlagUntilTimeout>
|
||
|
|
8002d24: 4603 mov r3, r0
|
||
|
|
8002d26: 2b00 cmp r3, #0
|
||
|
|
8002d28: d001 beq.n 8002d2e <UART_CheckIdleState+0x6e>
|
||
|
|
{
|
||
|
|
/* Timeout occurred */
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8002d2a: 2303 movs r3, #3
|
||
|
|
8002d2c: e00d b.n 8002d4a <UART_CheckIdleState+0x8a>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Initialize the UART State */
|
||
|
|
huart->gState = HAL_UART_STATE_READY;
|
||
|
|
8002d2e: 687b ldr r3, [r7, #4]
|
||
|
|
8002d30: 2220 movs r2, #32
|
||
|
|
8002d32: 679a str r2, [r3, #120] ; 0x78
|
||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
||
|
|
8002d34: 687b ldr r3, [r7, #4]
|
||
|
|
8002d36: 2220 movs r2, #32
|
||
|
|
8002d38: 67da str r2, [r3, #124] ; 0x7c
|
||
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||
|
|
8002d3a: 687b ldr r3, [r7, #4]
|
||
|
|
8002d3c: 2200 movs r2, #0
|
||
|
|
8002d3e: 661a str r2, [r3, #96] ; 0x60
|
||
|
|
|
||
|
|
__HAL_UNLOCK(huart);
|
||
|
|
8002d40: 687b ldr r3, [r7, #4]
|
||
|
|
8002d42: 2200 movs r2, #0
|
||
|
|
8002d44: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
||
|
|
|
||
|
|
return HAL_OK;
|
||
|
|
8002d48: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8002d4a: 4618 mov r0, r3
|
||
|
|
8002d4c: 3710 adds r7, #16
|
||
|
|
8002d4e: 46bd mov sp, r7
|
||
|
|
8002d50: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08002d52 <UART_WaitOnFlagUntilTimeout>:
|
||
|
|
* @param Timeout Timeout duration
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
||
|
|
uint32_t Tickstart, uint32_t Timeout)
|
||
|
|
{
|
||
|
|
8002d52: b580 push {r7, lr}
|
||
|
|
8002d54: b09c sub sp, #112 ; 0x70
|
||
|
|
8002d56: af00 add r7, sp, #0
|
||
|
|
8002d58: 60f8 str r0, [r7, #12]
|
||
|
|
8002d5a: 60b9 str r1, [r7, #8]
|
||
|
|
8002d5c: 603b str r3, [r7, #0]
|
||
|
|
8002d5e: 4613 mov r3, r2
|
||
|
|
8002d60: 71fb strb r3, [r7, #7]
|
||
|
|
/* Wait until flag is set */
|
||
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
||
|
|
8002d62: e0a5 b.n 8002eb0 <UART_WaitOnFlagUntilTimeout+0x15e>
|
||
|
|
{
|
||
|
|
/* Check for the Timeout */
|
||
|
|
if (Timeout != HAL_MAX_DELAY)
|
||
|
|
8002d64: 6fbb ldr r3, [r7, #120] ; 0x78
|
||
|
|
8002d66: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
8002d6a: f000 80a1 beq.w 8002eb0 <UART_WaitOnFlagUntilTimeout+0x15e>
|
||
|
|
{
|
||
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
||
|
|
8002d6e: f7fd fe2b bl 80009c8 <HAL_GetTick>
|
||
|
|
8002d72: 4602 mov r2, r0
|
||
|
|
8002d74: 683b ldr r3, [r7, #0]
|
||
|
|
8002d76: 1ad3 subs r3, r2, r3
|
||
|
|
8002d78: 6fba ldr r2, [r7, #120] ; 0x78
|
||
|
|
8002d7a: 429a cmp r2, r3
|
||
|
|
8002d7c: d302 bcc.n 8002d84 <UART_WaitOnFlagUntilTimeout+0x32>
|
||
|
|
8002d7e: 6fbb ldr r3, [r7, #120] ; 0x78
|
||
|
|
8002d80: 2b00 cmp r3, #0
|
||
|
|
8002d82: d13e bne.n 8002e02 <UART_WaitOnFlagUntilTimeout+0xb0>
|
||
|
|
interrupts for the interrupt process */
|
||
|
|
#if defined(USART_CR1_FIFOEN)
|
||
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
|
||
|
|
USART_CR1_TXEIE_TXFNFIE));
|
||
|
|
#else
|
||
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
||
|
|
8002d84: 68fb ldr r3, [r7, #12]
|
||
|
|
8002d86: 681b ldr r3, [r3, #0]
|
||
|
|
8002d88: 653b str r3, [r7, #80] ; 0x50
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||
|
|
8002d8a: 6d3b ldr r3, [r7, #80] ; 0x50
|
||
|
|
8002d8c: e853 3f00 ldrex r3, [r3]
|
||
|
|
8002d90: 64fb str r3, [r7, #76] ; 0x4c
|
||
|
|
return(result);
|
||
|
|
8002d92: 6cfb ldr r3, [r7, #76] ; 0x4c
|
||
|
|
8002d94: f423 73d0 bic.w r3, r3, #416 ; 0x1a0
|
||
|
|
8002d98: 667b str r3, [r7, #100] ; 0x64
|
||
|
|
8002d9a: 68fb ldr r3, [r7, #12]
|
||
|
|
8002d9c: 681b ldr r3, [r3, #0]
|
||
|
|
8002d9e: 461a mov r2, r3
|
||
|
|
8002da0: 6e7b ldr r3, [r7, #100] ; 0x64
|
||
|
|
8002da2: 65fb str r3, [r7, #92] ; 0x5c
|
||
|
|
8002da4: 65ba str r2, [r7, #88] ; 0x58
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||
|
|
8002da6: 6db9 ldr r1, [r7, #88] ; 0x58
|
||
|
|
8002da8: 6dfa ldr r2, [r7, #92] ; 0x5c
|
||
|
|
8002daa: e841 2300 strex r3, r2, [r1]
|
||
|
|
8002dae: 657b str r3, [r7, #84] ; 0x54
|
||
|
|
return(result);
|
||
|
|
8002db0: 6d7b ldr r3, [r7, #84] ; 0x54
|
||
|
|
8002db2: 2b00 cmp r3, #0
|
||
|
|
8002db4: d1e6 bne.n 8002d84 <UART_WaitOnFlagUntilTimeout+0x32>
|
||
|
|
#endif /* USART_CR1_FIFOEN */
|
||
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||
|
|
8002db6: 68fb ldr r3, [r7, #12]
|
||
|
|
8002db8: 681b ldr r3, [r3, #0]
|
||
|
|
8002dba: 3308 adds r3, #8
|
||
|
|
8002dbc: 63fb str r3, [r7, #60] ; 0x3c
|
||
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||
|
|
8002dbe: 6bfb ldr r3, [r7, #60] ; 0x3c
|
||
|
|
8002dc0: e853 3f00 ldrex r3, [r3]
|
||
|
|
8002dc4: 63bb str r3, [r7, #56] ; 0x38
|
||
|
|
return(result);
|
||
|
|
8002dc6: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
8002dc8: f023 0301 bic.w r3, r3, #1
|
||
|
|
8002dcc: 663b str r3, [r7, #96] ; 0x60
|
||
|
|
8002dce: 68fb ldr r3, [r7, #12]
|
||
|
|
8002dd0: 681b ldr r3, [r3, #0]
|
||
|
|
8002dd2: 3308 adds r3, #8
|
||
|
|
8002dd4: 6e3a ldr r2, [r7, #96] ; 0x60
|
||
|
|
8002dd6: 64ba str r2, [r7, #72] ; 0x48
|
||
|
|
8002dd8: 647b str r3, [r7, #68] ; 0x44
|
||
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||
|
|
8002dda: 6c79 ldr r1, [r7, #68] ; 0x44
|
||
|
|
8002ddc: 6cba ldr r2, [r7, #72] ; 0x48
|
||
|
|
8002dde: e841 2300 strex r3, r2, [r1]
|
||
|
|
8002de2: 643b str r3, [r7, #64] ; 0x40
|
||
|
|
return(result);
|
||
|
|
8002de4: 6c3b ldr r3, [r7, #64] ; 0x40
|
||
|
|
8002de6: 2b00 cmp r3, #0
|
||
|
|
8002de8: d1e5 bne.n 8002db6 <UART_WaitOnFlagUntilTimeout+0x64>
|
||
|
|
|
||
|
|
huart->gState = HAL_UART_STATE_READY;
|
||
|
|
8002dea: 68fb ldr r3, [r7, #12]
|
||
|
|
8002dec: 2220 movs r2, #32
|
||
|
|
8002dee: 679a str r2, [r3, #120] ; 0x78
|
||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
||
|
|
8002df0: 68fb ldr r3, [r7, #12]
|
||
|
|
8002df2: 2220 movs r2, #32
|
||
|
|
8002df4: 67da str r2, [r3, #124] ; 0x7c
|
||
|
|
|
||
|
|
__HAL_UNLOCK(huart);
|
||
|
|
8002df6: 68fb ldr r3, [r7, #12]
|
||
|
|
8002df8: 2200 movs r2, #0
|
||
|
|
8002dfa: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
||
|
|
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8002dfe: 2303 movs r3, #3
|
||
|
|
8002e00: e067 b.n 8002ed2 <UART_WaitOnFlagUntilTimeout+0x180>
|
||
|
|
}
|
||
|
|
|
||
|
|
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
|
||
|
|
8002e02: 68fb ldr r3, [r7, #12]
|
||
|
|
8002e04: 681b ldr r3, [r3, #0]
|
||
|
|
8002e06: 681b ldr r3, [r3, #0]
|
||
|
|
8002e08: f003 0304 and.w r3, r3, #4
|
||
|
|
8002e0c: 2b00 cmp r3, #0
|
||
|
|
8002e0e: d04f beq.n 8002eb0 <UART_WaitOnFlagUntilTimeout+0x15e>
|
||
|
|
{
|
||
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
||
|
|
8002e10: 68fb ldr r3, [r7, #12]
|
||
|
|
8002e12: 681b ldr r3, [r3, #0]
|
||
|
|
8002e14: 69db ldr r3, [r3, #28]
|
||
|
|
8002e16: f403 6300 and.w r3, r3, #2048 ; 0x800
|
||
|
|
8002e1a: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
||
|
|
8002e1e: d147 bne.n 8002eb0 <UART_WaitOnFlagUntilTimeout+0x15e>
|
||
|
|
{
|
||
|
|
/* Clear Receiver Timeout flag*/
|
||
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
||
|
|
8002e20: 68fb ldr r3, [r7, #12]
|
||
|
|
8002e22: 681b ldr r3, [r3, #0]
|
||
|
|
8002e24: f44f 6200 mov.w r2, #2048 ; 0x800
|
||
|
|
8002e28: 621a str r2, [r3, #32]
|
||
|
|
interrupts for the interrupt process */
|
||
|
|
#if defined(USART_CR1_FIFOEN)
|
||
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
|
||
|
|
USART_CR1_TXEIE_TXFNFIE));
|
||
|
|
#else
|
||
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
||
|
|
8002e2a: 68fb ldr r3, [r7, #12]
|
||
|
|
8002e2c: 681b ldr r3, [r3, #0]
|
||
|
|
8002e2e: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||
|
|
8002e30: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8002e32: e853 3f00 ldrex r3, [r3]
|
||
|
|
8002e36: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
return(result);
|
||
|
|
8002e38: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8002e3a: f423 73d0 bic.w r3, r3, #416 ; 0x1a0
|
||
|
|
8002e3e: 66fb str r3, [r7, #108] ; 0x6c
|
||
|
|
8002e40: 68fb ldr r3, [r7, #12]
|
||
|
|
8002e42: 681b ldr r3, [r3, #0]
|
||
|
|
8002e44: 461a mov r2, r3
|
||
|
|
8002e46: 6efb ldr r3, [r7, #108] ; 0x6c
|
||
|
|
8002e48: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
8002e4a: 633a str r2, [r7, #48] ; 0x30
|
||
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||
|
|
8002e4c: 6b39 ldr r1, [r7, #48] ; 0x30
|
||
|
|
8002e4e: 6b7a ldr r2, [r7, #52] ; 0x34
|
||
|
|
8002e50: e841 2300 strex r3, r2, [r1]
|
||
|
|
8002e54: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
return(result);
|
||
|
|
8002e56: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8002e58: 2b00 cmp r3, #0
|
||
|
|
8002e5a: d1e6 bne.n 8002e2a <UART_WaitOnFlagUntilTimeout+0xd8>
|
||
|
|
#endif /* USART_CR1_FIFOEN */
|
||
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||
|
|
8002e5c: 68fb ldr r3, [r7, #12]
|
||
|
|
8002e5e: 681b ldr r3, [r3, #0]
|
||
|
|
8002e60: 3308 adds r3, #8
|
||
|
|
8002e62: 617b str r3, [r7, #20]
|
||
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||
|
|
8002e64: 697b ldr r3, [r7, #20]
|
||
|
|
8002e66: e853 3f00 ldrex r3, [r3]
|
||
|
|
8002e6a: 613b str r3, [r7, #16]
|
||
|
|
return(result);
|
||
|
|
8002e6c: 693b ldr r3, [r7, #16]
|
||
|
|
8002e6e: f023 0301 bic.w r3, r3, #1
|
||
|
|
8002e72: 66bb str r3, [r7, #104] ; 0x68
|
||
|
|
8002e74: 68fb ldr r3, [r7, #12]
|
||
|
|
8002e76: 681b ldr r3, [r3, #0]
|
||
|
|
8002e78: 3308 adds r3, #8
|
||
|
|
8002e7a: 6eba ldr r2, [r7, #104] ; 0x68
|
||
|
|
8002e7c: 623a str r2, [r7, #32]
|
||
|
|
8002e7e: 61fb str r3, [r7, #28]
|
||
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||
|
|
8002e80: 69f9 ldr r1, [r7, #28]
|
||
|
|
8002e82: 6a3a ldr r2, [r7, #32]
|
||
|
|
8002e84: e841 2300 strex r3, r2, [r1]
|
||
|
|
8002e88: 61bb str r3, [r7, #24]
|
||
|
|
return(result);
|
||
|
|
8002e8a: 69bb ldr r3, [r7, #24]
|
||
|
|
8002e8c: 2b00 cmp r3, #0
|
||
|
|
8002e8e: d1e5 bne.n 8002e5c <UART_WaitOnFlagUntilTimeout+0x10a>
|
||
|
|
|
||
|
|
huart->gState = HAL_UART_STATE_READY;
|
||
|
|
8002e90: 68fb ldr r3, [r7, #12]
|
||
|
|
8002e92: 2220 movs r2, #32
|
||
|
|
8002e94: 679a str r2, [r3, #120] ; 0x78
|
||
|
|
huart->RxState = HAL_UART_STATE_READY;
|
||
|
|
8002e96: 68fb ldr r3, [r7, #12]
|
||
|
|
8002e98: 2220 movs r2, #32
|
||
|
|
8002e9a: 67da str r2, [r3, #124] ; 0x7c
|
||
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
||
|
|
8002e9c: 68fb ldr r3, [r7, #12]
|
||
|
|
8002e9e: 2220 movs r2, #32
|
||
|
|
8002ea0: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(huart);
|
||
|
|
8002ea4: 68fb ldr r3, [r7, #12]
|
||
|
|
8002ea6: 2200 movs r2, #0
|
||
|
|
8002ea8: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
||
|
|
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
8002eac: 2303 movs r3, #3
|
||
|
|
8002eae: e010 b.n 8002ed2 <UART_WaitOnFlagUntilTimeout+0x180>
|
||
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
||
|
|
8002eb0: 68fb ldr r3, [r7, #12]
|
||
|
|
8002eb2: 681b ldr r3, [r3, #0]
|
||
|
|
8002eb4: 69da ldr r2, [r3, #28]
|
||
|
|
8002eb6: 68bb ldr r3, [r7, #8]
|
||
|
|
8002eb8: 4013 ands r3, r2
|
||
|
|
8002eba: 68ba ldr r2, [r7, #8]
|
||
|
|
8002ebc: 429a cmp r2, r3
|
||
|
|
8002ebe: bf0c ite eq
|
||
|
|
8002ec0: 2301 moveq r3, #1
|
||
|
|
8002ec2: 2300 movne r3, #0
|
||
|
|
8002ec4: b2db uxtb r3, r3
|
||
|
|
8002ec6: 461a mov r2, r3
|
||
|
|
8002ec8: 79fb ldrb r3, [r7, #7]
|
||
|
|
8002eca: 429a cmp r2, r3
|
||
|
|
8002ecc: f43f af4a beq.w 8002d64 <UART_WaitOnFlagUntilTimeout+0x12>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return HAL_OK;
|
||
|
|
8002ed0: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8002ed2: 4618 mov r0, r3
|
||
|
|
8002ed4: 3770 adds r7, #112 ; 0x70
|
||
|
|
8002ed6: 46bd mov sp, r7
|
||
|
|
8002ed8: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
08002edc <__NVIC_SetPriority>:
|
||
|
|
{
|
||
|
|
8002edc: b480 push {r7}
|
||
|
|
8002ede: b083 sub sp, #12
|
||
|
|
8002ee0: af00 add r7, sp, #0
|
||
|
|
8002ee2: 4603 mov r3, r0
|
||
|
|
8002ee4: 6039 str r1, [r7, #0]
|
||
|
|
8002ee6: 71fb strb r3, [r7, #7]
|
||
|
|
if ((int32_t)(IRQn) >= 0)
|
||
|
|
8002ee8: f997 3007 ldrsb.w r3, [r7, #7]
|
||
|
|
8002eec: 2b00 cmp r3, #0
|
||
|
|
8002eee: db0a blt.n 8002f06 <__NVIC_SetPriority+0x2a>
|
||
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||
|
|
8002ef0: 683b ldr r3, [r7, #0]
|
||
|
|
8002ef2: b2da uxtb r2, r3
|
||
|
|
8002ef4: 490c ldr r1, [pc, #48] ; (8002f28 <__NVIC_SetPriority+0x4c>)
|
||
|
|
8002ef6: f997 3007 ldrsb.w r3, [r7, #7]
|
||
|
|
8002efa: 0112 lsls r2, r2, #4
|
||
|
|
8002efc: b2d2 uxtb r2, r2
|
||
|
|
8002efe: 440b add r3, r1
|
||
|
|
8002f00: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
||
|
|
}
|
||
|
|
8002f04: e00a b.n 8002f1c <__NVIC_SetPriority+0x40>
|
||
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||
|
|
8002f06: 683b ldr r3, [r7, #0]
|
||
|
|
8002f08: b2da uxtb r2, r3
|
||
|
|
8002f0a: 4908 ldr r1, [pc, #32] ; (8002f2c <__NVIC_SetPriority+0x50>)
|
||
|
|
8002f0c: 79fb ldrb r3, [r7, #7]
|
||
|
|
8002f0e: f003 030f and.w r3, r3, #15
|
||
|
|
8002f12: 3b04 subs r3, #4
|
||
|
|
8002f14: 0112 lsls r2, r2, #4
|
||
|
|
8002f16: b2d2 uxtb r2, r2
|
||
|
|
8002f18: 440b add r3, r1
|
||
|
|
8002f1a: 761a strb r2, [r3, #24]
|
||
|
|
}
|
||
|
|
8002f1c: bf00 nop
|
||
|
|
8002f1e: 370c adds r7, #12
|
||
|
|
8002f20: 46bd mov sp, r7
|
||
|
|
8002f22: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8002f26: 4770 bx lr
|
||
|
|
8002f28: e000e100 .word 0xe000e100
|
||
|
|
8002f2c: e000ed00 .word 0xe000ed00
|
||
|
|
|
||
|
|
08002f30 <SVC_Setup>:
|
||
|
|
#endif /* SysTick */
|
||
|
|
|
||
|
|
/*
|
||
|
|
Setup SVC to reset value.
|
||
|
|
*/
|
||
|
|
__STATIC_INLINE void SVC_Setup (void) {
|
||
|
|
8002f30: b580 push {r7, lr}
|
||
|
|
8002f32: af00 add r7, sp, #0
|
||
|
|
#if (__ARM_ARCH_7A__ == 0U)
|
||
|
|
/* Service Call interrupt might be configured before kernel start */
|
||
|
|
/* and when its priority is lower or equal to BASEPRI, svc intruction */
|
||
|
|
/* causes a Hard Fault. */
|
||
|
|
NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
|
||
|
|
8002f34: 2100 movs r1, #0
|
||
|
|
8002f36: f06f 0004 mvn.w r0, #4
|
||
|
|
8002f3a: f7ff ffcf bl 8002edc <__NVIC_SetPriority>
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
8002f3e: bf00 nop
|
||
|
|
8002f40: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
08002f44 <osKernelInitialize>:
|
||
|
|
static uint32_t OS_Tick_GetOverflow (void);
|
||
|
|
/* Get OS Tick interval */
|
||
|
|
static uint32_t OS_Tick_GetInterval (void);
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
|
||
|
|
osStatus_t osKernelInitialize (void) {
|
||
|
|
8002f44: b580 push {r7, lr}
|
||
|
|
8002f46: b082 sub sp, #8
|
||
|
|
8002f48: af00 add r7, sp, #0
|
||
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||
|
|
8002f4a: f3ef 8305 mrs r3, IPSR
|
||
|
|
8002f4e: 603b str r3, [r7, #0]
|
||
|
|
return(result);
|
||
|
|
8002f50: 683b ldr r3, [r7, #0]
|
||
|
|
osStatus_t stat;
|
||
|
|
|
||
|
|
if (IS_IRQ()) {
|
||
|
|
8002f52: 2b00 cmp r3, #0
|
||
|
|
8002f54: d003 beq.n 8002f5e <osKernelInitialize+0x1a>
|
||
|
|
stat = osErrorISR;
|
||
|
|
8002f56: f06f 0305 mvn.w r3, #5
|
||
|
|
8002f5a: 607b str r3, [r7, #4]
|
||
|
|
8002f5c: e00f b.n 8002f7e <osKernelInitialize+0x3a>
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
if (KernelState == osKernelInactive) {
|
||
|
|
8002f5e: 4b0a ldr r3, [pc, #40] ; (8002f88 <osKernelInitialize+0x44>)
|
||
|
|
8002f60: 681b ldr r3, [r3, #0]
|
||
|
|
8002f62: 2b00 cmp r3, #0
|
||
|
|
8002f64: d108 bne.n 8002f78 <osKernelInitialize+0x34>
|
||
|
|
#if defined(USE_TRACE_EVENT_RECORDER)
|
||
|
|
EvrFreeRTOSSetup(0U);
|
||
|
|
#endif
|
||
|
|
#if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
|
||
|
|
vPortDefineHeapRegions (configHEAP_5_REGIONS);
|
||
|
|
8002f66: 4809 ldr r0, [pc, #36] ; (8002f8c <osKernelInitialize+0x48>)
|
||
|
|
8002f68: f002 fce6 bl 8005938 <vPortDefineHeapRegions>
|
||
|
|
#endif
|
||
|
|
KernelState = osKernelReady;
|
||
|
|
8002f6c: 4b06 ldr r3, [pc, #24] ; (8002f88 <osKernelInitialize+0x44>)
|
||
|
|
8002f6e: 2201 movs r2, #1
|
||
|
|
8002f70: 601a str r2, [r3, #0]
|
||
|
|
stat = osOK;
|
||
|
|
8002f72: 2300 movs r3, #0
|
||
|
|
8002f74: 607b str r3, [r7, #4]
|
||
|
|
8002f76: e002 b.n 8002f7e <osKernelInitialize+0x3a>
|
||
|
|
} else {
|
||
|
|
stat = osError;
|
||
|
|
8002f78: f04f 33ff mov.w r3, #4294967295
|
||
|
|
8002f7c: 607b str r3, [r7, #4]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return (stat);
|
||
|
|
8002f7e: 687b ldr r3, [r7, #4]
|
||
|
|
}
|
||
|
|
8002f80: 4618 mov r0, r3
|
||
|
|
8002f82: 3708 adds r7, #8
|
||
|
|
8002f84: 46bd mov sp, r7
|
||
|
|
8002f86: bd80 pop {r7, pc}
|
||
|
|
8002f88: 2000012c .word 0x2000012c
|
||
|
|
8002f8c: 2000000c .word 0x2000000c
|
||
|
|
|
||
|
|
08002f90 <osKernelStart>:
|
||
|
|
}
|
||
|
|
|
||
|
|
return (state);
|
||
|
|
}
|
||
|
|
|
||
|
|
osStatus_t osKernelStart (void) {
|
||
|
|
8002f90: b580 push {r7, lr}
|
||
|
|
8002f92: b082 sub sp, #8
|
||
|
|
8002f94: af00 add r7, sp, #0
|
||
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||
|
|
8002f96: f3ef 8305 mrs r3, IPSR
|
||
|
|
8002f9a: 603b str r3, [r7, #0]
|
||
|
|
return(result);
|
||
|
|
8002f9c: 683b ldr r3, [r7, #0]
|
||
|
|
osStatus_t stat;
|
||
|
|
|
||
|
|
if (IS_IRQ()) {
|
||
|
|
8002f9e: 2b00 cmp r3, #0
|
||
|
|
8002fa0: d003 beq.n 8002faa <osKernelStart+0x1a>
|
||
|
|
stat = osErrorISR;
|
||
|
|
8002fa2: f06f 0305 mvn.w r3, #5
|
||
|
|
8002fa6: 607b str r3, [r7, #4]
|
||
|
|
8002fa8: e010 b.n 8002fcc <osKernelStart+0x3c>
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
if (KernelState == osKernelReady) {
|
||
|
|
8002faa: 4b0b ldr r3, [pc, #44] ; (8002fd8 <osKernelStart+0x48>)
|
||
|
|
8002fac: 681b ldr r3, [r3, #0]
|
||
|
|
8002fae: 2b01 cmp r3, #1
|
||
|
|
8002fb0: d109 bne.n 8002fc6 <osKernelStart+0x36>
|
||
|
|
/* Ensure SVC priority is at the reset value */
|
||
|
|
SVC_Setup();
|
||
|
|
8002fb2: f7ff ffbd bl 8002f30 <SVC_Setup>
|
||
|
|
/* Change state to enable IRQ masking check */
|
||
|
|
KernelState = osKernelRunning;
|
||
|
|
8002fb6: 4b08 ldr r3, [pc, #32] ; (8002fd8 <osKernelStart+0x48>)
|
||
|
|
8002fb8: 2202 movs r2, #2
|
||
|
|
8002fba: 601a str r2, [r3, #0]
|
||
|
|
/* Start the kernel scheduler */
|
||
|
|
vTaskStartScheduler();
|
||
|
|
8002fbc: f001 f87c bl 80040b8 <vTaskStartScheduler>
|
||
|
|
stat = osOK;
|
||
|
|
8002fc0: 2300 movs r3, #0
|
||
|
|
8002fc2: 607b str r3, [r7, #4]
|
||
|
|
8002fc4: e002 b.n 8002fcc <osKernelStart+0x3c>
|
||
|
|
} else {
|
||
|
|
stat = osError;
|
||
|
|
8002fc6: f04f 33ff mov.w r3, #4294967295
|
||
|
|
8002fca: 607b str r3, [r7, #4]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return (stat);
|
||
|
|
8002fcc: 687b ldr r3, [r7, #4]
|
||
|
|
}
|
||
|
|
8002fce: 4618 mov r0, r3
|
||
|
|
8002fd0: 3708 adds r7, #8
|
||
|
|
8002fd2: 46bd mov sp, r7
|
||
|
|
8002fd4: bd80 pop {r7, pc}
|
||
|
|
8002fd6: bf00 nop
|
||
|
|
8002fd8: 2000012c .word 0x2000012c
|
||
|
|
|
||
|
|
08002fdc <osThreadNew>:
|
||
|
|
return (configCPU_CLOCK_HZ);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
|
||
|
|
osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
|
||
|
|
8002fdc: b580 push {r7, lr}
|
||
|
|
8002fde: b08e sub sp, #56 ; 0x38
|
||
|
|
8002fe0: af04 add r7, sp, #16
|
||
|
|
8002fe2: 60f8 str r0, [r7, #12]
|
||
|
|
8002fe4: 60b9 str r1, [r7, #8]
|
||
|
|
8002fe6: 607a str r2, [r7, #4]
|
||
|
|
uint32_t stack;
|
||
|
|
TaskHandle_t hTask;
|
||
|
|
UBaseType_t prio;
|
||
|
|
int32_t mem;
|
||
|
|
|
||
|
|
hTask = NULL;
|
||
|
|
8002fe8: 2300 movs r3, #0
|
||
|
|
8002fea: 613b str r3, [r7, #16]
|
||
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||
|
|
8002fec: f3ef 8305 mrs r3, IPSR
|
||
|
|
8002ff0: 617b str r3, [r7, #20]
|
||
|
|
return(result);
|
||
|
|
8002ff2: 697b ldr r3, [r7, #20]
|
||
|
|
|
||
|
|
if (!IS_IRQ() && (func != NULL)) {
|
||
|
|
8002ff4: 2b00 cmp r3, #0
|
||
|
|
8002ff6: d17e bne.n 80030f6 <osThreadNew+0x11a>
|
||
|
|
8002ff8: 68fb ldr r3, [r7, #12]
|
||
|
|
8002ffa: 2b00 cmp r3, #0
|
||
|
|
8002ffc: d07b beq.n 80030f6 <osThreadNew+0x11a>
|
||
|
|
stack = configMINIMAL_STACK_SIZE;
|
||
|
|
8002ffe: 2380 movs r3, #128 ; 0x80
|
||
|
|
8003000: 623b str r3, [r7, #32]
|
||
|
|
prio = (UBaseType_t)osPriorityNormal;
|
||
|
|
8003002: 2318 movs r3, #24
|
||
|
|
8003004: 61fb str r3, [r7, #28]
|
||
|
|
|
||
|
|
name = NULL;
|
||
|
|
8003006: 2300 movs r3, #0
|
||
|
|
8003008: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
mem = -1;
|
||
|
|
800300a: f04f 33ff mov.w r3, #4294967295
|
||
|
|
800300e: 61bb str r3, [r7, #24]
|
||
|
|
|
||
|
|
if (attr != NULL) {
|
||
|
|
8003010: 687b ldr r3, [r7, #4]
|
||
|
|
8003012: 2b00 cmp r3, #0
|
||
|
|
8003014: d045 beq.n 80030a2 <osThreadNew+0xc6>
|
||
|
|
if (attr->name != NULL) {
|
||
|
|
8003016: 687b ldr r3, [r7, #4]
|
||
|
|
8003018: 681b ldr r3, [r3, #0]
|
||
|
|
800301a: 2b00 cmp r3, #0
|
||
|
|
800301c: d002 beq.n 8003024 <osThreadNew+0x48>
|
||
|
|
name = attr->name;
|
||
|
|
800301e: 687b ldr r3, [r7, #4]
|
||
|
|
8003020: 681b ldr r3, [r3, #0]
|
||
|
|
8003022: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
}
|
||
|
|
if (attr->priority != osPriorityNone) {
|
||
|
|
8003024: 687b ldr r3, [r7, #4]
|
||
|
|
8003026: 699b ldr r3, [r3, #24]
|
||
|
|
8003028: 2b00 cmp r3, #0
|
||
|
|
800302a: d002 beq.n 8003032 <osThreadNew+0x56>
|
||
|
|
prio = (UBaseType_t)attr->priority;
|
||
|
|
800302c: 687b ldr r3, [r7, #4]
|
||
|
|
800302e: 699b ldr r3, [r3, #24]
|
||
|
|
8003030: 61fb str r3, [r7, #28]
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
|
||
|
|
8003032: 69fb ldr r3, [r7, #28]
|
||
|
|
8003034: 2b00 cmp r3, #0
|
||
|
|
8003036: d008 beq.n 800304a <osThreadNew+0x6e>
|
||
|
|
8003038: 69fb ldr r3, [r7, #28]
|
||
|
|
800303a: 2b38 cmp r3, #56 ; 0x38
|
||
|
|
800303c: d805 bhi.n 800304a <osThreadNew+0x6e>
|
||
|
|
800303e: 687b ldr r3, [r7, #4]
|
||
|
|
8003040: 685b ldr r3, [r3, #4]
|
||
|
|
8003042: f003 0301 and.w r3, r3, #1
|
||
|
|
8003046: 2b00 cmp r3, #0
|
||
|
|
8003048: d001 beq.n 800304e <osThreadNew+0x72>
|
||
|
|
return (NULL);
|
||
|
|
800304a: 2300 movs r3, #0
|
||
|
|
800304c: e054 b.n 80030f8 <osThreadNew+0x11c>
|
||
|
|
}
|
||
|
|
|
||
|
|
if (attr->stack_size > 0U) {
|
||
|
|
800304e: 687b ldr r3, [r7, #4]
|
||
|
|
8003050: 695b ldr r3, [r3, #20]
|
||
|
|
8003052: 2b00 cmp r3, #0
|
||
|
|
8003054: d003 beq.n 800305e <osThreadNew+0x82>
|
||
|
|
/* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */
|
||
|
|
/* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
|
||
|
|
stack = attr->stack_size / sizeof(StackType_t);
|
||
|
|
8003056: 687b ldr r3, [r7, #4]
|
||
|
|
8003058: 695b ldr r3, [r3, #20]
|
||
|
|
800305a: 089b lsrs r3, r3, #2
|
||
|
|
800305c: 623b str r3, [r7, #32]
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
|
||
|
|
800305e: 687b ldr r3, [r7, #4]
|
||
|
|
8003060: 689b ldr r3, [r3, #8]
|
||
|
|
8003062: 2b00 cmp r3, #0
|
||
|
|
8003064: d00e beq.n 8003084 <osThreadNew+0xa8>
|
||
|
|
8003066: 687b ldr r3, [r7, #4]
|
||
|
|
8003068: 68db ldr r3, [r3, #12]
|
||
|
|
800306a: 2bbb cmp r3, #187 ; 0xbb
|
||
|
|
800306c: d90a bls.n 8003084 <osThreadNew+0xa8>
|
||
|
|
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
|
||
|
|
800306e: 687b ldr r3, [r7, #4]
|
||
|
|
8003070: 691b ldr r3, [r3, #16]
|
||
|
|
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
|
||
|
|
8003072: 2b00 cmp r3, #0
|
||
|
|
8003074: d006 beq.n 8003084 <osThreadNew+0xa8>
|
||
|
|
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
|
||
|
|
8003076: 687b ldr r3, [r7, #4]
|
||
|
|
8003078: 695b ldr r3, [r3, #20]
|
||
|
|
800307a: 2b00 cmp r3, #0
|
||
|
|
800307c: d002 beq.n 8003084 <osThreadNew+0xa8>
|
||
|
|
mem = 1;
|
||
|
|
800307e: 2301 movs r3, #1
|
||
|
|
8003080: 61bb str r3, [r7, #24]
|
||
|
|
8003082: e010 b.n 80030a6 <osThreadNew+0xca>
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
|
||
|
|
8003084: 687b ldr r3, [r7, #4]
|
||
|
|
8003086: 689b ldr r3, [r3, #8]
|
||
|
|
8003088: 2b00 cmp r3, #0
|
||
|
|
800308a: d10c bne.n 80030a6 <osThreadNew+0xca>
|
||
|
|
800308c: 687b ldr r3, [r7, #4]
|
||
|
|
800308e: 68db ldr r3, [r3, #12]
|
||
|
|
8003090: 2b00 cmp r3, #0
|
||
|
|
8003092: d108 bne.n 80030a6 <osThreadNew+0xca>
|
||
|
|
8003094: 687b ldr r3, [r7, #4]
|
||
|
|
8003096: 691b ldr r3, [r3, #16]
|
||
|
|
8003098: 2b00 cmp r3, #0
|
||
|
|
800309a: d104 bne.n 80030a6 <osThreadNew+0xca>
|
||
|
|
mem = 0;
|
||
|
|
800309c: 2300 movs r3, #0
|
||
|
|
800309e: 61bb str r3, [r7, #24]
|
||
|
|
80030a0: e001 b.n 80030a6 <osThreadNew+0xca>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
mem = 0;
|
||
|
|
80030a2: 2300 movs r3, #0
|
||
|
|
80030a4: 61bb str r3, [r7, #24]
|
||
|
|
}
|
||
|
|
|
||
|
|
if (mem == 1) {
|
||
|
|
80030a6: 69bb ldr r3, [r7, #24]
|
||
|
|
80030a8: 2b01 cmp r3, #1
|
||
|
|
80030aa: d110 bne.n 80030ce <osThreadNew+0xf2>
|
||
|
|
#if (configSUPPORT_STATIC_ALLOCATION == 1)
|
||
|
|
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
|
||
|
|
80030ac: 687b ldr r3, [r7, #4]
|
||
|
|
80030ae: 691b ldr r3, [r3, #16]
|
||
|
|
(StaticTask_t *)attr->cb_mem);
|
||
|
|
80030b0: 687a ldr r2, [r7, #4]
|
||
|
|
80030b2: 6892 ldr r2, [r2, #8]
|
||
|
|
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
|
||
|
|
80030b4: 9202 str r2, [sp, #8]
|
||
|
|
80030b6: 9301 str r3, [sp, #4]
|
||
|
|
80030b8: 69fb ldr r3, [r7, #28]
|
||
|
|
80030ba: 9300 str r3, [sp, #0]
|
||
|
|
80030bc: 68bb ldr r3, [r7, #8]
|
||
|
|
80030be: 6a3a ldr r2, [r7, #32]
|
||
|
|
80030c0: 6a79 ldr r1, [r7, #36] ; 0x24
|
||
|
|
80030c2: 68f8 ldr r0, [r7, #12]
|
||
|
|
80030c4: f000 fe0c bl 8003ce0 <xTaskCreateStatic>
|
||
|
|
80030c8: 4603 mov r3, r0
|
||
|
|
80030ca: 613b str r3, [r7, #16]
|
||
|
|
80030cc: e013 b.n 80030f6 <osThreadNew+0x11a>
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
if (mem == 0) {
|
||
|
|
80030ce: 69bb ldr r3, [r7, #24]
|
||
|
|
80030d0: 2b00 cmp r3, #0
|
||
|
|
80030d2: d110 bne.n 80030f6 <osThreadNew+0x11a>
|
||
|
|
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
|
||
|
|
if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
|
||
|
|
80030d4: 6a3b ldr r3, [r7, #32]
|
||
|
|
80030d6: b29a uxth r2, r3
|
||
|
|
80030d8: f107 0310 add.w r3, r7, #16
|
||
|
|
80030dc: 9301 str r3, [sp, #4]
|
||
|
|
80030de: 69fb ldr r3, [r7, #28]
|
||
|
|
80030e0: 9300 str r3, [sp, #0]
|
||
|
|
80030e2: 68bb ldr r3, [r7, #8]
|
||
|
|
80030e4: 6a79 ldr r1, [r7, #36] ; 0x24
|
||
|
|
80030e6: 68f8 ldr r0, [r7, #12]
|
||
|
|
80030e8: f000 fe57 bl 8003d9a <xTaskCreate>
|
||
|
|
80030ec: 4603 mov r3, r0
|
||
|
|
80030ee: 2b01 cmp r3, #1
|
||
|
|
80030f0: d001 beq.n 80030f6 <osThreadNew+0x11a>
|
||
|
|
hTask = NULL;
|
||
|
|
80030f2: 2300 movs r3, #0
|
||
|
|
80030f4: 613b str r3, [r7, #16]
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return ((osThreadId_t)hTask);
|
||
|
|
80030f6: 693b ldr r3, [r7, #16]
|
||
|
|
}
|
||
|
|
80030f8: 4618 mov r0, r3
|
||
|
|
80030fa: 3728 adds r7, #40 ; 0x28
|
||
|
|
80030fc: 46bd mov sp, r7
|
||
|
|
80030fe: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08003100 <osDelay>:
|
||
|
|
/* Return flags before clearing */
|
||
|
|
return (rflags);
|
||
|
|
}
|
||
|
|
#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */
|
||
|
|
|
||
|
|
osStatus_t osDelay (uint32_t ticks) {
|
||
|
|
8003100: b580 push {r7, lr}
|
||
|
|
8003102: b084 sub sp, #16
|
||
|
|
8003104: af00 add r7, sp, #0
|
||
|
|
8003106: 6078 str r0, [r7, #4]
|
||
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||
|
|
8003108: f3ef 8305 mrs r3, IPSR
|
||
|
|
800310c: 60bb str r3, [r7, #8]
|
||
|
|
return(result);
|
||
|
|
800310e: 68bb ldr r3, [r7, #8]
|
||
|
|
osStatus_t stat;
|
||
|
|
|
||
|
|
if (IS_IRQ()) {
|
||
|
|
8003110: 2b00 cmp r3, #0
|
||
|
|
8003112: d003 beq.n 800311c <osDelay+0x1c>
|
||
|
|
stat = osErrorISR;
|
||
|
|
8003114: f06f 0305 mvn.w r3, #5
|
||
|
|
8003118: 60fb str r3, [r7, #12]
|
||
|
|
800311a: e007 b.n 800312c <osDelay+0x2c>
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
stat = osOK;
|
||
|
|
800311c: 2300 movs r3, #0
|
||
|
|
800311e: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
if (ticks != 0U) {
|
||
|
|
8003120: 687b ldr r3, [r7, #4]
|
||
|
|
8003122: 2b00 cmp r3, #0
|
||
|
|
8003124: d002 beq.n 800312c <osDelay+0x2c>
|
||
|
|
vTaskDelay(ticks);
|
||
|
|
8003126: 6878 ldr r0, [r7, #4]
|
||
|
|
8003128: f000 ff92 bl 8004050 <vTaskDelay>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return (stat);
|
||
|
|
800312c: 68fb ldr r3, [r7, #12]
|
||
|
|
}
|
||
|
|
800312e: 4618 mov r0, r3
|
||
|
|
8003130: 3710 adds r7, #16
|
||
|
|
8003132: 46bd mov sp, r7
|
||
|
|
8003134: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
08003138 <vApplicationGetIdleTaskMemory>:
|
||
|
|
|
||
|
|
/*
|
||
|
|
vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
|
||
|
|
equals to 1 and is required for static memory allocation support.
|
||
|
|
*/
|
||
|
|
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
|
||
|
|
8003138: b480 push {r7}
|
||
|
|
800313a: b085 sub sp, #20
|
||
|
|
800313c: af00 add r7, sp, #0
|
||
|
|
800313e: 60f8 str r0, [r7, #12]
|
||
|
|
8003140: 60b9 str r1, [r7, #8]
|
||
|
|
8003142: 607a str r2, [r7, #4]
|
||
|
|
/* Idle task control block and stack */
|
||
|
|
static StaticTask_t Idle_TCB;
|
||
|
|
static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE];
|
||
|
|
|
||
|
|
*ppxIdleTaskTCBBuffer = &Idle_TCB;
|
||
|
|
8003144: 68fb ldr r3, [r7, #12]
|
||
|
|
8003146: 4a07 ldr r2, [pc, #28] ; (8003164 <vApplicationGetIdleTaskMemory+0x2c>)
|
||
|
|
8003148: 601a str r2, [r3, #0]
|
||
|
|
*ppxIdleTaskStackBuffer = &Idle_Stack[0];
|
||
|
|
800314a: 68bb ldr r3, [r7, #8]
|
||
|
|
800314c: 4a06 ldr r2, [pc, #24] ; (8003168 <vApplicationGetIdleTaskMemory+0x30>)
|
||
|
|
800314e: 601a str r2, [r3, #0]
|
||
|
|
*pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
|
||
|
|
8003150: 687b ldr r3, [r7, #4]
|
||
|
|
8003152: 2280 movs r2, #128 ; 0x80
|
||
|
|
8003154: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
8003156: bf00 nop
|
||
|
|
8003158: 3714 adds r7, #20
|
||
|
|
800315a: 46bd mov sp, r7
|
||
|
|
800315c: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8003160: 4770 bx lr
|
||
|
|
8003162: bf00 nop
|
||
|
|
8003164: 20003010 .word 0x20003010
|
||
|
|
8003168: 200030cc .word 0x200030cc
|
||
|
|
|
||
|
|
0800316c <vApplicationGetTimerTaskMemory>:
|
||
|
|
|
||
|
|
/*
|
||
|
|
vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
|
||
|
|
equals to 1 and is required for static memory allocation support.
|
||
|
|
*/
|
||
|
|
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
|
||
|
|
800316c: b480 push {r7}
|
||
|
|
800316e: b085 sub sp, #20
|
||
|
|
8003170: af00 add r7, sp, #0
|
||
|
|
8003172: 60f8 str r0, [r7, #12]
|
||
|
|
8003174: 60b9 str r1, [r7, #8]
|
||
|
|
8003176: 607a str r2, [r7, #4]
|
||
|
|
/* Timer task control block and stack */
|
||
|
|
static StaticTask_t Timer_TCB;
|
||
|
|
static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH];
|
||
|
|
|
||
|
|
*ppxTimerTaskTCBBuffer = &Timer_TCB;
|
||
|
|
8003178: 68fb ldr r3, [r7, #12]
|
||
|
|
800317a: 4a07 ldr r2, [pc, #28] ; (8003198 <vApplicationGetTimerTaskMemory+0x2c>)
|
||
|
|
800317c: 601a str r2, [r3, #0]
|
||
|
|
*ppxTimerTaskStackBuffer = &Timer_Stack[0];
|
||
|
|
800317e: 68bb ldr r3, [r7, #8]
|
||
|
|
8003180: 4a06 ldr r2, [pc, #24] ; (800319c <vApplicationGetTimerTaskMemory+0x30>)
|
||
|
|
8003182: 601a str r2, [r3, #0]
|
||
|
|
*pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
|
||
|
|
8003184: 687b ldr r3, [r7, #4]
|
||
|
|
8003186: f44f 7280 mov.w r2, #256 ; 0x100
|
||
|
|
800318a: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
800318c: bf00 nop
|
||
|
|
800318e: 3714 adds r7, #20
|
||
|
|
8003190: 46bd mov sp, r7
|
||
|
|
8003192: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8003196: 4770 bx lr
|
||
|
|
8003198: 200032cc .word 0x200032cc
|
||
|
|
800319c: 20003388 .word 0x20003388
|
||
|
|
|
||
|
|
080031a0 <vListInitialise>:
|
||
|
|
/*-----------------------------------------------------------
|
||
|
|
* PUBLIC LIST API documented in list.h
|
||
|
|
*----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vListInitialise( List_t * const pxList )
|
||
|
|
{
|
||
|
|
80031a0: b480 push {r7}
|
||
|
|
80031a2: b083 sub sp, #12
|
||
|
|
80031a4: af00 add r7, sp, #0
|
||
|
|
80031a6: 6078 str r0, [r7, #4]
|
||
|
|
/* The list structure contains a list item which is used to mark the
|
||
|
|
end of the list. To initialise the list the list end is inserted
|
||
|
|
as the only list entry. */
|
||
|
|
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||
|
|
80031a8: 687b ldr r3, [r7, #4]
|
||
|
|
80031aa: f103 0208 add.w r2, r3, #8
|
||
|
|
80031ae: 687b ldr r3, [r7, #4]
|
||
|
|
80031b0: 605a str r2, [r3, #4]
|
||
|
|
|
||
|
|
/* The list end value is the highest possible value in the list to
|
||
|
|
ensure it remains at the end of the list. */
|
||
|
|
pxList->xListEnd.xItemValue = portMAX_DELAY;
|
||
|
|
80031b2: 687b ldr r3, [r7, #4]
|
||
|
|
80031b4: f04f 32ff mov.w r2, #4294967295
|
||
|
|
80031b8: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
/* The list end next and previous pointers point to itself so we know
|
||
|
|
when the list is empty. */
|
||
|
|
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||
|
|
80031ba: 687b ldr r3, [r7, #4]
|
||
|
|
80031bc: f103 0208 add.w r2, r3, #8
|
||
|
|
80031c0: 687b ldr r3, [r7, #4]
|
||
|
|
80031c2: 60da str r2, [r3, #12]
|
||
|
|
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||
|
|
80031c4: 687b ldr r3, [r7, #4]
|
||
|
|
80031c6: f103 0208 add.w r2, r3, #8
|
||
|
|
80031ca: 687b ldr r3, [r7, #4]
|
||
|
|
80031cc: 611a str r2, [r3, #16]
|
||
|
|
|
||
|
|
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
|
||
|
|
80031ce: 687b ldr r3, [r7, #4]
|
||
|
|
80031d0: 2200 movs r2, #0
|
||
|
|
80031d2: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Write known values into the list if
|
||
|
|
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||
|
|
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
|
||
|
|
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
|
||
|
|
}
|
||
|
|
80031d4: bf00 nop
|
||
|
|
80031d6: 370c adds r7, #12
|
||
|
|
80031d8: 46bd mov sp, r7
|
||
|
|
80031da: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80031de: 4770 bx lr
|
||
|
|
|
||
|
|
080031e0 <vListInitialiseItem>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vListInitialiseItem( ListItem_t * const pxItem )
|
||
|
|
{
|
||
|
|
80031e0: b480 push {r7}
|
||
|
|
80031e2: b083 sub sp, #12
|
||
|
|
80031e4: af00 add r7, sp, #0
|
||
|
|
80031e6: 6078 str r0, [r7, #4]
|
||
|
|
/* Make sure the list item is not recorded as being on a list. */
|
||
|
|
pxItem->pxContainer = NULL;
|
||
|
|
80031e8: 687b ldr r3, [r7, #4]
|
||
|
|
80031ea: 2200 movs r2, #0
|
||
|
|
80031ec: 611a str r2, [r3, #16]
|
||
|
|
|
||
|
|
/* Write known values into the list item if
|
||
|
|
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||
|
|
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
||
|
|
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
||
|
|
}
|
||
|
|
80031ee: bf00 nop
|
||
|
|
80031f0: 370c adds r7, #12
|
||
|
|
80031f2: 46bd mov sp, r7
|
||
|
|
80031f4: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80031f8: 4770 bx lr
|
||
|
|
|
||
|
|
080031fa <vListInsertEnd>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
|
||
|
|
{
|
||
|
|
80031fa: b480 push {r7}
|
||
|
|
80031fc: b085 sub sp, #20
|
||
|
|
80031fe: af00 add r7, sp, #0
|
||
|
|
8003200: 6078 str r0, [r7, #4]
|
||
|
|
8003202: 6039 str r1, [r7, #0]
|
||
|
|
ListItem_t * const pxIndex = pxList->pxIndex;
|
||
|
|
8003204: 687b ldr r3, [r7, #4]
|
||
|
|
8003206: 685b ldr r3, [r3, #4]
|
||
|
|
8003208: 60fb str r3, [r7, #12]
|
||
|
|
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
|
||
|
|
|
||
|
|
/* Insert a new list item into pxList, but rather than sort the list,
|
||
|
|
makes the new list item the last item to be removed by a call to
|
||
|
|
listGET_OWNER_OF_NEXT_ENTRY(). */
|
||
|
|
pxNewListItem->pxNext = pxIndex;
|
||
|
|
800320a: 683b ldr r3, [r7, #0]
|
||
|
|
800320c: 68fa ldr r2, [r7, #12]
|
||
|
|
800320e: 605a str r2, [r3, #4]
|
||
|
|
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
|
||
|
|
8003210: 68fb ldr r3, [r7, #12]
|
||
|
|
8003212: 689a ldr r2, [r3, #8]
|
||
|
|
8003214: 683b ldr r3, [r7, #0]
|
||
|
|
8003216: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
/* Only used during decision coverage testing. */
|
||
|
|
mtCOVERAGE_TEST_DELAY();
|
||
|
|
|
||
|
|
pxIndex->pxPrevious->pxNext = pxNewListItem;
|
||
|
|
8003218: 68fb ldr r3, [r7, #12]
|
||
|
|
800321a: 689b ldr r3, [r3, #8]
|
||
|
|
800321c: 683a ldr r2, [r7, #0]
|
||
|
|
800321e: 605a str r2, [r3, #4]
|
||
|
|
pxIndex->pxPrevious = pxNewListItem;
|
||
|
|
8003220: 68fb ldr r3, [r7, #12]
|
||
|
|
8003222: 683a ldr r2, [r7, #0]
|
||
|
|
8003224: 609a str r2, [r3, #8]
|
||
|
|
|
||
|
|
/* Remember which list the item is in. */
|
||
|
|
pxNewListItem->pxContainer = pxList;
|
||
|
|
8003226: 683b ldr r3, [r7, #0]
|
||
|
|
8003228: 687a ldr r2, [r7, #4]
|
||
|
|
800322a: 611a str r2, [r3, #16]
|
||
|
|
|
||
|
|
( pxList->uxNumberOfItems )++;
|
||
|
|
800322c: 687b ldr r3, [r7, #4]
|
||
|
|
800322e: 681b ldr r3, [r3, #0]
|
||
|
|
8003230: 1c5a adds r2, r3, #1
|
||
|
|
8003232: 687b ldr r3, [r7, #4]
|
||
|
|
8003234: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
8003236: bf00 nop
|
||
|
|
8003238: 3714 adds r7, #20
|
||
|
|
800323a: 46bd mov sp, r7
|
||
|
|
800323c: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8003240: 4770 bx lr
|
||
|
|
|
||
|
|
08003242 <vListInsert>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
|
||
|
|
{
|
||
|
|
8003242: b480 push {r7}
|
||
|
|
8003244: b085 sub sp, #20
|
||
|
|
8003246: af00 add r7, sp, #0
|
||
|
|
8003248: 6078 str r0, [r7, #4]
|
||
|
|
800324a: 6039 str r1, [r7, #0]
|
||
|
|
ListItem_t *pxIterator;
|
||
|
|
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
|
||
|
|
800324c: 683b ldr r3, [r7, #0]
|
||
|
|
800324e: 681b ldr r3, [r3, #0]
|
||
|
|
8003250: 60bb str r3, [r7, #8]
|
||
|
|
new list item should be placed after it. This ensures that TCBs which are
|
||
|
|
stored in ready lists (all of which have the same xItemValue value) get a
|
||
|
|
share of the CPU. However, if the xItemValue is the same as the back marker
|
||
|
|
the iteration loop below will not end. Therefore the value is checked
|
||
|
|
first, and the algorithm slightly modified if necessary. */
|
||
|
|
if( xValueOfInsertion == portMAX_DELAY )
|
||
|
|
8003252: 68bb ldr r3, [r7, #8]
|
||
|
|
8003254: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
8003258: d103 bne.n 8003262 <vListInsert+0x20>
|
||
|
|
{
|
||
|
|
pxIterator = pxList->xListEnd.pxPrevious;
|
||
|
|
800325a: 687b ldr r3, [r7, #4]
|
||
|
|
800325c: 691b ldr r3, [r3, #16]
|
||
|
|
800325e: 60fb str r3, [r7, #12]
|
||
|
|
8003260: e00c b.n 800327c <vListInsert+0x3a>
|
||
|
|
4) Using a queue or semaphore before it has been initialised or
|
||
|
|
before the scheduler has been started (are interrupts firing
|
||
|
|
before vTaskStartScheduler() has been called?).
|
||
|
|
**********************************************************************/
|
||
|
|
|
||
|
|
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
|
||
|
|
8003262: 687b ldr r3, [r7, #4]
|
||
|
|
8003264: 3308 adds r3, #8
|
||
|
|
8003266: 60fb str r3, [r7, #12]
|
||
|
|
8003268: e002 b.n 8003270 <vListInsert+0x2e>
|
||
|
|
800326a: 68fb ldr r3, [r7, #12]
|
||
|
|
800326c: 685b ldr r3, [r3, #4]
|
||
|
|
800326e: 60fb str r3, [r7, #12]
|
||
|
|
8003270: 68fb ldr r3, [r7, #12]
|
||
|
|
8003272: 685b ldr r3, [r3, #4]
|
||
|
|
8003274: 681b ldr r3, [r3, #0]
|
||
|
|
8003276: 68ba ldr r2, [r7, #8]
|
||
|
|
8003278: 429a cmp r2, r3
|
||
|
|
800327a: d2f6 bcs.n 800326a <vListInsert+0x28>
|
||
|
|
/* There is nothing to do here, just iterating to the wanted
|
||
|
|
insertion position. */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
pxNewListItem->pxNext = pxIterator->pxNext;
|
||
|
|
800327c: 68fb ldr r3, [r7, #12]
|
||
|
|
800327e: 685a ldr r2, [r3, #4]
|
||
|
|
8003280: 683b ldr r3, [r7, #0]
|
||
|
|
8003282: 605a str r2, [r3, #4]
|
||
|
|
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
|
||
|
|
8003284: 683b ldr r3, [r7, #0]
|
||
|
|
8003286: 685b ldr r3, [r3, #4]
|
||
|
|
8003288: 683a ldr r2, [r7, #0]
|
||
|
|
800328a: 609a str r2, [r3, #8]
|
||
|
|
pxNewListItem->pxPrevious = pxIterator;
|
||
|
|
800328c: 683b ldr r3, [r7, #0]
|
||
|
|
800328e: 68fa ldr r2, [r7, #12]
|
||
|
|
8003290: 609a str r2, [r3, #8]
|
||
|
|
pxIterator->pxNext = pxNewListItem;
|
||
|
|
8003292: 68fb ldr r3, [r7, #12]
|
||
|
|
8003294: 683a ldr r2, [r7, #0]
|
||
|
|
8003296: 605a str r2, [r3, #4]
|
||
|
|
|
||
|
|
/* Remember which list the item is in. This allows fast removal of the
|
||
|
|
item later. */
|
||
|
|
pxNewListItem->pxContainer = pxList;
|
||
|
|
8003298: 683b ldr r3, [r7, #0]
|
||
|
|
800329a: 687a ldr r2, [r7, #4]
|
||
|
|
800329c: 611a str r2, [r3, #16]
|
||
|
|
|
||
|
|
( pxList->uxNumberOfItems )++;
|
||
|
|
800329e: 687b ldr r3, [r7, #4]
|
||
|
|
80032a0: 681b ldr r3, [r3, #0]
|
||
|
|
80032a2: 1c5a adds r2, r3, #1
|
||
|
|
80032a4: 687b ldr r3, [r7, #4]
|
||
|
|
80032a6: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
80032a8: bf00 nop
|
||
|
|
80032aa: 3714 adds r7, #20
|
||
|
|
80032ac: 46bd mov sp, r7
|
||
|
|
80032ae: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80032b2: 4770 bx lr
|
||
|
|
|
||
|
|
080032b4 <uxListRemove>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
|
||
|
|
{
|
||
|
|
80032b4: b480 push {r7}
|
||
|
|
80032b6: b085 sub sp, #20
|
||
|
|
80032b8: af00 add r7, sp, #0
|
||
|
|
80032ba: 6078 str r0, [r7, #4]
|
||
|
|
/* The list item knows which list it is in. Obtain the list from the list
|
||
|
|
item. */
|
||
|
|
List_t * const pxList = pxItemToRemove->pxContainer;
|
||
|
|
80032bc: 687b ldr r3, [r7, #4]
|
||
|
|
80032be: 691b ldr r3, [r3, #16]
|
||
|
|
80032c0: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
|
||
|
|
80032c2: 687b ldr r3, [r7, #4]
|
||
|
|
80032c4: 685b ldr r3, [r3, #4]
|
||
|
|
80032c6: 687a ldr r2, [r7, #4]
|
||
|
|
80032c8: 6892 ldr r2, [r2, #8]
|
||
|
|
80032ca: 609a str r2, [r3, #8]
|
||
|
|
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
|
||
|
|
80032cc: 687b ldr r3, [r7, #4]
|
||
|
|
80032ce: 689b ldr r3, [r3, #8]
|
||
|
|
80032d0: 687a ldr r2, [r7, #4]
|
||
|
|
80032d2: 6852 ldr r2, [r2, #4]
|
||
|
|
80032d4: 605a str r2, [r3, #4]
|
||
|
|
|
||
|
|
/* Only used during decision coverage testing. */
|
||
|
|
mtCOVERAGE_TEST_DELAY();
|
||
|
|
|
||
|
|
/* Make sure the index is left pointing to a valid item. */
|
||
|
|
if( pxList->pxIndex == pxItemToRemove )
|
||
|
|
80032d6: 68fb ldr r3, [r7, #12]
|
||
|
|
80032d8: 685b ldr r3, [r3, #4]
|
||
|
|
80032da: 687a ldr r2, [r7, #4]
|
||
|
|
80032dc: 429a cmp r2, r3
|
||
|
|
80032de: d103 bne.n 80032e8 <uxListRemove+0x34>
|
||
|
|
{
|
||
|
|
pxList->pxIndex = pxItemToRemove->pxPrevious;
|
||
|
|
80032e0: 687b ldr r3, [r7, #4]
|
||
|
|
80032e2: 689a ldr r2, [r3, #8]
|
||
|
|
80032e4: 68fb ldr r3, [r7, #12]
|
||
|
|
80032e6: 605a str r2, [r3, #4]
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
pxItemToRemove->pxContainer = NULL;
|
||
|
|
80032e8: 687b ldr r3, [r7, #4]
|
||
|
|
80032ea: 2200 movs r2, #0
|
||
|
|
80032ec: 611a str r2, [r3, #16]
|
||
|
|
( pxList->uxNumberOfItems )--;
|
||
|
|
80032ee: 68fb ldr r3, [r7, #12]
|
||
|
|
80032f0: 681b ldr r3, [r3, #0]
|
||
|
|
80032f2: 1e5a subs r2, r3, #1
|
||
|
|
80032f4: 68fb ldr r3, [r7, #12]
|
||
|
|
80032f6: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
return pxList->uxNumberOfItems;
|
||
|
|
80032f8: 68fb ldr r3, [r7, #12]
|
||
|
|
80032fa: 681b ldr r3, [r3, #0]
|
||
|
|
}
|
||
|
|
80032fc: 4618 mov r0, r3
|
||
|
|
80032fe: 3714 adds r7, #20
|
||
|
|
8003300: 46bd mov sp, r7
|
||
|
|
8003302: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8003306: 4770 bx lr
|
||
|
|
|
||
|
|
08003308 <xQueueGenericReset>:
|
||
|
|
} \
|
||
|
|
taskEXIT_CRITICAL()
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
|
||
|
|
{
|
||
|
|
8003308: b580 push {r7, lr}
|
||
|
|
800330a: b084 sub sp, #16
|
||
|
|
800330c: af00 add r7, sp, #0
|
||
|
|
800330e: 6078 str r0, [r7, #4]
|
||
|
|
8003310: 6039 str r1, [r7, #0]
|
||
|
|
Queue_t * const pxQueue = xQueue;
|
||
|
|
8003312: 687b ldr r3, [r7, #4]
|
||
|
|
8003314: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
configASSERT( pxQueue );
|
||
|
|
8003316: 68fb ldr r3, [r7, #12]
|
||
|
|
8003318: 2b00 cmp r3, #0
|
||
|
|
800331a: d10a bne.n 8003332 <xQueueGenericReset+0x2a>
|
||
|
|
|
||
|
|
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
|
||
|
|
{
|
||
|
|
uint32_t ulNewBASEPRI;
|
||
|
|
|
||
|
|
__asm volatile
|
||
|
|
800331c: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003320: f383 8811 msr BASEPRI, r3
|
||
|
|
8003324: f3bf 8f6f isb sy
|
||
|
|
8003328: f3bf 8f4f dsb sy
|
||
|
|
800332c: 60bb str r3, [r7, #8]
|
||
|
|
" msr basepri, %0 \n" \
|
||
|
|
" isb \n" \
|
||
|
|
" dsb \n" \
|
||
|
|
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
||
|
|
);
|
||
|
|
}
|
||
|
|
800332e: bf00 nop
|
||
|
|
8003330: e7fe b.n 8003330 <xQueueGenericReset+0x28>
|
||
|
|
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
8003332: f002 f87f bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
||
|
|
8003336: 68fb ldr r3, [r7, #12]
|
||
|
|
8003338: 681a ldr r2, [r3, #0]
|
||
|
|
800333a: 68fb ldr r3, [r7, #12]
|
||
|
|
800333c: 6bdb ldr r3, [r3, #60] ; 0x3c
|
||
|
|
800333e: 68f9 ldr r1, [r7, #12]
|
||
|
|
8003340: 6c09 ldr r1, [r1, #64] ; 0x40
|
||
|
|
8003342: fb01 f303 mul.w r3, r1, r3
|
||
|
|
8003346: 441a add r2, r3
|
||
|
|
8003348: 68fb ldr r3, [r7, #12]
|
||
|
|
800334a: 609a str r2, [r3, #8]
|
||
|
|
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
|
||
|
|
800334c: 68fb ldr r3, [r7, #12]
|
||
|
|
800334e: 2200 movs r2, #0
|
||
|
|
8003350: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
||
|
|
8003352: 68fb ldr r3, [r7, #12]
|
||
|
|
8003354: 681a ldr r2, [r3, #0]
|
||
|
|
8003356: 68fb ldr r3, [r7, #12]
|
||
|
|
8003358: 605a str r2, [r3, #4]
|
||
|
|
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
||
|
|
800335a: 68fb ldr r3, [r7, #12]
|
||
|
|
800335c: 681a ldr r2, [r3, #0]
|
||
|
|
800335e: 68fb ldr r3, [r7, #12]
|
||
|
|
8003360: 6bdb ldr r3, [r3, #60] ; 0x3c
|
||
|
|
8003362: 3b01 subs r3, #1
|
||
|
|
8003364: 68f9 ldr r1, [r7, #12]
|
||
|
|
8003366: 6c09 ldr r1, [r1, #64] ; 0x40
|
||
|
|
8003368: fb01 f303 mul.w r3, r1, r3
|
||
|
|
800336c: 441a add r2, r3
|
||
|
|
800336e: 68fb ldr r3, [r7, #12]
|
||
|
|
8003370: 60da str r2, [r3, #12]
|
||
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
||
|
|
8003372: 68fb ldr r3, [r7, #12]
|
||
|
|
8003374: 22ff movs r2, #255 ; 0xff
|
||
|
|
8003376: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
||
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
||
|
|
800337a: 68fb ldr r3, [r7, #12]
|
||
|
|
800337c: 22ff movs r2, #255 ; 0xff
|
||
|
|
800337e: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
||
|
|
|
||
|
|
if( xNewQueue == pdFALSE )
|
||
|
|
8003382: 683b ldr r3, [r7, #0]
|
||
|
|
8003384: 2b00 cmp r3, #0
|
||
|
|
8003386: d114 bne.n 80033b2 <xQueueGenericReset+0xaa>
|
||
|
|
/* If there are tasks blocked waiting to read from the queue, then
|
||
|
|
the tasks will remain blocked as after this function exits the queue
|
||
|
|
will still be empty. If there are tasks blocked waiting to write to
|
||
|
|
the queue, then one should be unblocked as after this function exits
|
||
|
|
it will be possible to write to it. */
|
||
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
||
|
|
8003388: 68fb ldr r3, [r7, #12]
|
||
|
|
800338a: 691b ldr r3, [r3, #16]
|
||
|
|
800338c: 2b00 cmp r3, #0
|
||
|
|
800338e: d01a beq.n 80033c6 <xQueueGenericReset+0xbe>
|
||
|
|
{
|
||
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
||
|
|
8003390: 68fb ldr r3, [r7, #12]
|
||
|
|
8003392: 3310 adds r3, #16
|
||
|
|
8003394: 4618 mov r0, r3
|
||
|
|
8003396: f001 f931 bl 80045fc <xTaskRemoveFromEventList>
|
||
|
|
800339a: 4603 mov r3, r0
|
||
|
|
800339c: 2b00 cmp r3, #0
|
||
|
|
800339e: d012 beq.n 80033c6 <xQueueGenericReset+0xbe>
|
||
|
|
{
|
||
|
|
queueYIELD_IF_USING_PREEMPTION();
|
||
|
|
80033a0: 4b0c ldr r3, [pc, #48] ; (80033d4 <xQueueGenericReset+0xcc>)
|
||
|
|
80033a2: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
80033a6: 601a str r2, [r3, #0]
|
||
|
|
80033a8: f3bf 8f4f dsb sy
|
||
|
|
80033ac: f3bf 8f6f isb sy
|
||
|
|
80033b0: e009 b.n 80033c6 <xQueueGenericReset+0xbe>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Ensure the event queues start in the correct state. */
|
||
|
|
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
|
||
|
|
80033b2: 68fb ldr r3, [r7, #12]
|
||
|
|
80033b4: 3310 adds r3, #16
|
||
|
|
80033b6: 4618 mov r0, r3
|
||
|
|
80033b8: f7ff fef2 bl 80031a0 <vListInitialise>
|
||
|
|
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
|
||
|
|
80033bc: 68fb ldr r3, [r7, #12]
|
||
|
|
80033be: 3324 adds r3, #36 ; 0x24
|
||
|
|
80033c0: 4618 mov r0, r3
|
||
|
|
80033c2: f7ff feed bl 80031a0 <vListInitialise>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
80033c6: f002 f865 bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
/* A value is returned for calling semantic consistency with previous
|
||
|
|
versions. */
|
||
|
|
return pdPASS;
|
||
|
|
80033ca: 2301 movs r3, #1
|
||
|
|
}
|
||
|
|
80033cc: 4618 mov r0, r3
|
||
|
|
80033ce: 3710 adds r7, #16
|
||
|
|
80033d0: 46bd mov sp, r7
|
||
|
|
80033d2: bd80 pop {r7, pc}
|
||
|
|
80033d4: e000ed04 .word 0xe000ed04
|
||
|
|
|
||
|
|
080033d8 <xQueueGenericCreateStatic>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
||
|
|
|
||
|
|
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
|
||
|
|
{
|
||
|
|
80033d8: b580 push {r7, lr}
|
||
|
|
80033da: b08e sub sp, #56 ; 0x38
|
||
|
|
80033dc: af02 add r7, sp, #8
|
||
|
|
80033de: 60f8 str r0, [r7, #12]
|
||
|
|
80033e0: 60b9 str r1, [r7, #8]
|
||
|
|
80033e2: 607a str r2, [r7, #4]
|
||
|
|
80033e4: 603b str r3, [r7, #0]
|
||
|
|
Queue_t *pxNewQueue;
|
||
|
|
|
||
|
|
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
|
||
|
|
80033e6: 68fb ldr r3, [r7, #12]
|
||
|
|
80033e8: 2b00 cmp r3, #0
|
||
|
|
80033ea: d10a bne.n 8003402 <xQueueGenericCreateStatic+0x2a>
|
||
|
|
__asm volatile
|
||
|
|
80033ec: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80033f0: f383 8811 msr BASEPRI, r3
|
||
|
|
80033f4: f3bf 8f6f isb sy
|
||
|
|
80033f8: f3bf 8f4f dsb sy
|
||
|
|
80033fc: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
}
|
||
|
|
80033fe: bf00 nop
|
||
|
|
8003400: e7fe b.n 8003400 <xQueueGenericCreateStatic+0x28>
|
||
|
|
|
||
|
|
/* The StaticQueue_t structure and the queue storage area must be
|
||
|
|
supplied. */
|
||
|
|
configASSERT( pxStaticQueue != NULL );
|
||
|
|
8003402: 683b ldr r3, [r7, #0]
|
||
|
|
8003404: 2b00 cmp r3, #0
|
||
|
|
8003406: d10a bne.n 800341e <xQueueGenericCreateStatic+0x46>
|
||
|
|
__asm volatile
|
||
|
|
8003408: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
800340c: f383 8811 msr BASEPRI, r3
|
||
|
|
8003410: f3bf 8f6f isb sy
|
||
|
|
8003414: f3bf 8f4f dsb sy
|
||
|
|
8003418: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
}
|
||
|
|
800341a: bf00 nop
|
||
|
|
800341c: e7fe b.n 800341c <xQueueGenericCreateStatic+0x44>
|
||
|
|
|
||
|
|
/* A queue storage area should be provided if the item size is not 0, and
|
||
|
|
should not be provided if the item size is 0. */
|
||
|
|
configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
|
||
|
|
800341e: 687b ldr r3, [r7, #4]
|
||
|
|
8003420: 2b00 cmp r3, #0
|
||
|
|
8003422: d002 beq.n 800342a <xQueueGenericCreateStatic+0x52>
|
||
|
|
8003424: 68bb ldr r3, [r7, #8]
|
||
|
|
8003426: 2b00 cmp r3, #0
|
||
|
|
8003428: d001 beq.n 800342e <xQueueGenericCreateStatic+0x56>
|
||
|
|
800342a: 2301 movs r3, #1
|
||
|
|
800342c: e000 b.n 8003430 <xQueueGenericCreateStatic+0x58>
|
||
|
|
800342e: 2300 movs r3, #0
|
||
|
|
8003430: 2b00 cmp r3, #0
|
||
|
|
8003432: d10a bne.n 800344a <xQueueGenericCreateStatic+0x72>
|
||
|
|
__asm volatile
|
||
|
|
8003434: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003438: f383 8811 msr BASEPRI, r3
|
||
|
|
800343c: f3bf 8f6f isb sy
|
||
|
|
8003440: f3bf 8f4f dsb sy
|
||
|
|
8003444: 623b str r3, [r7, #32]
|
||
|
|
}
|
||
|
|
8003446: bf00 nop
|
||
|
|
8003448: e7fe b.n 8003448 <xQueueGenericCreateStatic+0x70>
|
||
|
|
configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
|
||
|
|
800344a: 687b ldr r3, [r7, #4]
|
||
|
|
800344c: 2b00 cmp r3, #0
|
||
|
|
800344e: d102 bne.n 8003456 <xQueueGenericCreateStatic+0x7e>
|
||
|
|
8003450: 68bb ldr r3, [r7, #8]
|
||
|
|
8003452: 2b00 cmp r3, #0
|
||
|
|
8003454: d101 bne.n 800345a <xQueueGenericCreateStatic+0x82>
|
||
|
|
8003456: 2301 movs r3, #1
|
||
|
|
8003458: e000 b.n 800345c <xQueueGenericCreateStatic+0x84>
|
||
|
|
800345a: 2300 movs r3, #0
|
||
|
|
800345c: 2b00 cmp r3, #0
|
||
|
|
800345e: d10a bne.n 8003476 <xQueueGenericCreateStatic+0x9e>
|
||
|
|
__asm volatile
|
||
|
|
8003460: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003464: f383 8811 msr BASEPRI, r3
|
||
|
|
8003468: f3bf 8f6f isb sy
|
||
|
|
800346c: f3bf 8f4f dsb sy
|
||
|
|
8003470: 61fb str r3, [r7, #28]
|
||
|
|
}
|
||
|
|
8003472: bf00 nop
|
||
|
|
8003474: e7fe b.n 8003474 <xQueueGenericCreateStatic+0x9c>
|
||
|
|
#if( configASSERT_DEFINED == 1 )
|
||
|
|
{
|
||
|
|
/* Sanity check that the size of the structure used to declare a
|
||
|
|
variable of type StaticQueue_t or StaticSemaphore_t equals the size of
|
||
|
|
the real queue and semaphore structures. */
|
||
|
|
volatile size_t xSize = sizeof( StaticQueue_t );
|
||
|
|
8003476: 2350 movs r3, #80 ; 0x50
|
||
|
|
8003478: 617b str r3, [r7, #20]
|
||
|
|
configASSERT( xSize == sizeof( Queue_t ) );
|
||
|
|
800347a: 697b ldr r3, [r7, #20]
|
||
|
|
800347c: 2b50 cmp r3, #80 ; 0x50
|
||
|
|
800347e: d00a beq.n 8003496 <xQueueGenericCreateStatic+0xbe>
|
||
|
|
__asm volatile
|
||
|
|
8003480: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003484: f383 8811 msr BASEPRI, r3
|
||
|
|
8003488: f3bf 8f6f isb sy
|
||
|
|
800348c: f3bf 8f4f dsb sy
|
||
|
|
8003490: 61bb str r3, [r7, #24]
|
||
|
|
}
|
||
|
|
8003492: bf00 nop
|
||
|
|
8003494: e7fe b.n 8003494 <xQueueGenericCreateStatic+0xbc>
|
||
|
|
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
|
||
|
|
8003496: 697b ldr r3, [r7, #20]
|
||
|
|
#endif /* configASSERT_DEFINED */
|
||
|
|
|
||
|
|
/* The address of a statically allocated queue was passed in, use it.
|
||
|
|
The address of a statically allocated storage area was also passed in
|
||
|
|
but is already set. */
|
||
|
|
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
|
||
|
|
8003498: 683b ldr r3, [r7, #0]
|
||
|
|
800349a: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
|
||
|
|
if( pxNewQueue != NULL )
|
||
|
|
800349c: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
800349e: 2b00 cmp r3, #0
|
||
|
|
80034a0: d00d beq.n 80034be <xQueueGenericCreateStatic+0xe6>
|
||
|
|
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
||
|
|
{
|
||
|
|
/* Queues can be allocated wither statically or dynamically, so
|
||
|
|
note this queue was allocated statically in case the queue is
|
||
|
|
later deleted. */
|
||
|
|
pxNewQueue->ucStaticallyAllocated = pdTRUE;
|
||
|
|
80034a2: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
80034a4: 2201 movs r2, #1
|
||
|
|
80034a6: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
||
|
|
}
|
||
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
||
|
|
|
||
|
|
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
|
||
|
|
80034aa: f897 2038 ldrb.w r2, [r7, #56] ; 0x38
|
||
|
|
80034ae: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
80034b0: 9300 str r3, [sp, #0]
|
||
|
|
80034b2: 4613 mov r3, r2
|
||
|
|
80034b4: 687a ldr r2, [r7, #4]
|
||
|
|
80034b6: 68b9 ldr r1, [r7, #8]
|
||
|
|
80034b8: 68f8 ldr r0, [r7, #12]
|
||
|
|
80034ba: f000 f805 bl 80034c8 <prvInitialiseNewQueue>
|
||
|
|
{
|
||
|
|
traceQUEUE_CREATE_FAILED( ucQueueType );
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
return pxNewQueue;
|
||
|
|
80034be: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
}
|
||
|
|
80034c0: 4618 mov r0, r3
|
||
|
|
80034c2: 3730 adds r7, #48 ; 0x30
|
||
|
|
80034c4: 46bd mov sp, r7
|
||
|
|
80034c6: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
080034c8 <prvInitialiseNewQueue>:
|
||
|
|
|
||
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
|
||
|
|
{
|
||
|
|
80034c8: b580 push {r7, lr}
|
||
|
|
80034ca: b084 sub sp, #16
|
||
|
|
80034cc: af00 add r7, sp, #0
|
||
|
|
80034ce: 60f8 str r0, [r7, #12]
|
||
|
|
80034d0: 60b9 str r1, [r7, #8]
|
||
|
|
80034d2: 607a str r2, [r7, #4]
|
||
|
|
80034d4: 70fb strb r3, [r7, #3]
|
||
|
|
/* Remove compiler warnings about unused parameters should
|
||
|
|
configUSE_TRACE_FACILITY not be set to 1. */
|
||
|
|
( void ) ucQueueType;
|
||
|
|
|
||
|
|
if( uxItemSize == ( UBaseType_t ) 0 )
|
||
|
|
80034d6: 68bb ldr r3, [r7, #8]
|
||
|
|
80034d8: 2b00 cmp r3, #0
|
||
|
|
80034da: d103 bne.n 80034e4 <prvInitialiseNewQueue+0x1c>
|
||
|
|
{
|
||
|
|
/* No RAM was allocated for the queue storage area, but PC head cannot
|
||
|
|
be set to NULL because NULL is used as a key to say the queue is used as
|
||
|
|
a mutex. Therefore just set pcHead to point to the queue as a benign
|
||
|
|
value that is known to be within the memory map. */
|
||
|
|
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
|
||
|
|
80034dc: 69bb ldr r3, [r7, #24]
|
||
|
|
80034de: 69ba ldr r2, [r7, #24]
|
||
|
|
80034e0: 601a str r2, [r3, #0]
|
||
|
|
80034e2: e002 b.n 80034ea <prvInitialiseNewQueue+0x22>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Set the head to the start of the queue storage area. */
|
||
|
|
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
|
||
|
|
80034e4: 69bb ldr r3, [r7, #24]
|
||
|
|
80034e6: 687a ldr r2, [r7, #4]
|
||
|
|
80034e8: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Initialise the queue members as described where the queue type is
|
||
|
|
defined. */
|
||
|
|
pxNewQueue->uxLength = uxQueueLength;
|
||
|
|
80034ea: 69bb ldr r3, [r7, #24]
|
||
|
|
80034ec: 68fa ldr r2, [r7, #12]
|
||
|
|
80034ee: 63da str r2, [r3, #60] ; 0x3c
|
||
|
|
pxNewQueue->uxItemSize = uxItemSize;
|
||
|
|
80034f0: 69bb ldr r3, [r7, #24]
|
||
|
|
80034f2: 68ba ldr r2, [r7, #8]
|
||
|
|
80034f4: 641a str r2, [r3, #64] ; 0x40
|
||
|
|
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
|
||
|
|
80034f6: 2101 movs r1, #1
|
||
|
|
80034f8: 69b8 ldr r0, [r7, #24]
|
||
|
|
80034fa: f7ff ff05 bl 8003308 <xQueueGenericReset>
|
||
|
|
|
||
|
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
||
|
|
{
|
||
|
|
pxNewQueue->ucQueueType = ucQueueType;
|
||
|
|
80034fe: 69bb ldr r3, [r7, #24]
|
||
|
|
8003500: 78fa ldrb r2, [r7, #3]
|
||
|
|
8003502: f883 204c strb.w r2, [r3, #76] ; 0x4c
|
||
|
|
pxNewQueue->pxQueueSetContainer = NULL;
|
||
|
|
}
|
||
|
|
#endif /* configUSE_QUEUE_SETS */
|
||
|
|
|
||
|
|
traceQUEUE_CREATE( pxNewQueue );
|
||
|
|
}
|
||
|
|
8003506: bf00 nop
|
||
|
|
8003508: 3710 adds r7, #16
|
||
|
|
800350a: 46bd mov sp, r7
|
||
|
|
800350c: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
08003510 <xQueueGenericSend>:
|
||
|
|
|
||
|
|
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
|
||
|
|
{
|
||
|
|
8003510: b580 push {r7, lr}
|
||
|
|
8003512: b08e sub sp, #56 ; 0x38
|
||
|
|
8003514: af00 add r7, sp, #0
|
||
|
|
8003516: 60f8 str r0, [r7, #12]
|
||
|
|
8003518: 60b9 str r1, [r7, #8]
|
||
|
|
800351a: 607a str r2, [r7, #4]
|
||
|
|
800351c: 603b str r3, [r7, #0]
|
||
|
|
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
|
||
|
|
800351e: 2300 movs r3, #0
|
||
|
|
8003520: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
TimeOut_t xTimeOut;
|
||
|
|
Queue_t * const pxQueue = xQueue;
|
||
|
|
8003522: 68fb ldr r3, [r7, #12]
|
||
|
|
8003524: 633b str r3, [r7, #48] ; 0x30
|
||
|
|
|
||
|
|
configASSERT( pxQueue );
|
||
|
|
8003526: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003528: 2b00 cmp r3, #0
|
||
|
|
800352a: d10a bne.n 8003542 <xQueueGenericSend+0x32>
|
||
|
|
__asm volatile
|
||
|
|
800352c: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003530: f383 8811 msr BASEPRI, r3
|
||
|
|
8003534: f3bf 8f6f isb sy
|
||
|
|
8003538: f3bf 8f4f dsb sy
|
||
|
|
800353c: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
}
|
||
|
|
800353e: bf00 nop
|
||
|
|
8003540: e7fe b.n 8003540 <xQueueGenericSend+0x30>
|
||
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
||
|
|
8003542: 68bb ldr r3, [r7, #8]
|
||
|
|
8003544: 2b00 cmp r3, #0
|
||
|
|
8003546: d103 bne.n 8003550 <xQueueGenericSend+0x40>
|
||
|
|
8003548: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
800354a: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
800354c: 2b00 cmp r3, #0
|
||
|
|
800354e: d101 bne.n 8003554 <xQueueGenericSend+0x44>
|
||
|
|
8003550: 2301 movs r3, #1
|
||
|
|
8003552: e000 b.n 8003556 <xQueueGenericSend+0x46>
|
||
|
|
8003554: 2300 movs r3, #0
|
||
|
|
8003556: 2b00 cmp r3, #0
|
||
|
|
8003558: d10a bne.n 8003570 <xQueueGenericSend+0x60>
|
||
|
|
__asm volatile
|
||
|
|
800355a: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
800355e: f383 8811 msr BASEPRI, r3
|
||
|
|
8003562: f3bf 8f6f isb sy
|
||
|
|
8003566: f3bf 8f4f dsb sy
|
||
|
|
800356a: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
}
|
||
|
|
800356c: bf00 nop
|
||
|
|
800356e: e7fe b.n 800356e <xQueueGenericSend+0x5e>
|
||
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
||
|
|
8003570: 683b ldr r3, [r7, #0]
|
||
|
|
8003572: 2b02 cmp r3, #2
|
||
|
|
8003574: d103 bne.n 800357e <xQueueGenericSend+0x6e>
|
||
|
|
8003576: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003578: 6bdb ldr r3, [r3, #60] ; 0x3c
|
||
|
|
800357a: 2b01 cmp r3, #1
|
||
|
|
800357c: d101 bne.n 8003582 <xQueueGenericSend+0x72>
|
||
|
|
800357e: 2301 movs r3, #1
|
||
|
|
8003580: e000 b.n 8003584 <xQueueGenericSend+0x74>
|
||
|
|
8003582: 2300 movs r3, #0
|
||
|
|
8003584: 2b00 cmp r3, #0
|
||
|
|
8003586: d10a bne.n 800359e <xQueueGenericSend+0x8e>
|
||
|
|
__asm volatile
|
||
|
|
8003588: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
800358c: f383 8811 msr BASEPRI, r3
|
||
|
|
8003590: f3bf 8f6f isb sy
|
||
|
|
8003594: f3bf 8f4f dsb sy
|
||
|
|
8003598: 623b str r3, [r7, #32]
|
||
|
|
}
|
||
|
|
800359a: bf00 nop
|
||
|
|
800359c: e7fe b.n 800359c <xQueueGenericSend+0x8c>
|
||
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||
|
|
{
|
||
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
||
|
|
800359e: f001 f9f1 bl 8004984 <xTaskGetSchedulerState>
|
||
|
|
80035a2: 4603 mov r3, r0
|
||
|
|
80035a4: 2b00 cmp r3, #0
|
||
|
|
80035a6: d102 bne.n 80035ae <xQueueGenericSend+0x9e>
|
||
|
|
80035a8: 687b ldr r3, [r7, #4]
|
||
|
|
80035aa: 2b00 cmp r3, #0
|
||
|
|
80035ac: d101 bne.n 80035b2 <xQueueGenericSend+0xa2>
|
||
|
|
80035ae: 2301 movs r3, #1
|
||
|
|
80035b0: e000 b.n 80035b4 <xQueueGenericSend+0xa4>
|
||
|
|
80035b2: 2300 movs r3, #0
|
||
|
|
80035b4: 2b00 cmp r3, #0
|
||
|
|
80035b6: d10a bne.n 80035ce <xQueueGenericSend+0xbe>
|
||
|
|
__asm volatile
|
||
|
|
80035b8: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80035bc: f383 8811 msr BASEPRI, r3
|
||
|
|
80035c0: f3bf 8f6f isb sy
|
||
|
|
80035c4: f3bf 8f4f dsb sy
|
||
|
|
80035c8: 61fb str r3, [r7, #28]
|
||
|
|
}
|
||
|
|
80035ca: bf00 nop
|
||
|
|
80035cc: e7fe b.n 80035cc <xQueueGenericSend+0xbc>
|
||
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
||
|
|
allow return statements within the function itself. This is done in the
|
||
|
|
interest of execution time efficiency. */
|
||
|
|
for( ;; )
|
||
|
|
{
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
80035ce: f001 ff31 bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
/* Is there room on the queue now? The running task must be the
|
||
|
|
highest priority task wanting to access the queue. If the head item
|
||
|
|
in the queue is to be overwritten then it does not matter if the
|
||
|
|
queue is full. */
|
||
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
||
|
|
80035d2: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
80035d4: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
80035d6: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
80035d8: 6bdb ldr r3, [r3, #60] ; 0x3c
|
||
|
|
80035da: 429a cmp r2, r3
|
||
|
|
80035dc: d302 bcc.n 80035e4 <xQueueGenericSend+0xd4>
|
||
|
|
80035de: 683b ldr r3, [r7, #0]
|
||
|
|
80035e0: 2b02 cmp r3, #2
|
||
|
|
80035e2: d129 bne.n 8003638 <xQueueGenericSend+0x128>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#else /* configUSE_QUEUE_SETS */
|
||
|
|
{
|
||
|
|
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
||
|
|
80035e4: 683a ldr r2, [r7, #0]
|
||
|
|
80035e6: 68b9 ldr r1, [r7, #8]
|
||
|
|
80035e8: 6b38 ldr r0, [r7, #48] ; 0x30
|
||
|
|
80035ea: f000 fa0b bl 8003a04 <prvCopyDataToQueue>
|
||
|
|
80035ee: 62f8 str r0, [r7, #44] ; 0x2c
|
||
|
|
|
||
|
|
/* If there was a task waiting for data to arrive on the
|
||
|
|
queue then unblock it now. */
|
||
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
||
|
|
80035f0: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
80035f2: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
80035f4: 2b00 cmp r3, #0
|
||
|
|
80035f6: d010 beq.n 800361a <xQueueGenericSend+0x10a>
|
||
|
|
{
|
||
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
||
|
|
80035f8: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
80035fa: 3324 adds r3, #36 ; 0x24
|
||
|
|
80035fc: 4618 mov r0, r3
|
||
|
|
80035fe: f000 fffd bl 80045fc <xTaskRemoveFromEventList>
|
||
|
|
8003602: 4603 mov r3, r0
|
||
|
|
8003604: 2b00 cmp r3, #0
|
||
|
|
8003606: d013 beq.n 8003630 <xQueueGenericSend+0x120>
|
||
|
|
{
|
||
|
|
/* The unblocked task has a priority higher than
|
||
|
|
our own so yield immediately. Yes it is ok to do
|
||
|
|
this from within the critical section - the kernel
|
||
|
|
takes care of that. */
|
||
|
|
queueYIELD_IF_USING_PREEMPTION();
|
||
|
|
8003608: 4b3f ldr r3, [pc, #252] ; (8003708 <xQueueGenericSend+0x1f8>)
|
||
|
|
800360a: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
800360e: 601a str r2, [r3, #0]
|
||
|
|
8003610: f3bf 8f4f dsb sy
|
||
|
|
8003614: f3bf 8f6f isb sy
|
||
|
|
8003618: e00a b.n 8003630 <xQueueGenericSend+0x120>
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if( xYieldRequired != pdFALSE )
|
||
|
|
800361a: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
800361c: 2b00 cmp r3, #0
|
||
|
|
800361e: d007 beq.n 8003630 <xQueueGenericSend+0x120>
|
||
|
|
{
|
||
|
|
/* This path is a special case that will only get
|
||
|
|
executed if the task was holding multiple mutexes and
|
||
|
|
the mutexes were given back in an order that is
|
||
|
|
different to that in which they were taken. */
|
||
|
|
queueYIELD_IF_USING_PREEMPTION();
|
||
|
|
8003620: 4b39 ldr r3, [pc, #228] ; (8003708 <xQueueGenericSend+0x1f8>)
|
||
|
|
8003622: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
8003626: 601a str r2, [r3, #0]
|
||
|
|
8003628: f3bf 8f4f dsb sy
|
||
|
|
800362c: f3bf 8f6f isb sy
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* configUSE_QUEUE_SETS */
|
||
|
|
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
8003630: f001 ff30 bl 8005494 <vPortExitCritical>
|
||
|
|
return pdPASS;
|
||
|
|
8003634: 2301 movs r3, #1
|
||
|
|
8003636: e063 b.n 8003700 <xQueueGenericSend+0x1f0>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
||
|
|
8003638: 687b ldr r3, [r7, #4]
|
||
|
|
800363a: 2b00 cmp r3, #0
|
||
|
|
800363c: d103 bne.n 8003646 <xQueueGenericSend+0x136>
|
||
|
|
{
|
||
|
|
/* The queue was full and no block time is specified (or
|
||
|
|
the block time has expired) so leave now. */
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
800363e: f001 ff29 bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
/* Return to the original privilege level before exiting
|
||
|
|
the function. */
|
||
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
||
|
|
return errQUEUE_FULL;
|
||
|
|
8003642: 2300 movs r3, #0
|
||
|
|
8003644: e05c b.n 8003700 <xQueueGenericSend+0x1f0>
|
||
|
|
}
|
||
|
|
else if( xEntryTimeSet == pdFALSE )
|
||
|
|
8003646: 6b7b ldr r3, [r7, #52] ; 0x34
|
||
|
|
8003648: 2b00 cmp r3, #0
|
||
|
|
800364a: d106 bne.n 800365a <xQueueGenericSend+0x14a>
|
||
|
|
{
|
||
|
|
/* The queue was full and a block time was specified so
|
||
|
|
configure the timeout structure. */
|
||
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
||
|
|
800364c: f107 0314 add.w r3, r7, #20
|
||
|
|
8003650: 4618 mov r0, r3
|
||
|
|
8003652: f001 f837 bl 80046c4 <vTaskInternalSetTimeOutState>
|
||
|
|
xEntryTimeSet = pdTRUE;
|
||
|
|
8003656: 2301 movs r3, #1
|
||
|
|
8003658: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
/* Entry time was already set. */
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
800365a: f001 ff1b bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
||
|
|
now the critical section has been exited. */
|
||
|
|
|
||
|
|
vTaskSuspendAll();
|
||
|
|
800365e: f000 fd9b bl 8004198 <vTaskSuspendAll>
|
||
|
|
prvLockQueue( pxQueue );
|
||
|
|
8003662: f001 fee7 bl 8005434 <vPortEnterCritical>
|
||
|
|
8003666: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003668: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
||
|
|
800366c: b25b sxtb r3, r3
|
||
|
|
800366e: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
8003672: d103 bne.n 800367c <xQueueGenericSend+0x16c>
|
||
|
|
8003674: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003676: 2200 movs r2, #0
|
||
|
|
8003678: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
||
|
|
800367c: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
800367e: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
||
|
|
8003682: b25b sxtb r3, r3
|
||
|
|
8003684: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
8003688: d103 bne.n 8003692 <xQueueGenericSend+0x182>
|
||
|
|
800368a: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
800368c: 2200 movs r2, #0
|
||
|
|
800368e: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
||
|
|
8003692: f001 feff bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
/* Update the timeout state to see if it has expired yet. */
|
||
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
||
|
|
8003696: 1d3a adds r2, r7, #4
|
||
|
|
8003698: f107 0314 add.w r3, r7, #20
|
||
|
|
800369c: 4611 mov r1, r2
|
||
|
|
800369e: 4618 mov r0, r3
|
||
|
|
80036a0: f001 f826 bl 80046f0 <xTaskCheckForTimeOut>
|
||
|
|
80036a4: 4603 mov r3, r0
|
||
|
|
80036a6: 2b00 cmp r3, #0
|
||
|
|
80036a8: d124 bne.n 80036f4 <xQueueGenericSend+0x1e4>
|
||
|
|
{
|
||
|
|
if( prvIsQueueFull( pxQueue ) != pdFALSE )
|
||
|
|
80036aa: 6b38 ldr r0, [r7, #48] ; 0x30
|
||
|
|
80036ac: f000 faa2 bl 8003bf4 <prvIsQueueFull>
|
||
|
|
80036b0: 4603 mov r3, r0
|
||
|
|
80036b2: 2b00 cmp r3, #0
|
||
|
|
80036b4: d018 beq.n 80036e8 <xQueueGenericSend+0x1d8>
|
||
|
|
{
|
||
|
|
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
|
||
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
|
||
|
|
80036b6: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
80036b8: 3310 adds r3, #16
|
||
|
|
80036ba: 687a ldr r2, [r7, #4]
|
||
|
|
80036bc: 4611 mov r1, r2
|
||
|
|
80036be: 4618 mov r0, r3
|
||
|
|
80036c0: f000 ff4c bl 800455c <vTaskPlaceOnEventList>
|
||
|
|
/* Unlocking the queue means queue events can effect the
|
||
|
|
event list. It is possible that interrupts occurring now
|
||
|
|
remove this task from the event list again - but as the
|
||
|
|
scheduler is suspended the task will go onto the pending
|
||
|
|
ready last instead of the actual ready list. */
|
||
|
|
prvUnlockQueue( pxQueue );
|
||
|
|
80036c4: 6b38 ldr r0, [r7, #48] ; 0x30
|
||
|
|
80036c6: f000 fa2d bl 8003b24 <prvUnlockQueue>
|
||
|
|
/* Resuming the scheduler will move tasks from the pending
|
||
|
|
ready list into the ready list - so it is feasible that this
|
||
|
|
task is already in a ready list before it yields - in which
|
||
|
|
case the yield will not cause a context switch unless there
|
||
|
|
is also a higher priority task in the pending ready list. */
|
||
|
|
if( xTaskResumeAll() == pdFALSE )
|
||
|
|
80036ca: f000 fd73 bl 80041b4 <xTaskResumeAll>
|
||
|
|
80036ce: 4603 mov r3, r0
|
||
|
|
80036d0: 2b00 cmp r3, #0
|
||
|
|
80036d2: f47f af7c bne.w 80035ce <xQueueGenericSend+0xbe>
|
||
|
|
{
|
||
|
|
portYIELD_WITHIN_API();
|
||
|
|
80036d6: 4b0c ldr r3, [pc, #48] ; (8003708 <xQueueGenericSend+0x1f8>)
|
||
|
|
80036d8: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
80036dc: 601a str r2, [r3, #0]
|
||
|
|
80036de: f3bf 8f4f dsb sy
|
||
|
|
80036e2: f3bf 8f6f isb sy
|
||
|
|
80036e6: e772 b.n 80035ce <xQueueGenericSend+0xbe>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Try again. */
|
||
|
|
prvUnlockQueue( pxQueue );
|
||
|
|
80036e8: 6b38 ldr r0, [r7, #48] ; 0x30
|
||
|
|
80036ea: f000 fa1b bl 8003b24 <prvUnlockQueue>
|
||
|
|
( void ) xTaskResumeAll();
|
||
|
|
80036ee: f000 fd61 bl 80041b4 <xTaskResumeAll>
|
||
|
|
80036f2: e76c b.n 80035ce <xQueueGenericSend+0xbe>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* The timeout has expired. */
|
||
|
|
prvUnlockQueue( pxQueue );
|
||
|
|
80036f4: 6b38 ldr r0, [r7, #48] ; 0x30
|
||
|
|
80036f6: f000 fa15 bl 8003b24 <prvUnlockQueue>
|
||
|
|
( void ) xTaskResumeAll();
|
||
|
|
80036fa: f000 fd5b bl 80041b4 <xTaskResumeAll>
|
||
|
|
|
||
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
||
|
|
return errQUEUE_FULL;
|
||
|
|
80036fe: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
} /*lint -restore */
|
||
|
|
}
|
||
|
|
8003700: 4618 mov r0, r3
|
||
|
|
8003702: 3738 adds r7, #56 ; 0x38
|
||
|
|
8003704: 46bd mov sp, r7
|
||
|
|
8003706: bd80 pop {r7, pc}
|
||
|
|
8003708: e000ed04 .word 0xe000ed04
|
||
|
|
|
||
|
|
0800370c <xQueueGenericSendFromISR>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
|
||
|
|
{
|
||
|
|
800370c: b580 push {r7, lr}
|
||
|
|
800370e: b090 sub sp, #64 ; 0x40
|
||
|
|
8003710: af00 add r7, sp, #0
|
||
|
|
8003712: 60f8 str r0, [r7, #12]
|
||
|
|
8003714: 60b9 str r1, [r7, #8]
|
||
|
|
8003716: 607a str r2, [r7, #4]
|
||
|
|
8003718: 603b str r3, [r7, #0]
|
||
|
|
BaseType_t xReturn;
|
||
|
|
UBaseType_t uxSavedInterruptStatus;
|
||
|
|
Queue_t * const pxQueue = xQueue;
|
||
|
|
800371a: 68fb ldr r3, [r7, #12]
|
||
|
|
800371c: 63bb str r3, [r7, #56] ; 0x38
|
||
|
|
|
||
|
|
configASSERT( pxQueue );
|
||
|
|
800371e: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
8003720: 2b00 cmp r3, #0
|
||
|
|
8003722: d10a bne.n 800373a <xQueueGenericSendFromISR+0x2e>
|
||
|
|
__asm volatile
|
||
|
|
8003724: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003728: f383 8811 msr BASEPRI, r3
|
||
|
|
800372c: f3bf 8f6f isb sy
|
||
|
|
8003730: f3bf 8f4f dsb sy
|
||
|
|
8003734: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
}
|
||
|
|
8003736: bf00 nop
|
||
|
|
8003738: e7fe b.n 8003738 <xQueueGenericSendFromISR+0x2c>
|
||
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
||
|
|
800373a: 68bb ldr r3, [r7, #8]
|
||
|
|
800373c: 2b00 cmp r3, #0
|
||
|
|
800373e: d103 bne.n 8003748 <xQueueGenericSendFromISR+0x3c>
|
||
|
|
8003740: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
8003742: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8003744: 2b00 cmp r3, #0
|
||
|
|
8003746: d101 bne.n 800374c <xQueueGenericSendFromISR+0x40>
|
||
|
|
8003748: 2301 movs r3, #1
|
||
|
|
800374a: e000 b.n 800374e <xQueueGenericSendFromISR+0x42>
|
||
|
|
800374c: 2300 movs r3, #0
|
||
|
|
800374e: 2b00 cmp r3, #0
|
||
|
|
8003750: d10a bne.n 8003768 <xQueueGenericSendFromISR+0x5c>
|
||
|
|
__asm volatile
|
||
|
|
8003752: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003756: f383 8811 msr BASEPRI, r3
|
||
|
|
800375a: f3bf 8f6f isb sy
|
||
|
|
800375e: f3bf 8f4f dsb sy
|
||
|
|
8003762: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
}
|
||
|
|
8003764: bf00 nop
|
||
|
|
8003766: e7fe b.n 8003766 <xQueueGenericSendFromISR+0x5a>
|
||
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
||
|
|
8003768: 683b ldr r3, [r7, #0]
|
||
|
|
800376a: 2b02 cmp r3, #2
|
||
|
|
800376c: d103 bne.n 8003776 <xQueueGenericSendFromISR+0x6a>
|
||
|
|
800376e: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
8003770: 6bdb ldr r3, [r3, #60] ; 0x3c
|
||
|
|
8003772: 2b01 cmp r3, #1
|
||
|
|
8003774: d101 bne.n 800377a <xQueueGenericSendFromISR+0x6e>
|
||
|
|
8003776: 2301 movs r3, #1
|
||
|
|
8003778: e000 b.n 800377c <xQueueGenericSendFromISR+0x70>
|
||
|
|
800377a: 2300 movs r3, #0
|
||
|
|
800377c: 2b00 cmp r3, #0
|
||
|
|
800377e: d10a bne.n 8003796 <xQueueGenericSendFromISR+0x8a>
|
||
|
|
__asm volatile
|
||
|
|
8003780: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003784: f383 8811 msr BASEPRI, r3
|
||
|
|
8003788: f3bf 8f6f isb sy
|
||
|
|
800378c: f3bf 8f4f dsb sy
|
||
|
|
8003790: 623b str r3, [r7, #32]
|
||
|
|
}
|
||
|
|
8003792: bf00 nop
|
||
|
|
8003794: e7fe b.n 8003794 <xQueueGenericSendFromISR+0x88>
|
||
|
|
that have been assigned a priority at or (logically) below the maximum
|
||
|
|
system call interrupt priority. FreeRTOS maintains a separate interrupt
|
||
|
|
safe API to ensure interrupt entry is as fast and as simple as possible.
|
||
|
|
More information (albeit Cortex-M specific) is provided on the following
|
||
|
|
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
|
||
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
||
|
|
8003796: f001 ff2f bl 80055f8 <vPortValidateInterruptPriority>
|
||
|
|
|
||
|
|
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
|
||
|
|
{
|
||
|
|
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
|
||
|
|
|
||
|
|
__asm volatile
|
||
|
|
800379a: f3ef 8211 mrs r2, BASEPRI
|
||
|
|
800379e: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80037a2: f383 8811 msr BASEPRI, r3
|
||
|
|
80037a6: f3bf 8f6f isb sy
|
||
|
|
80037aa: f3bf 8f4f dsb sy
|
||
|
|
80037ae: 61fa str r2, [r7, #28]
|
||
|
|
80037b0: 61bb str r3, [r7, #24]
|
||
|
|
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
||
|
|
);
|
||
|
|
|
||
|
|
/* This return will not be reached but is necessary to prevent compiler
|
||
|
|
warnings. */
|
||
|
|
return ulOriginalBASEPRI;
|
||
|
|
80037b2: 69fb ldr r3, [r7, #28]
|
||
|
|
/* Similar to xQueueGenericSend, except without blocking if there is no room
|
||
|
|
in the queue. Also don't directly wake a task that was blocked on a queue
|
||
|
|
read, instead return a flag to say whether a context switch is required or
|
||
|
|
not (i.e. has a task with a higher priority than us been woken by this
|
||
|
|
post). */
|
||
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
||
|
|
80037b4: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
{
|
||
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
||
|
|
80037b6: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
80037b8: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
80037ba: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
80037bc: 6bdb ldr r3, [r3, #60] ; 0x3c
|
||
|
|
80037be: 429a cmp r2, r3
|
||
|
|
80037c0: d302 bcc.n 80037c8 <xQueueGenericSendFromISR+0xbc>
|
||
|
|
80037c2: 683b ldr r3, [r7, #0]
|
||
|
|
80037c4: 2b02 cmp r3, #2
|
||
|
|
80037c6: d12f bne.n 8003828 <xQueueGenericSendFromISR+0x11c>
|
||
|
|
{
|
||
|
|
const int8_t cTxLock = pxQueue->cTxLock;
|
||
|
|
80037c8: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
80037ca: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
||
|
|
80037ce: f887 3033 strb.w r3, [r7, #51] ; 0x33
|
||
|
|
const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
|
||
|
|
80037d2: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
80037d4: 6b9b ldr r3, [r3, #56] ; 0x38
|
||
|
|
80037d6: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
|
||
|
|
semaphore or mutex. That means prvCopyDataToQueue() cannot result
|
||
|
|
in a task disinheriting a priority and prvCopyDataToQueue() can be
|
||
|
|
called here even though the disinherit function does not check if
|
||
|
|
the scheduler is suspended before accessing the ready lists. */
|
||
|
|
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
||
|
|
80037d8: 683a ldr r2, [r7, #0]
|
||
|
|
80037da: 68b9 ldr r1, [r7, #8]
|
||
|
|
80037dc: 6bb8 ldr r0, [r7, #56] ; 0x38
|
||
|
|
80037de: f000 f911 bl 8003a04 <prvCopyDataToQueue>
|
||
|
|
|
||
|
|
/* The event list is not altered if the queue is locked. This will
|
||
|
|
be done when the queue is unlocked later. */
|
||
|
|
if( cTxLock == queueUNLOCKED )
|
||
|
|
80037e2: f997 3033 ldrsb.w r3, [r7, #51] ; 0x33
|
||
|
|
80037e6: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
80037ea: d112 bne.n 8003812 <xQueueGenericSendFromISR+0x106>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#else /* configUSE_QUEUE_SETS */
|
||
|
|
{
|
||
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
||
|
|
80037ec: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
80037ee: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
80037f0: 2b00 cmp r3, #0
|
||
|
|
80037f2: d016 beq.n 8003822 <xQueueGenericSendFromISR+0x116>
|
||
|
|
{
|
||
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
||
|
|
80037f4: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
80037f6: 3324 adds r3, #36 ; 0x24
|
||
|
|
80037f8: 4618 mov r0, r3
|
||
|
|
80037fa: f000 feff bl 80045fc <xTaskRemoveFromEventList>
|
||
|
|
80037fe: 4603 mov r3, r0
|
||
|
|
8003800: 2b00 cmp r3, #0
|
||
|
|
8003802: d00e beq.n 8003822 <xQueueGenericSendFromISR+0x116>
|
||
|
|
{
|
||
|
|
/* The task waiting has a higher priority so record that a
|
||
|
|
context switch is required. */
|
||
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
||
|
|
8003804: 687b ldr r3, [r7, #4]
|
||
|
|
8003806: 2b00 cmp r3, #0
|
||
|
|
8003808: d00b beq.n 8003822 <xQueueGenericSendFromISR+0x116>
|
||
|
|
{
|
||
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
||
|
|
800380a: 687b ldr r3, [r7, #4]
|
||
|
|
800380c: 2201 movs r2, #1
|
||
|
|
800380e: 601a str r2, [r3, #0]
|
||
|
|
8003810: e007 b.n 8003822 <xQueueGenericSendFromISR+0x116>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Increment the lock count so the task that unlocks the queue
|
||
|
|
knows that data was posted while it was locked. */
|
||
|
|
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
|
||
|
|
8003812: f897 3033 ldrb.w r3, [r7, #51] ; 0x33
|
||
|
|
8003816: 3301 adds r3, #1
|
||
|
|
8003818: b2db uxtb r3, r3
|
||
|
|
800381a: b25a sxtb r2, r3
|
||
|
|
800381c: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
800381e: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
||
|
|
}
|
||
|
|
|
||
|
|
xReturn = pdPASS;
|
||
|
|
8003822: 2301 movs r3, #1
|
||
|
|
8003824: 63fb str r3, [r7, #60] ; 0x3c
|
||
|
|
{
|
||
|
|
8003826: e001 b.n 800382c <xQueueGenericSendFromISR+0x120>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
|
||
|
|
xReturn = errQUEUE_FULL;
|
||
|
|
8003828: 2300 movs r3, #0
|
||
|
|
800382a: 63fb str r3, [r7, #60] ; 0x3c
|
||
|
|
800382c: 6b7b ldr r3, [r7, #52] ; 0x34
|
||
|
|
800382e: 617b str r3, [r7, #20]
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
||
|
|
{
|
||
|
|
__asm volatile
|
||
|
|
8003830: 697b ldr r3, [r7, #20]
|
||
|
|
8003832: f383 8811 msr BASEPRI, r3
|
||
|
|
(
|
||
|
|
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
|
||
|
|
);
|
||
|
|
}
|
||
|
|
8003836: bf00 nop
|
||
|
|
}
|
||
|
|
}
|
||
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
8003838: 6bfb ldr r3, [r7, #60] ; 0x3c
|
||
|
|
}
|
||
|
|
800383a: 4618 mov r0, r3
|
||
|
|
800383c: 3740 adds r7, #64 ; 0x40
|
||
|
|
800383e: 46bd mov sp, r7
|
||
|
|
8003840: bd80 pop {r7, pc}
|
||
|
|
...
|
||
|
|
|
||
|
|
08003844 <xQueueReceive>:
|
||
|
|
return xReturn;
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
|
||
|
|
{
|
||
|
|
8003844: b580 push {r7, lr}
|
||
|
|
8003846: b08c sub sp, #48 ; 0x30
|
||
|
|
8003848: af00 add r7, sp, #0
|
||
|
|
800384a: 60f8 str r0, [r7, #12]
|
||
|
|
800384c: 60b9 str r1, [r7, #8]
|
||
|
|
800384e: 607a str r2, [r7, #4]
|
||
|
|
BaseType_t xEntryTimeSet = pdFALSE;
|
||
|
|
8003850: 2300 movs r3, #0
|
||
|
|
8003852: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
TimeOut_t xTimeOut;
|
||
|
|
Queue_t * const pxQueue = xQueue;
|
||
|
|
8003854: 68fb ldr r3, [r7, #12]
|
||
|
|
8003856: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
|
||
|
|
/* Check the pointer is not NULL. */
|
||
|
|
configASSERT( ( pxQueue ) );
|
||
|
|
8003858: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
800385a: 2b00 cmp r3, #0
|
||
|
|
800385c: d10a bne.n 8003874 <xQueueReceive+0x30>
|
||
|
|
__asm volatile
|
||
|
|
800385e: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003862: f383 8811 msr BASEPRI, r3
|
||
|
|
8003866: f3bf 8f6f isb sy
|
||
|
|
800386a: f3bf 8f4f dsb sy
|
||
|
|
800386e: 623b str r3, [r7, #32]
|
||
|
|
}
|
||
|
|
8003870: bf00 nop
|
||
|
|
8003872: e7fe b.n 8003872 <xQueueReceive+0x2e>
|
||
|
|
|
||
|
|
/* The buffer into which data is received can only be NULL if the data size
|
||
|
|
is zero (so no data is copied into the buffer. */
|
||
|
|
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
||
|
|
8003874: 68bb ldr r3, [r7, #8]
|
||
|
|
8003876: 2b00 cmp r3, #0
|
||
|
|
8003878: d103 bne.n 8003882 <xQueueReceive+0x3e>
|
||
|
|
800387a: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
800387c: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
800387e: 2b00 cmp r3, #0
|
||
|
|
8003880: d101 bne.n 8003886 <xQueueReceive+0x42>
|
||
|
|
8003882: 2301 movs r3, #1
|
||
|
|
8003884: e000 b.n 8003888 <xQueueReceive+0x44>
|
||
|
|
8003886: 2300 movs r3, #0
|
||
|
|
8003888: 2b00 cmp r3, #0
|
||
|
|
800388a: d10a bne.n 80038a2 <xQueueReceive+0x5e>
|
||
|
|
__asm volatile
|
||
|
|
800388c: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003890: f383 8811 msr BASEPRI, r3
|
||
|
|
8003894: f3bf 8f6f isb sy
|
||
|
|
8003898: f3bf 8f4f dsb sy
|
||
|
|
800389c: 61fb str r3, [r7, #28]
|
||
|
|
}
|
||
|
|
800389e: bf00 nop
|
||
|
|
80038a0: e7fe b.n 80038a0 <xQueueReceive+0x5c>
|
||
|
|
|
||
|
|
/* Cannot block if the scheduler is suspended. */
|
||
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||
|
|
{
|
||
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
||
|
|
80038a2: f001 f86f bl 8004984 <xTaskGetSchedulerState>
|
||
|
|
80038a6: 4603 mov r3, r0
|
||
|
|
80038a8: 2b00 cmp r3, #0
|
||
|
|
80038aa: d102 bne.n 80038b2 <xQueueReceive+0x6e>
|
||
|
|
80038ac: 687b ldr r3, [r7, #4]
|
||
|
|
80038ae: 2b00 cmp r3, #0
|
||
|
|
80038b0: d101 bne.n 80038b6 <xQueueReceive+0x72>
|
||
|
|
80038b2: 2301 movs r3, #1
|
||
|
|
80038b4: e000 b.n 80038b8 <xQueueReceive+0x74>
|
||
|
|
80038b6: 2300 movs r3, #0
|
||
|
|
80038b8: 2b00 cmp r3, #0
|
||
|
|
80038ba: d10a bne.n 80038d2 <xQueueReceive+0x8e>
|
||
|
|
__asm volatile
|
||
|
|
80038bc: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80038c0: f383 8811 msr BASEPRI, r3
|
||
|
|
80038c4: f3bf 8f6f isb sy
|
||
|
|
80038c8: f3bf 8f4f dsb sy
|
||
|
|
80038cc: 61bb str r3, [r7, #24]
|
||
|
|
}
|
||
|
|
80038ce: bf00 nop
|
||
|
|
80038d0: e7fe b.n 80038d0 <xQueueReceive+0x8c>
|
||
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
||
|
|
allow return statements within the function itself. This is done in the
|
||
|
|
interest of execution time efficiency. */
|
||
|
|
for( ;; )
|
||
|
|
{
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
80038d2: f001 fdaf bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
||
|
|
80038d6: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80038d8: 6b9b ldr r3, [r3, #56] ; 0x38
|
||
|
|
80038da: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
|
||
|
|
/* Is there data in the queue now? To be running the calling task
|
||
|
|
must be the highest priority task wanting to access the queue. */
|
||
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
||
|
|
80038dc: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
80038de: 2b00 cmp r3, #0
|
||
|
|
80038e0: d01f beq.n 8003922 <xQueueReceive+0xde>
|
||
|
|
{
|
||
|
|
/* Data available, remove one item. */
|
||
|
|
prvCopyDataFromQueue( pxQueue, pvBuffer );
|
||
|
|
80038e2: 68b9 ldr r1, [r7, #8]
|
||
|
|
80038e4: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
80038e6: f000 f8f7 bl 8003ad8 <prvCopyDataFromQueue>
|
||
|
|
traceQUEUE_RECEIVE( pxQueue );
|
||
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
|
||
|
|
80038ea: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
80038ec: 1e5a subs r2, r3, #1
|
||
|
|
80038ee: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80038f0: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
|
||
|
|
/* There is now space in the queue, were any tasks waiting to
|
||
|
|
post to the queue? If so, unblock the highest priority waiting
|
||
|
|
task. */
|
||
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
||
|
|
80038f2: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80038f4: 691b ldr r3, [r3, #16]
|
||
|
|
80038f6: 2b00 cmp r3, #0
|
||
|
|
80038f8: d00f beq.n 800391a <xQueueReceive+0xd6>
|
||
|
|
{
|
||
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
||
|
|
80038fa: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80038fc: 3310 adds r3, #16
|
||
|
|
80038fe: 4618 mov r0, r3
|
||
|
|
8003900: f000 fe7c bl 80045fc <xTaskRemoveFromEventList>
|
||
|
|
8003904: 4603 mov r3, r0
|
||
|
|
8003906: 2b00 cmp r3, #0
|
||
|
|
8003908: d007 beq.n 800391a <xQueueReceive+0xd6>
|
||
|
|
{
|
||
|
|
queueYIELD_IF_USING_PREEMPTION();
|
||
|
|
800390a: 4b3d ldr r3, [pc, #244] ; (8003a00 <xQueueReceive+0x1bc>)
|
||
|
|
800390c: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
8003910: 601a str r2, [r3, #0]
|
||
|
|
8003912: f3bf 8f4f dsb sy
|
||
|
|
8003916: f3bf 8f6f isb sy
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
800391a: f001 fdbb bl 8005494 <vPortExitCritical>
|
||
|
|
return pdPASS;
|
||
|
|
800391e: 2301 movs r3, #1
|
||
|
|
8003920: e069 b.n 80039f6 <xQueueReceive+0x1b2>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
||
|
|
8003922: 687b ldr r3, [r7, #4]
|
||
|
|
8003924: 2b00 cmp r3, #0
|
||
|
|
8003926: d103 bne.n 8003930 <xQueueReceive+0xec>
|
||
|
|
{
|
||
|
|
/* The queue was empty and no block time is specified (or
|
||
|
|
the block time has expired) so leave now. */
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
8003928: f001 fdb4 bl 8005494 <vPortExitCritical>
|
||
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
||
|
|
return errQUEUE_EMPTY;
|
||
|
|
800392c: 2300 movs r3, #0
|
||
|
|
800392e: e062 b.n 80039f6 <xQueueReceive+0x1b2>
|
||
|
|
}
|
||
|
|
else if( xEntryTimeSet == pdFALSE )
|
||
|
|
8003930: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8003932: 2b00 cmp r3, #0
|
||
|
|
8003934: d106 bne.n 8003944 <xQueueReceive+0x100>
|
||
|
|
{
|
||
|
|
/* The queue was empty and a block time was specified so
|
||
|
|
configure the timeout structure. */
|
||
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
||
|
|
8003936: f107 0310 add.w r3, r7, #16
|
||
|
|
800393a: 4618 mov r0, r3
|
||
|
|
800393c: f000 fec2 bl 80046c4 <vTaskInternalSetTimeOutState>
|
||
|
|
xEntryTimeSet = pdTRUE;
|
||
|
|
8003940: 2301 movs r3, #1
|
||
|
|
8003942: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
/* Entry time was already set. */
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
8003944: f001 fda6 bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
||
|
|
now the critical section has been exited. */
|
||
|
|
|
||
|
|
vTaskSuspendAll();
|
||
|
|
8003948: f000 fc26 bl 8004198 <vTaskSuspendAll>
|
||
|
|
prvLockQueue( pxQueue );
|
||
|
|
800394c: f001 fd72 bl 8005434 <vPortEnterCritical>
|
||
|
|
8003950: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8003952: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
||
|
|
8003956: b25b sxtb r3, r3
|
||
|
|
8003958: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
800395c: d103 bne.n 8003966 <xQueueReceive+0x122>
|
||
|
|
800395e: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8003960: 2200 movs r2, #0
|
||
|
|
8003962: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
||
|
|
8003966: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8003968: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
||
|
|
800396c: b25b sxtb r3, r3
|
||
|
|
800396e: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
8003972: d103 bne.n 800397c <xQueueReceive+0x138>
|
||
|
|
8003974: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8003976: 2200 movs r2, #0
|
||
|
|
8003978: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
||
|
|
800397c: f001 fd8a bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
/* Update the timeout state to see if it has expired yet. */
|
||
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
||
|
|
8003980: 1d3a adds r2, r7, #4
|
||
|
|
8003982: f107 0310 add.w r3, r7, #16
|
||
|
|
8003986: 4611 mov r1, r2
|
||
|
|
8003988: 4618 mov r0, r3
|
||
|
|
800398a: f000 feb1 bl 80046f0 <xTaskCheckForTimeOut>
|
||
|
|
800398e: 4603 mov r3, r0
|
||
|
|
8003990: 2b00 cmp r3, #0
|
||
|
|
8003992: d123 bne.n 80039dc <xQueueReceive+0x198>
|
||
|
|
{
|
||
|
|
/* The timeout has not expired. If the queue is still empty place
|
||
|
|
the task on the list of tasks waiting to receive from the queue. */
|
||
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
||
|
|
8003994: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
8003996: f000 f917 bl 8003bc8 <prvIsQueueEmpty>
|
||
|
|
800399a: 4603 mov r3, r0
|
||
|
|
800399c: 2b00 cmp r3, #0
|
||
|
|
800399e: d017 beq.n 80039d0 <xQueueReceive+0x18c>
|
||
|
|
{
|
||
|
|
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
|
||
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
|
||
|
|
80039a0: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80039a2: 3324 adds r3, #36 ; 0x24
|
||
|
|
80039a4: 687a ldr r2, [r7, #4]
|
||
|
|
80039a6: 4611 mov r1, r2
|
||
|
|
80039a8: 4618 mov r0, r3
|
||
|
|
80039aa: f000 fdd7 bl 800455c <vTaskPlaceOnEventList>
|
||
|
|
prvUnlockQueue( pxQueue );
|
||
|
|
80039ae: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
80039b0: f000 f8b8 bl 8003b24 <prvUnlockQueue>
|
||
|
|
if( xTaskResumeAll() == pdFALSE )
|
||
|
|
80039b4: f000 fbfe bl 80041b4 <xTaskResumeAll>
|
||
|
|
80039b8: 4603 mov r3, r0
|
||
|
|
80039ba: 2b00 cmp r3, #0
|
||
|
|
80039bc: d189 bne.n 80038d2 <xQueueReceive+0x8e>
|
||
|
|
{
|
||
|
|
portYIELD_WITHIN_API();
|
||
|
|
80039be: 4b10 ldr r3, [pc, #64] ; (8003a00 <xQueueReceive+0x1bc>)
|
||
|
|
80039c0: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
80039c4: 601a str r2, [r3, #0]
|
||
|
|
80039c6: f3bf 8f4f dsb sy
|
||
|
|
80039ca: f3bf 8f6f isb sy
|
||
|
|
80039ce: e780 b.n 80038d2 <xQueueReceive+0x8e>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* The queue contains data again. Loop back to try and read the
|
||
|
|
data. */
|
||
|
|
prvUnlockQueue( pxQueue );
|
||
|
|
80039d0: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
80039d2: f000 f8a7 bl 8003b24 <prvUnlockQueue>
|
||
|
|
( void ) xTaskResumeAll();
|
||
|
|
80039d6: f000 fbed bl 80041b4 <xTaskResumeAll>
|
||
|
|
80039da: e77a b.n 80038d2 <xQueueReceive+0x8e>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Timed out. If there is no data in the queue exit, otherwise loop
|
||
|
|
back and attempt to read the data. */
|
||
|
|
prvUnlockQueue( pxQueue );
|
||
|
|
80039dc: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
80039de: f000 f8a1 bl 8003b24 <prvUnlockQueue>
|
||
|
|
( void ) xTaskResumeAll();
|
||
|
|
80039e2: f000 fbe7 bl 80041b4 <xTaskResumeAll>
|
||
|
|
|
||
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
||
|
|
80039e6: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
80039e8: f000 f8ee bl 8003bc8 <prvIsQueueEmpty>
|
||
|
|
80039ec: 4603 mov r3, r0
|
||
|
|
80039ee: 2b00 cmp r3, #0
|
||
|
|
80039f0: f43f af6f beq.w 80038d2 <xQueueReceive+0x8e>
|
||
|
|
{
|
||
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
||
|
|
return errQUEUE_EMPTY;
|
||
|
|
80039f4: 2300 movs r3, #0
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} /*lint -restore */
|
||
|
|
}
|
||
|
|
80039f6: 4618 mov r0, r3
|
||
|
|
80039f8: 3730 adds r7, #48 ; 0x30
|
||
|
|
80039fa: 46bd mov sp, r7
|
||
|
|
80039fc: bd80 pop {r7, pc}
|
||
|
|
80039fe: bf00 nop
|
||
|
|
8003a00: e000ed04 .word 0xe000ed04
|
||
|
|
|
||
|
|
08003a04 <prvCopyDataToQueue>:
|
||
|
|
|
||
|
|
#endif /* configUSE_MUTEXES */
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
|
||
|
|
{
|
||
|
|
8003a04: b580 push {r7, lr}
|
||
|
|
8003a06: b086 sub sp, #24
|
||
|
|
8003a08: af00 add r7, sp, #0
|
||
|
|
8003a0a: 60f8 str r0, [r7, #12]
|
||
|
|
8003a0c: 60b9 str r1, [r7, #8]
|
||
|
|
8003a0e: 607a str r2, [r7, #4]
|
||
|
|
BaseType_t xReturn = pdFALSE;
|
||
|
|
8003a10: 2300 movs r3, #0
|
||
|
|
8003a12: 617b str r3, [r7, #20]
|
||
|
|
UBaseType_t uxMessagesWaiting;
|
||
|
|
|
||
|
|
/* This function is called from a critical section. */
|
||
|
|
|
||
|
|
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
||
|
|
8003a14: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a16: 6b9b ldr r3, [r3, #56] ; 0x38
|
||
|
|
8003a18: 613b str r3, [r7, #16]
|
||
|
|
|
||
|
|
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
|
||
|
|
8003a1a: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a1c: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8003a1e: 2b00 cmp r3, #0
|
||
|
|
8003a20: d10d bne.n 8003a3e <prvCopyDataToQueue+0x3a>
|
||
|
|
{
|
||
|
|
#if ( configUSE_MUTEXES == 1 )
|
||
|
|
{
|
||
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
||
|
|
8003a22: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a24: 681b ldr r3, [r3, #0]
|
||
|
|
8003a26: 2b00 cmp r3, #0
|
||
|
|
8003a28: d14d bne.n 8003ac6 <prvCopyDataToQueue+0xc2>
|
||
|
|
{
|
||
|
|
/* The mutex is no longer being held. */
|
||
|
|
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
|
||
|
|
8003a2a: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a2c: 689b ldr r3, [r3, #8]
|
||
|
|
8003a2e: 4618 mov r0, r3
|
||
|
|
8003a30: f000 ffc6 bl 80049c0 <xTaskPriorityDisinherit>
|
||
|
|
8003a34: 6178 str r0, [r7, #20]
|
||
|
|
pxQueue->u.xSemaphore.xMutexHolder = NULL;
|
||
|
|
8003a36: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a38: 2200 movs r2, #0
|
||
|
|
8003a3a: 609a str r2, [r3, #8]
|
||
|
|
8003a3c: e043 b.n 8003ac6 <prvCopyDataToQueue+0xc2>
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* configUSE_MUTEXES */
|
||
|
|
}
|
||
|
|
else if( xPosition == queueSEND_TO_BACK )
|
||
|
|
8003a3e: 687b ldr r3, [r7, #4]
|
||
|
|
8003a40: 2b00 cmp r3, #0
|
||
|
|
8003a42: d119 bne.n 8003a78 <prvCopyDataToQueue+0x74>
|
||
|
|
{
|
||
|
|
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
||
|
|
8003a44: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a46: 6858 ldr r0, [r3, #4]
|
||
|
|
8003a48: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a4a: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8003a4c: 461a mov r2, r3
|
||
|
|
8003a4e: 68b9 ldr r1, [r7, #8]
|
||
|
|
8003a50: f002 f862 bl 8005b18 <memcpy>
|
||
|
|
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
||
|
|
8003a54: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a56: 685a ldr r2, [r3, #4]
|
||
|
|
8003a58: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a5a: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8003a5c: 441a add r2, r3
|
||
|
|
8003a5e: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a60: 605a str r2, [r3, #4]
|
||
|
|
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
||
|
|
8003a62: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a64: 685a ldr r2, [r3, #4]
|
||
|
|
8003a66: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a68: 689b ldr r3, [r3, #8]
|
||
|
|
8003a6a: 429a cmp r2, r3
|
||
|
|
8003a6c: d32b bcc.n 8003ac6 <prvCopyDataToQueue+0xc2>
|
||
|
|
{
|
||
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
||
|
|
8003a6e: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a70: 681a ldr r2, [r3, #0]
|
||
|
|
8003a72: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a74: 605a str r2, [r3, #4]
|
||
|
|
8003a76: e026 b.n 8003ac6 <prvCopyDataToQueue+0xc2>
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
|
||
|
|
8003a78: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a7a: 68d8 ldr r0, [r3, #12]
|
||
|
|
8003a7c: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a7e: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8003a80: 461a mov r2, r3
|
||
|
|
8003a82: 68b9 ldr r1, [r7, #8]
|
||
|
|
8003a84: f002 f848 bl 8005b18 <memcpy>
|
||
|
|
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
|
||
|
|
8003a88: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a8a: 68da ldr r2, [r3, #12]
|
||
|
|
8003a8c: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a8e: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8003a90: 425b negs r3, r3
|
||
|
|
8003a92: 441a add r2, r3
|
||
|
|
8003a94: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a96: 60da str r2, [r3, #12]
|
||
|
|
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
||
|
|
8003a98: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a9a: 68da ldr r2, [r3, #12]
|
||
|
|
8003a9c: 68fb ldr r3, [r7, #12]
|
||
|
|
8003a9e: 681b ldr r3, [r3, #0]
|
||
|
|
8003aa0: 429a cmp r2, r3
|
||
|
|
8003aa2: d207 bcs.n 8003ab4 <prvCopyDataToQueue+0xb0>
|
||
|
|
{
|
||
|
|
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
|
||
|
|
8003aa4: 68fb ldr r3, [r7, #12]
|
||
|
|
8003aa6: 689a ldr r2, [r3, #8]
|
||
|
|
8003aa8: 68fb ldr r3, [r7, #12]
|
||
|
|
8003aaa: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8003aac: 425b negs r3, r3
|
||
|
|
8003aae: 441a add r2, r3
|
||
|
|
8003ab0: 68fb ldr r3, [r7, #12]
|
||
|
|
8003ab2: 60da str r2, [r3, #12]
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
if( xPosition == queueOVERWRITE )
|
||
|
|
8003ab4: 687b ldr r3, [r7, #4]
|
||
|
|
8003ab6: 2b02 cmp r3, #2
|
||
|
|
8003ab8: d105 bne.n 8003ac6 <prvCopyDataToQueue+0xc2>
|
||
|
|
{
|
||
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
||
|
|
8003aba: 693b ldr r3, [r7, #16]
|
||
|
|
8003abc: 2b00 cmp r3, #0
|
||
|
|
8003abe: d002 beq.n 8003ac6 <prvCopyDataToQueue+0xc2>
|
||
|
|
{
|
||
|
|
/* An item is not being added but overwritten, so subtract
|
||
|
|
one from the recorded number of items in the queue so when
|
||
|
|
one is added again below the number of recorded items remains
|
||
|
|
correct. */
|
||
|
|
--uxMessagesWaiting;
|
||
|
|
8003ac0: 693b ldr r3, [r7, #16]
|
||
|
|
8003ac2: 3b01 subs r3, #1
|
||
|
|
8003ac4: 613b str r3, [r7, #16]
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
|
||
|
|
8003ac6: 693b ldr r3, [r7, #16]
|
||
|
|
8003ac8: 1c5a adds r2, r3, #1
|
||
|
|
8003aca: 68fb ldr r3, [r7, #12]
|
||
|
|
8003acc: 639a str r2, [r3, #56] ; 0x38
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
8003ace: 697b ldr r3, [r7, #20]
|
||
|
|
}
|
||
|
|
8003ad0: 4618 mov r0, r3
|
||
|
|
8003ad2: 3718 adds r7, #24
|
||
|
|
8003ad4: 46bd mov sp, r7
|
||
|
|
8003ad6: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08003ad8 <prvCopyDataFromQueue>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
|
||
|
|
{
|
||
|
|
8003ad8: b580 push {r7, lr}
|
||
|
|
8003ada: b082 sub sp, #8
|
||
|
|
8003adc: af00 add r7, sp, #0
|
||
|
|
8003ade: 6078 str r0, [r7, #4]
|
||
|
|
8003ae0: 6039 str r1, [r7, #0]
|
||
|
|
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
|
||
|
|
8003ae2: 687b ldr r3, [r7, #4]
|
||
|
|
8003ae4: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8003ae6: 2b00 cmp r3, #0
|
||
|
|
8003ae8: d018 beq.n 8003b1c <prvCopyDataFromQueue+0x44>
|
||
|
|
{
|
||
|
|
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
||
|
|
8003aea: 687b ldr r3, [r7, #4]
|
||
|
|
8003aec: 68da ldr r2, [r3, #12]
|
||
|
|
8003aee: 687b ldr r3, [r7, #4]
|
||
|
|
8003af0: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8003af2: 441a add r2, r3
|
||
|
|
8003af4: 687b ldr r3, [r7, #4]
|
||
|
|
8003af6: 60da str r2, [r3, #12]
|
||
|
|
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
|
||
|
|
8003af8: 687b ldr r3, [r7, #4]
|
||
|
|
8003afa: 68da ldr r2, [r3, #12]
|
||
|
|
8003afc: 687b ldr r3, [r7, #4]
|
||
|
|
8003afe: 689b ldr r3, [r3, #8]
|
||
|
|
8003b00: 429a cmp r2, r3
|
||
|
|
8003b02: d303 bcc.n 8003b0c <prvCopyDataFromQueue+0x34>
|
||
|
|
{
|
||
|
|
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
|
||
|
|
8003b04: 687b ldr r3, [r7, #4]
|
||
|
|
8003b06: 681a ldr r2, [r3, #0]
|
||
|
|
8003b08: 687b ldr r3, [r7, #4]
|
||
|
|
8003b0a: 60da str r2, [r3, #12]
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
||
|
|
8003b0c: 687b ldr r3, [r7, #4]
|
||
|
|
8003b0e: 68d9 ldr r1, [r3, #12]
|
||
|
|
8003b10: 687b ldr r3, [r7, #4]
|
||
|
|
8003b12: 6c1b ldr r3, [r3, #64] ; 0x40
|
||
|
|
8003b14: 461a mov r2, r3
|
||
|
|
8003b16: 6838 ldr r0, [r7, #0]
|
||
|
|
8003b18: f001 fffe bl 8005b18 <memcpy>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8003b1c: bf00 nop
|
||
|
|
8003b1e: 3708 adds r7, #8
|
||
|
|
8003b20: 46bd mov sp, r7
|
||
|
|
8003b22: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08003b24 <prvUnlockQueue>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvUnlockQueue( Queue_t * const pxQueue )
|
||
|
|
{
|
||
|
|
8003b24: b580 push {r7, lr}
|
||
|
|
8003b26: b084 sub sp, #16
|
||
|
|
8003b28: af00 add r7, sp, #0
|
||
|
|
8003b2a: 6078 str r0, [r7, #4]
|
||
|
|
|
||
|
|
/* The lock counts contains the number of extra data items placed or
|
||
|
|
removed from the queue while the queue was locked. When a queue is
|
||
|
|
locked items can be added or removed, but the event lists cannot be
|
||
|
|
updated. */
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
8003b2c: f001 fc82 bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
int8_t cTxLock = pxQueue->cTxLock;
|
||
|
|
8003b30: 687b ldr r3, [r7, #4]
|
||
|
|
8003b32: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
||
|
|
8003b36: 73fb strb r3, [r7, #15]
|
||
|
|
|
||
|
|
/* See if data was added to the queue while it was locked. */
|
||
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
||
|
|
8003b38: e011 b.n 8003b5e <prvUnlockQueue+0x3a>
|
||
|
|
}
|
||
|
|
#else /* configUSE_QUEUE_SETS */
|
||
|
|
{
|
||
|
|
/* Tasks that are removed from the event list will get added to
|
||
|
|
the pending ready list as the scheduler is still suspended. */
|
||
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
||
|
|
8003b3a: 687b ldr r3, [r7, #4]
|
||
|
|
8003b3c: 6a5b ldr r3, [r3, #36] ; 0x24
|
||
|
|
8003b3e: 2b00 cmp r3, #0
|
||
|
|
8003b40: d012 beq.n 8003b68 <prvUnlockQueue+0x44>
|
||
|
|
{
|
||
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
||
|
|
8003b42: 687b ldr r3, [r7, #4]
|
||
|
|
8003b44: 3324 adds r3, #36 ; 0x24
|
||
|
|
8003b46: 4618 mov r0, r3
|
||
|
|
8003b48: f000 fd58 bl 80045fc <xTaskRemoveFromEventList>
|
||
|
|
8003b4c: 4603 mov r3, r0
|
||
|
|
8003b4e: 2b00 cmp r3, #0
|
||
|
|
8003b50: d001 beq.n 8003b56 <prvUnlockQueue+0x32>
|
||
|
|
{
|
||
|
|
/* The task waiting has a higher priority so record that
|
||
|
|
a context switch is required. */
|
||
|
|
vTaskMissedYield();
|
||
|
|
8003b52: f000 fe2f bl 80047b4 <vTaskMissedYield>
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* configUSE_QUEUE_SETS */
|
||
|
|
|
||
|
|
--cTxLock;
|
||
|
|
8003b56: 7bfb ldrb r3, [r7, #15]
|
||
|
|
8003b58: 3b01 subs r3, #1
|
||
|
|
8003b5a: b2db uxtb r3, r3
|
||
|
|
8003b5c: 73fb strb r3, [r7, #15]
|
||
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
||
|
|
8003b5e: f997 300f ldrsb.w r3, [r7, #15]
|
||
|
|
8003b62: 2b00 cmp r3, #0
|
||
|
|
8003b64: dce9 bgt.n 8003b3a <prvUnlockQueue+0x16>
|
||
|
|
8003b66: e000 b.n 8003b6a <prvUnlockQueue+0x46>
|
||
|
|
break;
|
||
|
|
8003b68: bf00 nop
|
||
|
|
}
|
||
|
|
|
||
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
||
|
|
8003b6a: 687b ldr r3, [r7, #4]
|
||
|
|
8003b6c: 22ff movs r2, #255 ; 0xff
|
||
|
|
8003b6e: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
8003b72: f001 fc8f bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
/* Do the same for the Rx lock. */
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
8003b76: f001 fc5d bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
int8_t cRxLock = pxQueue->cRxLock;
|
||
|
|
8003b7a: 687b ldr r3, [r7, #4]
|
||
|
|
8003b7c: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
||
|
|
8003b80: 73bb strb r3, [r7, #14]
|
||
|
|
|
||
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
||
|
|
8003b82: e011 b.n 8003ba8 <prvUnlockQueue+0x84>
|
||
|
|
{
|
||
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
||
|
|
8003b84: 687b ldr r3, [r7, #4]
|
||
|
|
8003b86: 691b ldr r3, [r3, #16]
|
||
|
|
8003b88: 2b00 cmp r3, #0
|
||
|
|
8003b8a: d012 beq.n 8003bb2 <prvUnlockQueue+0x8e>
|
||
|
|
{
|
||
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
||
|
|
8003b8c: 687b ldr r3, [r7, #4]
|
||
|
|
8003b8e: 3310 adds r3, #16
|
||
|
|
8003b90: 4618 mov r0, r3
|
||
|
|
8003b92: f000 fd33 bl 80045fc <xTaskRemoveFromEventList>
|
||
|
|
8003b96: 4603 mov r3, r0
|
||
|
|
8003b98: 2b00 cmp r3, #0
|
||
|
|
8003b9a: d001 beq.n 8003ba0 <prvUnlockQueue+0x7c>
|
||
|
|
{
|
||
|
|
vTaskMissedYield();
|
||
|
|
8003b9c: f000 fe0a bl 80047b4 <vTaskMissedYield>
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
--cRxLock;
|
||
|
|
8003ba0: 7bbb ldrb r3, [r7, #14]
|
||
|
|
8003ba2: 3b01 subs r3, #1
|
||
|
|
8003ba4: b2db uxtb r3, r3
|
||
|
|
8003ba6: 73bb strb r3, [r7, #14]
|
||
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
||
|
|
8003ba8: f997 300e ldrsb.w r3, [r7, #14]
|
||
|
|
8003bac: 2b00 cmp r3, #0
|
||
|
|
8003bae: dce9 bgt.n 8003b84 <prvUnlockQueue+0x60>
|
||
|
|
8003bb0: e000 b.n 8003bb4 <prvUnlockQueue+0x90>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
break;
|
||
|
|
8003bb2: bf00 nop
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
||
|
|
8003bb4: 687b ldr r3, [r7, #4]
|
||
|
|
8003bb6: 22ff movs r2, #255 ; 0xff
|
||
|
|
8003bb8: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
8003bbc: f001 fc6a bl 8005494 <vPortExitCritical>
|
||
|
|
}
|
||
|
|
8003bc0: bf00 nop
|
||
|
|
8003bc2: 3710 adds r7, #16
|
||
|
|
8003bc4: 46bd mov sp, r7
|
||
|
|
8003bc6: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08003bc8 <prvIsQueueEmpty>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
|
||
|
|
{
|
||
|
|
8003bc8: b580 push {r7, lr}
|
||
|
|
8003bca: b084 sub sp, #16
|
||
|
|
8003bcc: af00 add r7, sp, #0
|
||
|
|
8003bce: 6078 str r0, [r7, #4]
|
||
|
|
BaseType_t xReturn;
|
||
|
|
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
8003bd0: f001 fc30 bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
|
||
|
|
8003bd4: 687b ldr r3, [r7, #4]
|
||
|
|
8003bd6: 6b9b ldr r3, [r3, #56] ; 0x38
|
||
|
|
8003bd8: 2b00 cmp r3, #0
|
||
|
|
8003bda: d102 bne.n 8003be2 <prvIsQueueEmpty+0x1a>
|
||
|
|
{
|
||
|
|
xReturn = pdTRUE;
|
||
|
|
8003bdc: 2301 movs r3, #1
|
||
|
|
8003bde: 60fb str r3, [r7, #12]
|
||
|
|
8003be0: e001 b.n 8003be6 <prvIsQueueEmpty+0x1e>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
xReturn = pdFALSE;
|
||
|
|
8003be2: 2300 movs r3, #0
|
||
|
|
8003be4: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
8003be6: f001 fc55 bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
8003bea: 68fb ldr r3, [r7, #12]
|
||
|
|
}
|
||
|
|
8003bec: 4618 mov r0, r3
|
||
|
|
8003bee: 3710 adds r7, #16
|
||
|
|
8003bf0: 46bd mov sp, r7
|
||
|
|
8003bf2: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08003bf4 <prvIsQueueFull>:
|
||
|
|
return xReturn;
|
||
|
|
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
|
||
|
|
{
|
||
|
|
8003bf4: b580 push {r7, lr}
|
||
|
|
8003bf6: b084 sub sp, #16
|
||
|
|
8003bf8: af00 add r7, sp, #0
|
||
|
|
8003bfa: 6078 str r0, [r7, #4]
|
||
|
|
BaseType_t xReturn;
|
||
|
|
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
8003bfc: f001 fc1a bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
|
||
|
|
8003c00: 687b ldr r3, [r7, #4]
|
||
|
|
8003c02: 6b9a ldr r2, [r3, #56] ; 0x38
|
||
|
|
8003c04: 687b ldr r3, [r7, #4]
|
||
|
|
8003c06: 6bdb ldr r3, [r3, #60] ; 0x3c
|
||
|
|
8003c08: 429a cmp r2, r3
|
||
|
|
8003c0a: d102 bne.n 8003c12 <prvIsQueueFull+0x1e>
|
||
|
|
{
|
||
|
|
xReturn = pdTRUE;
|
||
|
|
8003c0c: 2301 movs r3, #1
|
||
|
|
8003c0e: 60fb str r3, [r7, #12]
|
||
|
|
8003c10: e001 b.n 8003c16 <prvIsQueueFull+0x22>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
xReturn = pdFALSE;
|
||
|
|
8003c12: 2300 movs r3, #0
|
||
|
|
8003c14: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
8003c16: f001 fc3d bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
8003c1a: 68fb ldr r3, [r7, #12]
|
||
|
|
}
|
||
|
|
8003c1c: 4618 mov r0, r3
|
||
|
|
8003c1e: 3710 adds r7, #16
|
||
|
|
8003c20: 46bd mov sp, r7
|
||
|
|
8003c22: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08003c24 <vQueueAddToRegistry>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
#if ( configQUEUE_REGISTRY_SIZE > 0 )
|
||
|
|
|
||
|
|
void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
|
||
|
|
{
|
||
|
|
8003c24: b480 push {r7}
|
||
|
|
8003c26: b085 sub sp, #20
|
||
|
|
8003c28: af00 add r7, sp, #0
|
||
|
|
8003c2a: 6078 str r0, [r7, #4]
|
||
|
|
8003c2c: 6039 str r1, [r7, #0]
|
||
|
|
UBaseType_t ux;
|
||
|
|
|
||
|
|
/* See if there is an empty space in the registry. A NULL name denotes
|
||
|
|
a free slot. */
|
||
|
|
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
|
||
|
|
8003c2e: 2300 movs r3, #0
|
||
|
|
8003c30: 60fb str r3, [r7, #12]
|
||
|
|
8003c32: e014 b.n 8003c5e <vQueueAddToRegistry+0x3a>
|
||
|
|
{
|
||
|
|
if( xQueueRegistry[ ux ].pcQueueName == NULL )
|
||
|
|
8003c34: 4a0f ldr r2, [pc, #60] ; (8003c74 <vQueueAddToRegistry+0x50>)
|
||
|
|
8003c36: 68fb ldr r3, [r7, #12]
|
||
|
|
8003c38: f852 3033 ldr.w r3, [r2, r3, lsl #3]
|
||
|
|
8003c3c: 2b00 cmp r3, #0
|
||
|
|
8003c3e: d10b bne.n 8003c58 <vQueueAddToRegistry+0x34>
|
||
|
|
{
|
||
|
|
/* Store the information on this queue. */
|
||
|
|
xQueueRegistry[ ux ].pcQueueName = pcQueueName;
|
||
|
|
8003c40: 490c ldr r1, [pc, #48] ; (8003c74 <vQueueAddToRegistry+0x50>)
|
||
|
|
8003c42: 68fb ldr r3, [r7, #12]
|
||
|
|
8003c44: 683a ldr r2, [r7, #0]
|
||
|
|
8003c46: f841 2033 str.w r2, [r1, r3, lsl #3]
|
||
|
|
xQueueRegistry[ ux ].xHandle = xQueue;
|
||
|
|
8003c4a: 4a0a ldr r2, [pc, #40] ; (8003c74 <vQueueAddToRegistry+0x50>)
|
||
|
|
8003c4c: 68fb ldr r3, [r7, #12]
|
||
|
|
8003c4e: 00db lsls r3, r3, #3
|
||
|
|
8003c50: 4413 add r3, r2
|
||
|
|
8003c52: 687a ldr r2, [r7, #4]
|
||
|
|
8003c54: 605a str r2, [r3, #4]
|
||
|
|
|
||
|
|
traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
|
||
|
|
break;
|
||
|
|
8003c56: e006 b.n 8003c66 <vQueueAddToRegistry+0x42>
|
||
|
|
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
|
||
|
|
8003c58: 68fb ldr r3, [r7, #12]
|
||
|
|
8003c5a: 3301 adds r3, #1
|
||
|
|
8003c5c: 60fb str r3, [r7, #12]
|
||
|
|
8003c5e: 68fb ldr r3, [r7, #12]
|
||
|
|
8003c60: 2b07 cmp r3, #7
|
||
|
|
8003c62: d9e7 bls.n 8003c34 <vQueueAddToRegistry+0x10>
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8003c64: bf00 nop
|
||
|
|
8003c66: bf00 nop
|
||
|
|
8003c68: 3714 adds r7, #20
|
||
|
|
8003c6a: 46bd mov sp, r7
|
||
|
|
8003c6c: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8003c70: 4770 bx lr
|
||
|
|
8003c72: bf00 nop
|
||
|
|
8003c74: 20003788 .word 0x20003788
|
||
|
|
|
||
|
|
08003c78 <vQueueWaitForMessageRestricted>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
#if ( configUSE_TIMERS == 1 )
|
||
|
|
|
||
|
|
void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
|
||
|
|
{
|
||
|
|
8003c78: b580 push {r7, lr}
|
||
|
|
8003c7a: b086 sub sp, #24
|
||
|
|
8003c7c: af00 add r7, sp, #0
|
||
|
|
8003c7e: 60f8 str r0, [r7, #12]
|
||
|
|
8003c80: 60b9 str r1, [r7, #8]
|
||
|
|
8003c82: 607a str r2, [r7, #4]
|
||
|
|
Queue_t * const pxQueue = xQueue;
|
||
|
|
8003c84: 68fb ldr r3, [r7, #12]
|
||
|
|
8003c86: 617b str r3, [r7, #20]
|
||
|
|
will not actually cause the task to block, just place it on a blocked
|
||
|
|
list. It will not block until the scheduler is unlocked - at which
|
||
|
|
time a yield will be performed. If an item is added to the queue while
|
||
|
|
the queue is locked, and the calling task blocks on the queue, then the
|
||
|
|
calling task will be immediately unblocked when the queue is unlocked. */
|
||
|
|
prvLockQueue( pxQueue );
|
||
|
|
8003c88: f001 fbd4 bl 8005434 <vPortEnterCritical>
|
||
|
|
8003c8c: 697b ldr r3, [r7, #20]
|
||
|
|
8003c8e: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
||
|
|
8003c92: b25b sxtb r3, r3
|
||
|
|
8003c94: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
8003c98: d103 bne.n 8003ca2 <vQueueWaitForMessageRestricted+0x2a>
|
||
|
|
8003c9a: 697b ldr r3, [r7, #20]
|
||
|
|
8003c9c: 2200 movs r2, #0
|
||
|
|
8003c9e: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
||
|
|
8003ca2: 697b ldr r3, [r7, #20]
|
||
|
|
8003ca4: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
||
|
|
8003ca8: b25b sxtb r3, r3
|
||
|
|
8003caa: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
8003cae: d103 bne.n 8003cb8 <vQueueWaitForMessageRestricted+0x40>
|
||
|
|
8003cb0: 697b ldr r3, [r7, #20]
|
||
|
|
8003cb2: 2200 movs r2, #0
|
||
|
|
8003cb4: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
||
|
|
8003cb8: f001 fbec bl 8005494 <vPortExitCritical>
|
||
|
|
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
|
||
|
|
8003cbc: 697b ldr r3, [r7, #20]
|
||
|
|
8003cbe: 6b9b ldr r3, [r3, #56] ; 0x38
|
||
|
|
8003cc0: 2b00 cmp r3, #0
|
||
|
|
8003cc2: d106 bne.n 8003cd2 <vQueueWaitForMessageRestricted+0x5a>
|
||
|
|
{
|
||
|
|
/* There is nothing in the queue, block for the specified period. */
|
||
|
|
vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
|
||
|
|
8003cc4: 697b ldr r3, [r7, #20]
|
||
|
|
8003cc6: 3324 adds r3, #36 ; 0x24
|
||
|
|
8003cc8: 687a ldr r2, [r7, #4]
|
||
|
|
8003cca: 68b9 ldr r1, [r7, #8]
|
||
|
|
8003ccc: 4618 mov r0, r3
|
||
|
|
8003cce: f000 fc69 bl 80045a4 <vTaskPlaceOnEventListRestricted>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
prvUnlockQueue( pxQueue );
|
||
|
|
8003cd2: 6978 ldr r0, [r7, #20]
|
||
|
|
8003cd4: f7ff ff26 bl 8003b24 <prvUnlockQueue>
|
||
|
|
}
|
||
|
|
8003cd8: bf00 nop
|
||
|
|
8003cda: 3718 adds r7, #24
|
||
|
|
8003cdc: 46bd mov sp, r7
|
||
|
|
8003cde: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08003ce0 <xTaskCreateStatic>:
|
||
|
|
const uint32_t ulStackDepth,
|
||
|
|
void * const pvParameters,
|
||
|
|
UBaseType_t uxPriority,
|
||
|
|
StackType_t * const puxStackBuffer,
|
||
|
|
StaticTask_t * const pxTaskBuffer )
|
||
|
|
{
|
||
|
|
8003ce0: b580 push {r7, lr}
|
||
|
|
8003ce2: b08e sub sp, #56 ; 0x38
|
||
|
|
8003ce4: af04 add r7, sp, #16
|
||
|
|
8003ce6: 60f8 str r0, [r7, #12]
|
||
|
|
8003ce8: 60b9 str r1, [r7, #8]
|
||
|
|
8003cea: 607a str r2, [r7, #4]
|
||
|
|
8003cec: 603b str r3, [r7, #0]
|
||
|
|
TCB_t *pxNewTCB;
|
||
|
|
TaskHandle_t xReturn;
|
||
|
|
|
||
|
|
configASSERT( puxStackBuffer != NULL );
|
||
|
|
8003cee: 6b7b ldr r3, [r7, #52] ; 0x34
|
||
|
|
8003cf0: 2b00 cmp r3, #0
|
||
|
|
8003cf2: d10a bne.n 8003d0a <xTaskCreateStatic+0x2a>
|
||
|
|
__asm volatile
|
||
|
|
8003cf4: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003cf8: f383 8811 msr BASEPRI, r3
|
||
|
|
8003cfc: f3bf 8f6f isb sy
|
||
|
|
8003d00: f3bf 8f4f dsb sy
|
||
|
|
8003d04: 623b str r3, [r7, #32]
|
||
|
|
}
|
||
|
|
8003d06: bf00 nop
|
||
|
|
8003d08: e7fe b.n 8003d08 <xTaskCreateStatic+0x28>
|
||
|
|
configASSERT( pxTaskBuffer != NULL );
|
||
|
|
8003d0a: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
8003d0c: 2b00 cmp r3, #0
|
||
|
|
8003d0e: d10a bne.n 8003d26 <xTaskCreateStatic+0x46>
|
||
|
|
__asm volatile
|
||
|
|
8003d10: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003d14: f383 8811 msr BASEPRI, r3
|
||
|
|
8003d18: f3bf 8f6f isb sy
|
||
|
|
8003d1c: f3bf 8f4f dsb sy
|
||
|
|
8003d20: 61fb str r3, [r7, #28]
|
||
|
|
}
|
||
|
|
8003d22: bf00 nop
|
||
|
|
8003d24: e7fe b.n 8003d24 <xTaskCreateStatic+0x44>
|
||
|
|
#if( configASSERT_DEFINED == 1 )
|
||
|
|
{
|
||
|
|
/* Sanity check that the size of the structure used to declare a
|
||
|
|
variable of type StaticTask_t equals the size of the real task
|
||
|
|
structure. */
|
||
|
|
volatile size_t xSize = sizeof( StaticTask_t );
|
||
|
|
8003d26: 23bc movs r3, #188 ; 0xbc
|
||
|
|
8003d28: 613b str r3, [r7, #16]
|
||
|
|
configASSERT( xSize == sizeof( TCB_t ) );
|
||
|
|
8003d2a: 693b ldr r3, [r7, #16]
|
||
|
|
8003d2c: 2bbc cmp r3, #188 ; 0xbc
|
||
|
|
8003d2e: d00a beq.n 8003d46 <xTaskCreateStatic+0x66>
|
||
|
|
__asm volatile
|
||
|
|
8003d30: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003d34: f383 8811 msr BASEPRI, r3
|
||
|
|
8003d38: f3bf 8f6f isb sy
|
||
|
|
8003d3c: f3bf 8f4f dsb sy
|
||
|
|
8003d40: 61bb str r3, [r7, #24]
|
||
|
|
}
|
||
|
|
8003d42: bf00 nop
|
||
|
|
8003d44: e7fe b.n 8003d44 <xTaskCreateStatic+0x64>
|
||
|
|
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
|
||
|
|
8003d46: 693b ldr r3, [r7, #16]
|
||
|
|
}
|
||
|
|
#endif /* configASSERT_DEFINED */
|
||
|
|
|
||
|
|
|
||
|
|
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
|
||
|
|
8003d48: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
8003d4a: 2b00 cmp r3, #0
|
||
|
|
8003d4c: d01e beq.n 8003d8c <xTaskCreateStatic+0xac>
|
||
|
|
8003d4e: 6b7b ldr r3, [r7, #52] ; 0x34
|
||
|
|
8003d50: 2b00 cmp r3, #0
|
||
|
|
8003d52: d01b beq.n 8003d8c <xTaskCreateStatic+0xac>
|
||
|
|
{
|
||
|
|
/* The memory used for the task's TCB and stack are passed into this
|
||
|
|
function - use them. */
|
||
|
|
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
|
||
|
|
8003d54: 6bbb ldr r3, [r7, #56] ; 0x38
|
||
|
|
8003d56: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
|
||
|
|
8003d58: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8003d5a: 6b7a ldr r2, [r7, #52] ; 0x34
|
||
|
|
8003d5c: 631a str r2, [r3, #48] ; 0x30
|
||
|
|
|
||
|
|
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
|
||
|
|
{
|
||
|
|
/* Tasks can be created statically or dynamically, so note this
|
||
|
|
task was created statically in case the task is later deleted. */
|
||
|
|
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
|
||
|
|
8003d5e: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8003d60: 2202 movs r2, #2
|
||
|
|
8003d62: f883 20b9 strb.w r2, [r3, #185] ; 0xb9
|
||
|
|
}
|
||
|
|
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
|
||
|
|
|
||
|
|
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
|
||
|
|
8003d66: 2300 movs r3, #0
|
||
|
|
8003d68: 9303 str r3, [sp, #12]
|
||
|
|
8003d6a: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8003d6c: 9302 str r3, [sp, #8]
|
||
|
|
8003d6e: f107 0314 add.w r3, r7, #20
|
||
|
|
8003d72: 9301 str r3, [sp, #4]
|
||
|
|
8003d74: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003d76: 9300 str r3, [sp, #0]
|
||
|
|
8003d78: 683b ldr r3, [r7, #0]
|
||
|
|
8003d7a: 687a ldr r2, [r7, #4]
|
||
|
|
8003d7c: 68b9 ldr r1, [r7, #8]
|
||
|
|
8003d7e: 68f8 ldr r0, [r7, #12]
|
||
|
|
8003d80: f000 f850 bl 8003e24 <prvInitialiseNewTask>
|
||
|
|
prvAddNewTaskToReadyList( pxNewTCB );
|
||
|
|
8003d84: 6a78 ldr r0, [r7, #36] ; 0x24
|
||
|
|
8003d86: f000 f8f3 bl 8003f70 <prvAddNewTaskToReadyList>
|
||
|
|
8003d8a: e001 b.n 8003d90 <xTaskCreateStatic+0xb0>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
xReturn = NULL;
|
||
|
|
8003d8c: 2300 movs r3, #0
|
||
|
|
8003d8e: 617b str r3, [r7, #20]
|
||
|
|
}
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
8003d90: 697b ldr r3, [r7, #20]
|
||
|
|
}
|
||
|
|
8003d92: 4618 mov r0, r3
|
||
|
|
8003d94: 3728 adds r7, #40 ; 0x28
|
||
|
|
8003d96: 46bd mov sp, r7
|
||
|
|
8003d98: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08003d9a <xTaskCreate>:
|
||
|
|
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
|
||
|
|
const configSTACK_DEPTH_TYPE usStackDepth,
|
||
|
|
void * const pvParameters,
|
||
|
|
UBaseType_t uxPriority,
|
||
|
|
TaskHandle_t * const pxCreatedTask )
|
||
|
|
{
|
||
|
|
8003d9a: b580 push {r7, lr}
|
||
|
|
8003d9c: b08c sub sp, #48 ; 0x30
|
||
|
|
8003d9e: af04 add r7, sp, #16
|
||
|
|
8003da0: 60f8 str r0, [r7, #12]
|
||
|
|
8003da2: 60b9 str r1, [r7, #8]
|
||
|
|
8003da4: 603b str r3, [r7, #0]
|
||
|
|
8003da6: 4613 mov r3, r2
|
||
|
|
8003da8: 80fb strh r3, [r7, #6]
|
||
|
|
#else /* portSTACK_GROWTH */
|
||
|
|
{
|
||
|
|
StackType_t *pxStack;
|
||
|
|
|
||
|
|
/* Allocate space for the stack used by the task being created. */
|
||
|
|
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
|
||
|
|
8003daa: 88fb ldrh r3, [r7, #6]
|
||
|
|
8003dac: 009b lsls r3, r3, #2
|
||
|
|
8003dae: 4618 mov r0, r3
|
||
|
|
8003db0: f001 fc62 bl 8005678 <pvPortMalloc>
|
||
|
|
8003db4: 6178 str r0, [r7, #20]
|
||
|
|
|
||
|
|
if( pxStack != NULL )
|
||
|
|
8003db6: 697b ldr r3, [r7, #20]
|
||
|
|
8003db8: 2b00 cmp r3, #0
|
||
|
|
8003dba: d00e beq.n 8003dda <xTaskCreate+0x40>
|
||
|
|
{
|
||
|
|
/* Allocate space for the TCB. */
|
||
|
|
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
|
||
|
|
8003dbc: 20bc movs r0, #188 ; 0xbc
|
||
|
|
8003dbe: f001 fc5b bl 8005678 <pvPortMalloc>
|
||
|
|
8003dc2: 61f8 str r0, [r7, #28]
|
||
|
|
|
||
|
|
if( pxNewTCB != NULL )
|
||
|
|
8003dc4: 69fb ldr r3, [r7, #28]
|
||
|
|
8003dc6: 2b00 cmp r3, #0
|
||
|
|
8003dc8: d003 beq.n 8003dd2 <xTaskCreate+0x38>
|
||
|
|
{
|
||
|
|
/* Store the stack location in the TCB. */
|
||
|
|
pxNewTCB->pxStack = pxStack;
|
||
|
|
8003dca: 69fb ldr r3, [r7, #28]
|
||
|
|
8003dcc: 697a ldr r2, [r7, #20]
|
||
|
|
8003dce: 631a str r2, [r3, #48] ; 0x30
|
||
|
|
8003dd0: e005 b.n 8003dde <xTaskCreate+0x44>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* The stack cannot be used as the TCB was not created. Free
|
||
|
|
it again. */
|
||
|
|
vPortFree( pxStack );
|
||
|
|
8003dd2: 6978 ldr r0, [r7, #20]
|
||
|
|
8003dd4: f001 fcf4 bl 80057c0 <vPortFree>
|
||
|
|
8003dd8: e001 b.n 8003dde <xTaskCreate+0x44>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
pxNewTCB = NULL;
|
||
|
|
8003dda: 2300 movs r3, #0
|
||
|
|
8003ddc: 61fb str r3, [r7, #28]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* portSTACK_GROWTH */
|
||
|
|
|
||
|
|
if( pxNewTCB != NULL )
|
||
|
|
8003dde: 69fb ldr r3, [r7, #28]
|
||
|
|
8003de0: 2b00 cmp r3, #0
|
||
|
|
8003de2: d017 beq.n 8003e14 <xTaskCreate+0x7a>
|
||
|
|
{
|
||
|
|
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
|
||
|
|
{
|
||
|
|
/* Tasks can be created statically or dynamically, so note this
|
||
|
|
task was created dynamically in case it is later deleted. */
|
||
|
|
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
|
||
|
|
8003de4: 69fb ldr r3, [r7, #28]
|
||
|
|
8003de6: 2200 movs r2, #0
|
||
|
|
8003de8: f883 20b9 strb.w r2, [r3, #185] ; 0xb9
|
||
|
|
}
|
||
|
|
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
|
||
|
|
|
||
|
|
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
|
||
|
|
8003dec: 88fa ldrh r2, [r7, #6]
|
||
|
|
8003dee: 2300 movs r3, #0
|
||
|
|
8003df0: 9303 str r3, [sp, #12]
|
||
|
|
8003df2: 69fb ldr r3, [r7, #28]
|
||
|
|
8003df4: 9302 str r3, [sp, #8]
|
||
|
|
8003df6: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8003df8: 9301 str r3, [sp, #4]
|
||
|
|
8003dfa: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8003dfc: 9300 str r3, [sp, #0]
|
||
|
|
8003dfe: 683b ldr r3, [r7, #0]
|
||
|
|
8003e00: 68b9 ldr r1, [r7, #8]
|
||
|
|
8003e02: 68f8 ldr r0, [r7, #12]
|
||
|
|
8003e04: f000 f80e bl 8003e24 <prvInitialiseNewTask>
|
||
|
|
prvAddNewTaskToReadyList( pxNewTCB );
|
||
|
|
8003e08: 69f8 ldr r0, [r7, #28]
|
||
|
|
8003e0a: f000 f8b1 bl 8003f70 <prvAddNewTaskToReadyList>
|
||
|
|
xReturn = pdPASS;
|
||
|
|
8003e0e: 2301 movs r3, #1
|
||
|
|
8003e10: 61bb str r3, [r7, #24]
|
||
|
|
8003e12: e002 b.n 8003e1a <xTaskCreate+0x80>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
|
||
|
|
8003e14: f04f 33ff mov.w r3, #4294967295
|
||
|
|
8003e18: 61bb str r3, [r7, #24]
|
||
|
|
}
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
8003e1a: 69bb ldr r3, [r7, #24]
|
||
|
|
}
|
||
|
|
8003e1c: 4618 mov r0, r3
|
||
|
|
8003e1e: 3720 adds r7, #32
|
||
|
|
8003e20: 46bd mov sp, r7
|
||
|
|
8003e22: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08003e24 <prvInitialiseNewTask>:
|
||
|
|
void * const pvParameters,
|
||
|
|
UBaseType_t uxPriority,
|
||
|
|
TaskHandle_t * const pxCreatedTask,
|
||
|
|
TCB_t *pxNewTCB,
|
||
|
|
const MemoryRegion_t * const xRegions )
|
||
|
|
{
|
||
|
|
8003e24: b580 push {r7, lr}
|
||
|
|
8003e26: b088 sub sp, #32
|
||
|
|
8003e28: af00 add r7, sp, #0
|
||
|
|
8003e2a: 60f8 str r0, [r7, #12]
|
||
|
|
8003e2c: 60b9 str r1, [r7, #8]
|
||
|
|
8003e2e: 607a str r2, [r7, #4]
|
||
|
|
8003e30: 603b str r3, [r7, #0]
|
||
|
|
|
||
|
|
/* Avoid dependency on memset() if it is not required. */
|
||
|
|
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
|
||
|
|
{
|
||
|
|
/* Fill the stack with a known value to assist debugging. */
|
||
|
|
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
|
||
|
|
8003e32: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003e34: 6b18 ldr r0, [r3, #48] ; 0x30
|
||
|
|
8003e36: 687b ldr r3, [r7, #4]
|
||
|
|
8003e38: 009b lsls r3, r3, #2
|
||
|
|
8003e3a: 461a mov r2, r3
|
||
|
|
8003e3c: 21a5 movs r1, #165 ; 0xa5
|
||
|
|
8003e3e: f001 fe79 bl 8005b34 <memset>
|
||
|
|
grows from high memory to low (as per the 80x86) or vice versa.
|
||
|
|
portSTACK_GROWTH is used to make the result positive or negative as required
|
||
|
|
by the port. */
|
||
|
|
#if( portSTACK_GROWTH < 0 )
|
||
|
|
{
|
||
|
|
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
|
||
|
|
8003e42: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003e44: 6b1a ldr r2, [r3, #48] ; 0x30
|
||
|
|
8003e46: 687b ldr r3, [r7, #4]
|
||
|
|
8003e48: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000
|
||
|
|
8003e4c: 3b01 subs r3, #1
|
||
|
|
8003e4e: 009b lsls r3, r3, #2
|
||
|
|
8003e50: 4413 add r3, r2
|
||
|
|
8003e52: 61bb str r3, [r7, #24]
|
||
|
|
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
|
||
|
|
8003e54: 69bb ldr r3, [r7, #24]
|
||
|
|
8003e56: f023 0307 bic.w r3, r3, #7
|
||
|
|
8003e5a: 61bb str r3, [r7, #24]
|
||
|
|
|
||
|
|
/* Check the alignment of the calculated top of stack is correct. */
|
||
|
|
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
|
||
|
|
8003e5c: 69bb ldr r3, [r7, #24]
|
||
|
|
8003e5e: f003 0307 and.w r3, r3, #7
|
||
|
|
8003e62: 2b00 cmp r3, #0
|
||
|
|
8003e64: d00a beq.n 8003e7c <prvInitialiseNewTask+0x58>
|
||
|
|
__asm volatile
|
||
|
|
8003e66: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8003e6a: f383 8811 msr BASEPRI, r3
|
||
|
|
8003e6e: f3bf 8f6f isb sy
|
||
|
|
8003e72: f3bf 8f4f dsb sy
|
||
|
|
8003e76: 617b str r3, [r7, #20]
|
||
|
|
}
|
||
|
|
8003e78: bf00 nop
|
||
|
|
8003e7a: e7fe b.n 8003e7a <prvInitialiseNewTask+0x56>
|
||
|
|
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
|
||
|
|
}
|
||
|
|
#endif /* portSTACK_GROWTH */
|
||
|
|
|
||
|
|
/* Store the task name in the TCB. */
|
||
|
|
if( pcName != NULL )
|
||
|
|
8003e7c: 68bb ldr r3, [r7, #8]
|
||
|
|
8003e7e: 2b00 cmp r3, #0
|
||
|
|
8003e80: d01f beq.n 8003ec2 <prvInitialiseNewTask+0x9e>
|
||
|
|
{
|
||
|
|
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
|
||
|
|
8003e82: 2300 movs r3, #0
|
||
|
|
8003e84: 61fb str r3, [r7, #28]
|
||
|
|
8003e86: e012 b.n 8003eae <prvInitialiseNewTask+0x8a>
|
||
|
|
{
|
||
|
|
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
|
||
|
|
8003e88: 68ba ldr r2, [r7, #8]
|
||
|
|
8003e8a: 69fb ldr r3, [r7, #28]
|
||
|
|
8003e8c: 4413 add r3, r2
|
||
|
|
8003e8e: 7819 ldrb r1, [r3, #0]
|
||
|
|
8003e90: 6b3a ldr r2, [r7, #48] ; 0x30
|
||
|
|
8003e92: 69fb ldr r3, [r7, #28]
|
||
|
|
8003e94: 4413 add r3, r2
|
||
|
|
8003e96: 3334 adds r3, #52 ; 0x34
|
||
|
|
8003e98: 460a mov r2, r1
|
||
|
|
8003e9a: 701a strb r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
|
||
|
|
configMAX_TASK_NAME_LEN characters just in case the memory after the
|
||
|
|
string is not accessible (extremely unlikely). */
|
||
|
|
if( pcName[ x ] == ( char ) 0x00 )
|
||
|
|
8003e9c: 68ba ldr r2, [r7, #8]
|
||
|
|
8003e9e: 69fb ldr r3, [r7, #28]
|
||
|
|
8003ea0: 4413 add r3, r2
|
||
|
|
8003ea2: 781b ldrb r3, [r3, #0]
|
||
|
|
8003ea4: 2b00 cmp r3, #0
|
||
|
|
8003ea6: d006 beq.n 8003eb6 <prvInitialiseNewTask+0x92>
|
||
|
|
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
|
||
|
|
8003ea8: 69fb ldr r3, [r7, #28]
|
||
|
|
8003eaa: 3301 adds r3, #1
|
||
|
|
8003eac: 61fb str r3, [r7, #28]
|
||
|
|
8003eae: 69fb ldr r3, [r7, #28]
|
||
|
|
8003eb0: 2b0f cmp r3, #15
|
||
|
|
8003eb2: d9e9 bls.n 8003e88 <prvInitialiseNewTask+0x64>
|
||
|
|
8003eb4: e000 b.n 8003eb8 <prvInitialiseNewTask+0x94>
|
||
|
|
{
|
||
|
|
break;
|
||
|
|
8003eb6: bf00 nop
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Ensure the name string is terminated in the case that the string length
|
||
|
|
was greater or equal to configMAX_TASK_NAME_LEN. */
|
||
|
|
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
|
||
|
|
8003eb8: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003eba: 2200 movs r2, #0
|
||
|
|
8003ebc: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
||
|
|
8003ec0: e003 b.n 8003eca <prvInitialiseNewTask+0xa6>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* The task has not been given a name, so just ensure there is a NULL
|
||
|
|
terminator when it is read out. */
|
||
|
|
pxNewTCB->pcTaskName[ 0 ] = 0x00;
|
||
|
|
8003ec2: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003ec4: 2200 movs r2, #0
|
||
|
|
8003ec6: f883 2034 strb.w r2, [r3, #52] ; 0x34
|
||
|
|
}
|
||
|
|
|
||
|
|
/* This is used as an array index so must ensure it's not too large. First
|
||
|
|
remove the privilege bit if one is present. */
|
||
|
|
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
|
||
|
|
8003eca: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8003ecc: 2b37 cmp r3, #55 ; 0x37
|
||
|
|
8003ece: d901 bls.n 8003ed4 <prvInitialiseNewTask+0xb0>
|
||
|
|
{
|
||
|
|
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
|
||
|
|
8003ed0: 2337 movs r3, #55 ; 0x37
|
||
|
|
8003ed2: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
pxNewTCB->uxPriority = uxPriority;
|
||
|
|
8003ed4: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003ed6: 6aba ldr r2, [r7, #40] ; 0x28
|
||
|
|
8003ed8: 62da str r2, [r3, #44] ; 0x2c
|
||
|
|
#if ( configUSE_MUTEXES == 1 )
|
||
|
|
{
|
||
|
|
pxNewTCB->uxBasePriority = uxPriority;
|
||
|
|
8003eda: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003edc: 6aba ldr r2, [r7, #40] ; 0x28
|
||
|
|
8003ede: 64da str r2, [r3, #76] ; 0x4c
|
||
|
|
pxNewTCB->uxMutexesHeld = 0;
|
||
|
|
8003ee0: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003ee2: 2200 movs r2, #0
|
||
|
|
8003ee4: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
}
|
||
|
|
#endif /* configUSE_MUTEXES */
|
||
|
|
|
||
|
|
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
|
||
|
|
8003ee6: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003ee8: 3304 adds r3, #4
|
||
|
|
8003eea: 4618 mov r0, r3
|
||
|
|
8003eec: f7ff f978 bl 80031e0 <vListInitialiseItem>
|
||
|
|
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
|
||
|
|
8003ef0: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003ef2: 3318 adds r3, #24
|
||
|
|
8003ef4: 4618 mov r0, r3
|
||
|
|
8003ef6: f7ff f973 bl 80031e0 <vListInitialiseItem>
|
||
|
|
|
||
|
|
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
|
||
|
|
back to the containing TCB from a generic item in a list. */
|
||
|
|
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
|
||
|
|
8003efa: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003efc: 6b3a ldr r2, [r7, #48] ; 0x30
|
||
|
|
8003efe: 611a str r2, [r3, #16]
|
||
|
|
|
||
|
|
/* Event lists are always in priority order. */
|
||
|
|
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
||
|
|
8003f00: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8003f02: f1c3 0238 rsb r2, r3, #56 ; 0x38
|
||
|
|
8003f06: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003f08: 619a str r2, [r3, #24]
|
||
|
|
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
|
||
|
|
8003f0a: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003f0c: 6b3a ldr r2, [r7, #48] ; 0x30
|
||
|
|
8003f0e: 625a str r2, [r3, #36] ; 0x24
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
|
||
|
|
{
|
||
|
|
pxNewTCB->ulNotifiedValue = 0;
|
||
|
|
8003f10: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003f12: 2200 movs r2, #0
|
||
|
|
8003f14: f8c3 20b4 str.w r2, [r3, #180] ; 0xb4
|
||
|
|
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
|
||
|
|
8003f18: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003f1a: 2200 movs r2, #0
|
||
|
|
8003f1c: f883 20b8 strb.w r2, [r3, #184] ; 0xb8
|
||
|
|
#if ( configUSE_NEWLIB_REENTRANT == 1 )
|
||
|
|
{
|
||
|
|
/* Initialise this task's Newlib reent structure.
|
||
|
|
See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
|
||
|
|
for additional information. */
|
||
|
|
_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
|
||
|
|
8003f20: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003f22: 3354 adds r3, #84 ; 0x54
|
||
|
|
8003f24: 2260 movs r2, #96 ; 0x60
|
||
|
|
8003f26: 2100 movs r1, #0
|
||
|
|
8003f28: 4618 mov r0, r3
|
||
|
|
8003f2a: f001 fe03 bl 8005b34 <memset>
|
||
|
|
8003f2e: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003f30: 4a0c ldr r2, [pc, #48] ; (8003f64 <prvInitialiseNewTask+0x140>)
|
||
|
|
8003f32: 659a str r2, [r3, #88] ; 0x58
|
||
|
|
8003f34: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003f36: 4a0c ldr r2, [pc, #48] ; (8003f68 <prvInitialiseNewTask+0x144>)
|
||
|
|
8003f38: 65da str r2, [r3, #92] ; 0x5c
|
||
|
|
8003f3a: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003f3c: 4a0b ldr r2, [pc, #44] ; (8003f6c <prvInitialiseNewTask+0x148>)
|
||
|
|
8003f3e: 661a str r2, [r3, #96] ; 0x60
|
||
|
|
}
|
||
|
|
#endif /* portSTACK_GROWTH */
|
||
|
|
}
|
||
|
|
#else /* portHAS_STACK_OVERFLOW_CHECKING */
|
||
|
|
{
|
||
|
|
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
|
||
|
|
8003f40: 683a ldr r2, [r7, #0]
|
||
|
|
8003f42: 68f9 ldr r1, [r7, #12]
|
||
|
|
8003f44: 69b8 ldr r0, [r7, #24]
|
||
|
|
8003f46: f001 f94b bl 80051e0 <pxPortInitialiseStack>
|
||
|
|
8003f4a: 4602 mov r2, r0
|
||
|
|
8003f4c: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8003f4e: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
|
||
|
|
}
|
||
|
|
#endif /* portUSING_MPU_WRAPPERS */
|
||
|
|
|
||
|
|
if( pxCreatedTask != NULL )
|
||
|
|
8003f50: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8003f52: 2b00 cmp r3, #0
|
||
|
|
8003f54: d002 beq.n 8003f5c <prvInitialiseNewTask+0x138>
|
||
|
|
{
|
||
|
|
/* Pass the handle out in an anonymous way. The handle can be used to
|
||
|
|
change the created task's priority, delete the created task, etc.*/
|
||
|
|
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
|
||
|
|
8003f56: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8003f58: 6b3a ldr r2, [r7, #48] ; 0x30
|
||
|
|
8003f5a: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8003f5c: bf00 nop
|
||
|
|
8003f5e: 3720 adds r7, #32
|
||
|
|
8003f60: 46bd mov sp, r7
|
||
|
|
8003f62: bd80 pop {r7, pc}
|
||
|
|
8003f64: 08005d90 .word 0x08005d90
|
||
|
|
8003f68: 08005db0 .word 0x08005db0
|
||
|
|
8003f6c: 08005d70 .word 0x08005d70
|
||
|
|
|
||
|
|
08003f70 <prvAddNewTaskToReadyList>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
|
||
|
|
{
|
||
|
|
8003f70: b580 push {r7, lr}
|
||
|
|
8003f72: b082 sub sp, #8
|
||
|
|
8003f74: af00 add r7, sp, #0
|
||
|
|
8003f76: 6078 str r0, [r7, #4]
|
||
|
|
/* Ensure interrupts don't access the task lists while the lists are being
|
||
|
|
updated. */
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
8003f78: f001 fa5c bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
uxCurrentNumberOfTasks++;
|
||
|
|
8003f7c: 4b2d ldr r3, [pc, #180] ; (8004034 <prvAddNewTaskToReadyList+0xc4>)
|
||
|
|
8003f7e: 681b ldr r3, [r3, #0]
|
||
|
|
8003f80: 3301 adds r3, #1
|
||
|
|
8003f82: 4a2c ldr r2, [pc, #176] ; (8004034 <prvAddNewTaskToReadyList+0xc4>)
|
||
|
|
8003f84: 6013 str r3, [r2, #0]
|
||
|
|
if( pxCurrentTCB == NULL )
|
||
|
|
8003f86: 4b2c ldr r3, [pc, #176] ; (8004038 <prvAddNewTaskToReadyList+0xc8>)
|
||
|
|
8003f88: 681b ldr r3, [r3, #0]
|
||
|
|
8003f8a: 2b00 cmp r3, #0
|
||
|
|
8003f8c: d109 bne.n 8003fa2 <prvAddNewTaskToReadyList+0x32>
|
||
|
|
{
|
||
|
|
/* There are no other tasks, or all the other tasks are in
|
||
|
|
the suspended state - make this the current task. */
|
||
|
|
pxCurrentTCB = pxNewTCB;
|
||
|
|
8003f8e: 4a2a ldr r2, [pc, #168] ; (8004038 <prvAddNewTaskToReadyList+0xc8>)
|
||
|
|
8003f90: 687b ldr r3, [r7, #4]
|
||
|
|
8003f92: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
|
||
|
|
8003f94: 4b27 ldr r3, [pc, #156] ; (8004034 <prvAddNewTaskToReadyList+0xc4>)
|
||
|
|
8003f96: 681b ldr r3, [r3, #0]
|
||
|
|
8003f98: 2b01 cmp r3, #1
|
||
|
|
8003f9a: d110 bne.n 8003fbe <prvAddNewTaskToReadyList+0x4e>
|
||
|
|
{
|
||
|
|
/* This is the first task to be created so do the preliminary
|
||
|
|
initialisation required. We will not recover if this call
|
||
|
|
fails, but we will report the failure. */
|
||
|
|
prvInitialiseTaskLists();
|
||
|
|
8003f9c: f000 fc30 bl 8004800 <prvInitialiseTaskLists>
|
||
|
|
8003fa0: e00d b.n 8003fbe <prvAddNewTaskToReadyList+0x4e>
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* If the scheduler is not already running, make this task the
|
||
|
|
current task if it is the highest priority task to be created
|
||
|
|
so far. */
|
||
|
|
if( xSchedulerRunning == pdFALSE )
|
||
|
|
8003fa2: 4b26 ldr r3, [pc, #152] ; (800403c <prvAddNewTaskToReadyList+0xcc>)
|
||
|
|
8003fa4: 681b ldr r3, [r3, #0]
|
||
|
|
8003fa6: 2b00 cmp r3, #0
|
||
|
|
8003fa8: d109 bne.n 8003fbe <prvAddNewTaskToReadyList+0x4e>
|
||
|
|
{
|
||
|
|
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
|
||
|
|
8003faa: 4b23 ldr r3, [pc, #140] ; (8004038 <prvAddNewTaskToReadyList+0xc8>)
|
||
|
|
8003fac: 681b ldr r3, [r3, #0]
|
||
|
|
8003fae: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8003fb0: 687b ldr r3, [r7, #4]
|
||
|
|
8003fb2: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
8003fb4: 429a cmp r2, r3
|
||
|
|
8003fb6: d802 bhi.n 8003fbe <prvAddNewTaskToReadyList+0x4e>
|
||
|
|
{
|
||
|
|
pxCurrentTCB = pxNewTCB;
|
||
|
|
8003fb8: 4a1f ldr r2, [pc, #124] ; (8004038 <prvAddNewTaskToReadyList+0xc8>)
|
||
|
|
8003fba: 687b ldr r3, [r7, #4]
|
||
|
|
8003fbc: 6013 str r3, [r2, #0]
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
uxTaskNumber++;
|
||
|
|
8003fbe: 4b20 ldr r3, [pc, #128] ; (8004040 <prvAddNewTaskToReadyList+0xd0>)
|
||
|
|
8003fc0: 681b ldr r3, [r3, #0]
|
||
|
|
8003fc2: 3301 adds r3, #1
|
||
|
|
8003fc4: 4a1e ldr r2, [pc, #120] ; (8004040 <prvAddNewTaskToReadyList+0xd0>)
|
||
|
|
8003fc6: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
||
|
|
{
|
||
|
|
/* Add a counter into the TCB for tracing only. */
|
||
|
|
pxNewTCB->uxTCBNumber = uxTaskNumber;
|
||
|
|
8003fc8: 4b1d ldr r3, [pc, #116] ; (8004040 <prvAddNewTaskToReadyList+0xd0>)
|
||
|
|
8003fca: 681a ldr r2, [r3, #0]
|
||
|
|
8003fcc: 687b ldr r3, [r7, #4]
|
||
|
|
8003fce: 645a str r2, [r3, #68] ; 0x44
|
||
|
|
}
|
||
|
|
#endif /* configUSE_TRACE_FACILITY */
|
||
|
|
traceTASK_CREATE( pxNewTCB );
|
||
|
|
|
||
|
|
prvAddTaskToReadyList( pxNewTCB );
|
||
|
|
8003fd0: 687b ldr r3, [r7, #4]
|
||
|
|
8003fd2: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8003fd4: 4b1b ldr r3, [pc, #108] ; (8004044 <prvAddNewTaskToReadyList+0xd4>)
|
||
|
|
8003fd6: 681b ldr r3, [r3, #0]
|
||
|
|
8003fd8: 429a cmp r2, r3
|
||
|
|
8003fda: d903 bls.n 8003fe4 <prvAddNewTaskToReadyList+0x74>
|
||
|
|
8003fdc: 687b ldr r3, [r7, #4]
|
||
|
|
8003fde: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
8003fe0: 4a18 ldr r2, [pc, #96] ; (8004044 <prvAddNewTaskToReadyList+0xd4>)
|
||
|
|
8003fe2: 6013 str r3, [r2, #0]
|
||
|
|
8003fe4: 687b ldr r3, [r7, #4]
|
||
|
|
8003fe6: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8003fe8: 4613 mov r3, r2
|
||
|
|
8003fea: 009b lsls r3, r3, #2
|
||
|
|
8003fec: 4413 add r3, r2
|
||
|
|
8003fee: 009b lsls r3, r3, #2
|
||
|
|
8003ff0: 4a15 ldr r2, [pc, #84] ; (8004048 <prvAddNewTaskToReadyList+0xd8>)
|
||
|
|
8003ff2: 441a add r2, r3
|
||
|
|
8003ff4: 687b ldr r3, [r7, #4]
|
||
|
|
8003ff6: 3304 adds r3, #4
|
||
|
|
8003ff8: 4619 mov r1, r3
|
||
|
|
8003ffa: 4610 mov r0, r2
|
||
|
|
8003ffc: f7ff f8fd bl 80031fa <vListInsertEnd>
|
||
|
|
|
||
|
|
portSETUP_TCB( pxNewTCB );
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
8004000: f001 fa48 bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
if( xSchedulerRunning != pdFALSE )
|
||
|
|
8004004: 4b0d ldr r3, [pc, #52] ; (800403c <prvAddNewTaskToReadyList+0xcc>)
|
||
|
|
8004006: 681b ldr r3, [r3, #0]
|
||
|
|
8004008: 2b00 cmp r3, #0
|
||
|
|
800400a: d00e beq.n 800402a <prvAddNewTaskToReadyList+0xba>
|
||
|
|
{
|
||
|
|
/* If the created task is of a higher priority than the current task
|
||
|
|
then it should run now. */
|
||
|
|
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
|
||
|
|
800400c: 4b0a ldr r3, [pc, #40] ; (8004038 <prvAddNewTaskToReadyList+0xc8>)
|
||
|
|
800400e: 681b ldr r3, [r3, #0]
|
||
|
|
8004010: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8004012: 687b ldr r3, [r7, #4]
|
||
|
|
8004014: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
8004016: 429a cmp r2, r3
|
||
|
|
8004018: d207 bcs.n 800402a <prvAddNewTaskToReadyList+0xba>
|
||
|
|
{
|
||
|
|
taskYIELD_IF_USING_PREEMPTION();
|
||
|
|
800401a: 4b0c ldr r3, [pc, #48] ; (800404c <prvAddNewTaskToReadyList+0xdc>)
|
||
|
|
800401c: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
8004020: 601a str r2, [r3, #0]
|
||
|
|
8004022: f3bf 8f4f dsb sy
|
||
|
|
8004026: f3bf 8f6f isb sy
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
800402a: bf00 nop
|
||
|
|
800402c: 3708 adds r7, #8
|
||
|
|
800402e: 46bd mov sp, r7
|
||
|
|
8004030: bd80 pop {r7, pc}
|
||
|
|
8004032: bf00 nop
|
||
|
|
8004034: 20003c9c .word 0x20003c9c
|
||
|
|
8004038: 200037c8 .word 0x200037c8
|
||
|
|
800403c: 20003ca8 .word 0x20003ca8
|
||
|
|
8004040: 20003cb8 .word 0x20003cb8
|
||
|
|
8004044: 20003ca4 .word 0x20003ca4
|
||
|
|
8004048: 200037cc .word 0x200037cc
|
||
|
|
800404c: e000ed04 .word 0xe000ed04
|
||
|
|
|
||
|
|
08004050 <vTaskDelay>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
#if ( INCLUDE_vTaskDelay == 1 )
|
||
|
|
|
||
|
|
void vTaskDelay( const TickType_t xTicksToDelay )
|
||
|
|
{
|
||
|
|
8004050: b580 push {r7, lr}
|
||
|
|
8004052: b084 sub sp, #16
|
||
|
|
8004054: af00 add r7, sp, #0
|
||
|
|
8004056: 6078 str r0, [r7, #4]
|
||
|
|
BaseType_t xAlreadyYielded = pdFALSE;
|
||
|
|
8004058: 2300 movs r3, #0
|
||
|
|
800405a: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
/* A delay time of zero just forces a reschedule. */
|
||
|
|
if( xTicksToDelay > ( TickType_t ) 0U )
|
||
|
|
800405c: 687b ldr r3, [r7, #4]
|
||
|
|
800405e: 2b00 cmp r3, #0
|
||
|
|
8004060: d017 beq.n 8004092 <vTaskDelay+0x42>
|
||
|
|
{
|
||
|
|
configASSERT( uxSchedulerSuspended == 0 );
|
||
|
|
8004062: 4b13 ldr r3, [pc, #76] ; (80040b0 <vTaskDelay+0x60>)
|
||
|
|
8004064: 681b ldr r3, [r3, #0]
|
||
|
|
8004066: 2b00 cmp r3, #0
|
||
|
|
8004068: d00a beq.n 8004080 <vTaskDelay+0x30>
|
||
|
|
__asm volatile
|
||
|
|
800406a: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
800406e: f383 8811 msr BASEPRI, r3
|
||
|
|
8004072: f3bf 8f6f isb sy
|
||
|
|
8004076: f3bf 8f4f dsb sy
|
||
|
|
800407a: 60bb str r3, [r7, #8]
|
||
|
|
}
|
||
|
|
800407c: bf00 nop
|
||
|
|
800407e: e7fe b.n 800407e <vTaskDelay+0x2e>
|
||
|
|
vTaskSuspendAll();
|
||
|
|
8004080: f000 f88a bl 8004198 <vTaskSuspendAll>
|
||
|
|
list or removed from the blocked list until the scheduler
|
||
|
|
is resumed.
|
||
|
|
|
||
|
|
This task cannot be in an event list as it is the currently
|
||
|
|
executing task. */
|
||
|
|
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
|
||
|
|
8004084: 2100 movs r1, #0
|
||
|
|
8004086: 6878 ldr r0, [r7, #4]
|
||
|
|
8004088: f000 fd08 bl 8004a9c <prvAddCurrentTaskToDelayedList>
|
||
|
|
}
|
||
|
|
xAlreadyYielded = xTaskResumeAll();
|
||
|
|
800408c: f000 f892 bl 80041b4 <xTaskResumeAll>
|
||
|
|
8004090: 60f8 str r0, [r7, #12]
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Force a reschedule if xTaskResumeAll has not already done so, we may
|
||
|
|
have put ourselves to sleep. */
|
||
|
|
if( xAlreadyYielded == pdFALSE )
|
||
|
|
8004092: 68fb ldr r3, [r7, #12]
|
||
|
|
8004094: 2b00 cmp r3, #0
|
||
|
|
8004096: d107 bne.n 80040a8 <vTaskDelay+0x58>
|
||
|
|
{
|
||
|
|
portYIELD_WITHIN_API();
|
||
|
|
8004098: 4b06 ldr r3, [pc, #24] ; (80040b4 <vTaskDelay+0x64>)
|
||
|
|
800409a: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
800409e: 601a str r2, [r3, #0]
|
||
|
|
80040a0: f3bf 8f4f dsb sy
|
||
|
|
80040a4: f3bf 8f6f isb sy
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
80040a8: bf00 nop
|
||
|
|
80040aa: 3710 adds r7, #16
|
||
|
|
80040ac: 46bd mov sp, r7
|
||
|
|
80040ae: bd80 pop {r7, pc}
|
||
|
|
80040b0: 20003cc4 .word 0x20003cc4
|
||
|
|
80040b4: e000ed04 .word 0xe000ed04
|
||
|
|
|
||
|
|
080040b8 <vTaskStartScheduler>:
|
||
|
|
|
||
|
|
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vTaskStartScheduler( void )
|
||
|
|
{
|
||
|
|
80040b8: b580 push {r7, lr}
|
||
|
|
80040ba: b08a sub sp, #40 ; 0x28
|
||
|
|
80040bc: af04 add r7, sp, #16
|
||
|
|
BaseType_t xReturn;
|
||
|
|
|
||
|
|
/* Add the idle task at the lowest priority. */
|
||
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
||
|
|
{
|
||
|
|
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
|
||
|
|
80040be: 2300 movs r3, #0
|
||
|
|
80040c0: 60bb str r3, [r7, #8]
|
||
|
|
StackType_t *pxIdleTaskStackBuffer = NULL;
|
||
|
|
80040c2: 2300 movs r3, #0
|
||
|
|
80040c4: 607b str r3, [r7, #4]
|
||
|
|
uint32_t ulIdleTaskStackSize;
|
||
|
|
|
||
|
|
/* The Idle task is created using user provided RAM - obtain the
|
||
|
|
address of the RAM then create the idle task. */
|
||
|
|
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
|
||
|
|
80040c6: 463a mov r2, r7
|
||
|
|
80040c8: 1d39 adds r1, r7, #4
|
||
|
|
80040ca: f107 0308 add.w r3, r7, #8
|
||
|
|
80040ce: 4618 mov r0, r3
|
||
|
|
80040d0: f7ff f832 bl 8003138 <vApplicationGetIdleTaskMemory>
|
||
|
|
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
|
||
|
|
80040d4: 6839 ldr r1, [r7, #0]
|
||
|
|
80040d6: 687b ldr r3, [r7, #4]
|
||
|
|
80040d8: 68ba ldr r2, [r7, #8]
|
||
|
|
80040da: 9202 str r2, [sp, #8]
|
||
|
|
80040dc: 9301 str r3, [sp, #4]
|
||
|
|
80040de: 2300 movs r3, #0
|
||
|
|
80040e0: 9300 str r3, [sp, #0]
|
||
|
|
80040e2: 2300 movs r3, #0
|
||
|
|
80040e4: 460a mov r2, r1
|
||
|
|
80040e6: 4924 ldr r1, [pc, #144] ; (8004178 <vTaskStartScheduler+0xc0>)
|
||
|
|
80040e8: 4824 ldr r0, [pc, #144] ; (800417c <vTaskStartScheduler+0xc4>)
|
||
|
|
80040ea: f7ff fdf9 bl 8003ce0 <xTaskCreateStatic>
|
||
|
|
80040ee: 4603 mov r3, r0
|
||
|
|
80040f0: 4a23 ldr r2, [pc, #140] ; (8004180 <vTaskStartScheduler+0xc8>)
|
||
|
|
80040f2: 6013 str r3, [r2, #0]
|
||
|
|
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
|
||
|
|
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
|
||
|
|
pxIdleTaskStackBuffer,
|
||
|
|
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
|
||
|
|
|
||
|
|
if( xIdleTaskHandle != NULL )
|
||
|
|
80040f4: 4b22 ldr r3, [pc, #136] ; (8004180 <vTaskStartScheduler+0xc8>)
|
||
|
|
80040f6: 681b ldr r3, [r3, #0]
|
||
|
|
80040f8: 2b00 cmp r3, #0
|
||
|
|
80040fa: d002 beq.n 8004102 <vTaskStartScheduler+0x4a>
|
||
|
|
{
|
||
|
|
xReturn = pdPASS;
|
||
|
|
80040fc: 2301 movs r3, #1
|
||
|
|
80040fe: 617b str r3, [r7, #20]
|
||
|
|
8004100: e001 b.n 8004106 <vTaskStartScheduler+0x4e>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
xReturn = pdFAIL;
|
||
|
|
8004102: 2300 movs r3, #0
|
||
|
|
8004104: 617b str r3, [r7, #20]
|
||
|
|
}
|
||
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
||
|
|
|
||
|
|
#if ( configUSE_TIMERS == 1 )
|
||
|
|
{
|
||
|
|
if( xReturn == pdPASS )
|
||
|
|
8004106: 697b ldr r3, [r7, #20]
|
||
|
|
8004108: 2b01 cmp r3, #1
|
||
|
|
800410a: d102 bne.n 8004112 <vTaskStartScheduler+0x5a>
|
||
|
|
{
|
||
|
|
xReturn = xTimerCreateTimerTask();
|
||
|
|
800410c: f000 fd1a bl 8004b44 <xTimerCreateTimerTask>
|
||
|
|
8004110: 6178 str r0, [r7, #20]
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* configUSE_TIMERS */
|
||
|
|
|
||
|
|
if( xReturn == pdPASS )
|
||
|
|
8004112: 697b ldr r3, [r7, #20]
|
||
|
|
8004114: 2b01 cmp r3, #1
|
||
|
|
8004116: d11b bne.n 8004150 <vTaskStartScheduler+0x98>
|
||
|
|
__asm volatile
|
||
|
|
8004118: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
800411c: f383 8811 msr BASEPRI, r3
|
||
|
|
8004120: f3bf 8f6f isb sy
|
||
|
|
8004124: f3bf 8f4f dsb sy
|
||
|
|
8004128: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
800412a: bf00 nop
|
||
|
|
{
|
||
|
|
/* Switch Newlib's _impure_ptr variable to point to the _reent
|
||
|
|
structure specific to the task that will run first.
|
||
|
|
See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
|
||
|
|
for additional information. */
|
||
|
|
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
|
||
|
|
800412c: 4b15 ldr r3, [pc, #84] ; (8004184 <vTaskStartScheduler+0xcc>)
|
||
|
|
800412e: 681b ldr r3, [r3, #0]
|
||
|
|
8004130: 3354 adds r3, #84 ; 0x54
|
||
|
|
8004132: 4a15 ldr r2, [pc, #84] ; (8004188 <vTaskStartScheduler+0xd0>)
|
||
|
|
8004134: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
#endif /* configUSE_NEWLIB_REENTRANT */
|
||
|
|
|
||
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
||
|
|
8004136: 4b15 ldr r3, [pc, #84] ; (800418c <vTaskStartScheduler+0xd4>)
|
||
|
|
8004138: f04f 32ff mov.w r2, #4294967295
|
||
|
|
800413c: 601a str r2, [r3, #0]
|
||
|
|
xSchedulerRunning = pdTRUE;
|
||
|
|
800413e: 4b14 ldr r3, [pc, #80] ; (8004190 <vTaskStartScheduler+0xd8>)
|
||
|
|
8004140: 2201 movs r2, #1
|
||
|
|
8004142: 601a str r2, [r3, #0]
|
||
|
|
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
|
||
|
|
8004144: 4b13 ldr r3, [pc, #76] ; (8004194 <vTaskStartScheduler+0xdc>)
|
||
|
|
8004146: 2200 movs r2, #0
|
||
|
|
8004148: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
traceTASK_SWITCHED_IN();
|
||
|
|
|
||
|
|
/* Setting up the timer tick is hardware specific and thus in the
|
||
|
|
portable interface. */
|
||
|
|
if( xPortStartScheduler() != pdFALSE )
|
||
|
|
800414a: f001 f8d1 bl 80052f0 <xPortStartScheduler>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
|
||
|
|
meaning xIdleTaskHandle is not used anywhere else. */
|
||
|
|
( void ) xIdleTaskHandle;
|
||
|
|
}
|
||
|
|
800414e: e00e b.n 800416e <vTaskStartScheduler+0xb6>
|
||
|
|
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
|
||
|
|
8004150: 697b ldr r3, [r7, #20]
|
||
|
|
8004152: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
8004156: d10a bne.n 800416e <vTaskStartScheduler+0xb6>
|
||
|
|
__asm volatile
|
||
|
|
8004158: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
800415c: f383 8811 msr BASEPRI, r3
|
||
|
|
8004160: f3bf 8f6f isb sy
|
||
|
|
8004164: f3bf 8f4f dsb sy
|
||
|
|
8004168: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
800416a: bf00 nop
|
||
|
|
800416c: e7fe b.n 800416c <vTaskStartScheduler+0xb4>
|
||
|
|
}
|
||
|
|
800416e: bf00 nop
|
||
|
|
8004170: 3718 adds r7, #24
|
||
|
|
8004172: 46bd mov sp, r7
|
||
|
|
8004174: bd80 pop {r7, pc}
|
||
|
|
8004176: bf00 nop
|
||
|
|
8004178: 08005cec .word 0x08005cec
|
||
|
|
800417c: 080047cd .word 0x080047cd
|
||
|
|
8004180: 20003cc0 .word 0x20003cc0
|
||
|
|
8004184: 200037c8 .word 0x200037c8
|
||
|
|
8004188: 20000020 .word 0x20000020
|
||
|
|
800418c: 20003cbc .word 0x20003cbc
|
||
|
|
8004190: 20003ca8 .word 0x20003ca8
|
||
|
|
8004194: 20003ca0 .word 0x20003ca0
|
||
|
|
|
||
|
|
08004198 <vTaskSuspendAll>:
|
||
|
|
vPortEndScheduler();
|
||
|
|
}
|
||
|
|
/*----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vTaskSuspendAll( void )
|
||
|
|
{
|
||
|
|
8004198: b480 push {r7}
|
||
|
|
800419a: af00 add r7, sp, #0
|
||
|
|
do not otherwise exhibit real time behaviour. */
|
||
|
|
portSOFTWARE_BARRIER();
|
||
|
|
|
||
|
|
/* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
|
||
|
|
is used to allow calls to vTaskSuspendAll() to nest. */
|
||
|
|
++uxSchedulerSuspended;
|
||
|
|
800419c: 4b04 ldr r3, [pc, #16] ; (80041b0 <vTaskSuspendAll+0x18>)
|
||
|
|
800419e: 681b ldr r3, [r3, #0]
|
||
|
|
80041a0: 3301 adds r3, #1
|
||
|
|
80041a2: 4a03 ldr r2, [pc, #12] ; (80041b0 <vTaskSuspendAll+0x18>)
|
||
|
|
80041a4: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Enforces ordering for ports and optimised compilers that may otherwise place
|
||
|
|
the above increment elsewhere. */
|
||
|
|
portMEMORY_BARRIER();
|
||
|
|
}
|
||
|
|
80041a6: bf00 nop
|
||
|
|
80041a8: 46bd mov sp, r7
|
||
|
|
80041aa: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80041ae: 4770 bx lr
|
||
|
|
80041b0: 20003cc4 .word 0x20003cc4
|
||
|
|
|
||
|
|
080041b4 <xTaskResumeAll>:
|
||
|
|
|
||
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
||
|
|
/*----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xTaskResumeAll( void )
|
||
|
|
{
|
||
|
|
80041b4: b580 push {r7, lr}
|
||
|
|
80041b6: b084 sub sp, #16
|
||
|
|
80041b8: af00 add r7, sp, #0
|
||
|
|
TCB_t *pxTCB = NULL;
|
||
|
|
80041ba: 2300 movs r3, #0
|
||
|
|
80041bc: 60fb str r3, [r7, #12]
|
||
|
|
BaseType_t xAlreadyYielded = pdFALSE;
|
||
|
|
80041be: 2300 movs r3, #0
|
||
|
|
80041c0: 60bb str r3, [r7, #8]
|
||
|
|
|
||
|
|
/* If uxSchedulerSuspended is zero then this function does not match a
|
||
|
|
previous call to vTaskSuspendAll(). */
|
||
|
|
configASSERT( uxSchedulerSuspended );
|
||
|
|
80041c2: 4b42 ldr r3, [pc, #264] ; (80042cc <xTaskResumeAll+0x118>)
|
||
|
|
80041c4: 681b ldr r3, [r3, #0]
|
||
|
|
80041c6: 2b00 cmp r3, #0
|
||
|
|
80041c8: d10a bne.n 80041e0 <xTaskResumeAll+0x2c>
|
||
|
|
__asm volatile
|
||
|
|
80041ca: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80041ce: f383 8811 msr BASEPRI, r3
|
||
|
|
80041d2: f3bf 8f6f isb sy
|
||
|
|
80041d6: f3bf 8f4f dsb sy
|
||
|
|
80041da: 603b str r3, [r7, #0]
|
||
|
|
}
|
||
|
|
80041dc: bf00 nop
|
||
|
|
80041de: e7fe b.n 80041de <xTaskResumeAll+0x2a>
|
||
|
|
/* It is possible that an ISR caused a task to be removed from an event
|
||
|
|
list while the scheduler was suspended. If this was the case then the
|
||
|
|
removed task will have been added to the xPendingReadyList. Once the
|
||
|
|
scheduler has been resumed it is safe to move all the pending ready
|
||
|
|
tasks from this list into their appropriate ready list. */
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
80041e0: f001 f928 bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
--uxSchedulerSuspended;
|
||
|
|
80041e4: 4b39 ldr r3, [pc, #228] ; (80042cc <xTaskResumeAll+0x118>)
|
||
|
|
80041e6: 681b ldr r3, [r3, #0]
|
||
|
|
80041e8: 3b01 subs r3, #1
|
||
|
|
80041ea: 4a38 ldr r2, [pc, #224] ; (80042cc <xTaskResumeAll+0x118>)
|
||
|
|
80041ec: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
||
|
|
80041ee: 4b37 ldr r3, [pc, #220] ; (80042cc <xTaskResumeAll+0x118>)
|
||
|
|
80041f0: 681b ldr r3, [r3, #0]
|
||
|
|
80041f2: 2b00 cmp r3, #0
|
||
|
|
80041f4: d162 bne.n 80042bc <xTaskResumeAll+0x108>
|
||
|
|
{
|
||
|
|
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
|
||
|
|
80041f6: 4b36 ldr r3, [pc, #216] ; (80042d0 <xTaskResumeAll+0x11c>)
|
||
|
|
80041f8: 681b ldr r3, [r3, #0]
|
||
|
|
80041fa: 2b00 cmp r3, #0
|
||
|
|
80041fc: d05e beq.n 80042bc <xTaskResumeAll+0x108>
|
||
|
|
{
|
||
|
|
/* Move any readied tasks from the pending list into the
|
||
|
|
appropriate ready list. */
|
||
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
||
|
|
80041fe: e02f b.n 8004260 <xTaskResumeAll+0xac>
|
||
|
|
{
|
||
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
||
|
|
8004200: 4b34 ldr r3, [pc, #208] ; (80042d4 <xTaskResumeAll+0x120>)
|
||
|
|
8004202: 68db ldr r3, [r3, #12]
|
||
|
|
8004204: 68db ldr r3, [r3, #12]
|
||
|
|
8004206: 60fb str r3, [r7, #12]
|
||
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
||
|
|
8004208: 68fb ldr r3, [r7, #12]
|
||
|
|
800420a: 3318 adds r3, #24
|
||
|
|
800420c: 4618 mov r0, r3
|
||
|
|
800420e: f7ff f851 bl 80032b4 <uxListRemove>
|
||
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
||
|
|
8004212: 68fb ldr r3, [r7, #12]
|
||
|
|
8004214: 3304 adds r3, #4
|
||
|
|
8004216: 4618 mov r0, r3
|
||
|
|
8004218: f7ff f84c bl 80032b4 <uxListRemove>
|
||
|
|
prvAddTaskToReadyList( pxTCB );
|
||
|
|
800421c: 68fb ldr r3, [r7, #12]
|
||
|
|
800421e: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8004220: 4b2d ldr r3, [pc, #180] ; (80042d8 <xTaskResumeAll+0x124>)
|
||
|
|
8004222: 681b ldr r3, [r3, #0]
|
||
|
|
8004224: 429a cmp r2, r3
|
||
|
|
8004226: d903 bls.n 8004230 <xTaskResumeAll+0x7c>
|
||
|
|
8004228: 68fb ldr r3, [r7, #12]
|
||
|
|
800422a: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
800422c: 4a2a ldr r2, [pc, #168] ; (80042d8 <xTaskResumeAll+0x124>)
|
||
|
|
800422e: 6013 str r3, [r2, #0]
|
||
|
|
8004230: 68fb ldr r3, [r7, #12]
|
||
|
|
8004232: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8004234: 4613 mov r3, r2
|
||
|
|
8004236: 009b lsls r3, r3, #2
|
||
|
|
8004238: 4413 add r3, r2
|
||
|
|
800423a: 009b lsls r3, r3, #2
|
||
|
|
800423c: 4a27 ldr r2, [pc, #156] ; (80042dc <xTaskResumeAll+0x128>)
|
||
|
|
800423e: 441a add r2, r3
|
||
|
|
8004240: 68fb ldr r3, [r7, #12]
|
||
|
|
8004242: 3304 adds r3, #4
|
||
|
|
8004244: 4619 mov r1, r3
|
||
|
|
8004246: 4610 mov r0, r2
|
||
|
|
8004248: f7fe ffd7 bl 80031fa <vListInsertEnd>
|
||
|
|
|
||
|
|
/* If the moved task has a priority higher than the current
|
||
|
|
task then a yield must be performed. */
|
||
|
|
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
|
||
|
|
800424c: 68fb ldr r3, [r7, #12]
|
||
|
|
800424e: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8004250: 4b23 ldr r3, [pc, #140] ; (80042e0 <xTaskResumeAll+0x12c>)
|
||
|
|
8004252: 681b ldr r3, [r3, #0]
|
||
|
|
8004254: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
8004256: 429a cmp r2, r3
|
||
|
|
8004258: d302 bcc.n 8004260 <xTaskResumeAll+0xac>
|
||
|
|
{
|
||
|
|
xYieldPending = pdTRUE;
|
||
|
|
800425a: 4b22 ldr r3, [pc, #136] ; (80042e4 <xTaskResumeAll+0x130>)
|
||
|
|
800425c: 2201 movs r2, #1
|
||
|
|
800425e: 601a str r2, [r3, #0]
|
||
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
||
|
|
8004260: 4b1c ldr r3, [pc, #112] ; (80042d4 <xTaskResumeAll+0x120>)
|
||
|
|
8004262: 681b ldr r3, [r3, #0]
|
||
|
|
8004264: 2b00 cmp r3, #0
|
||
|
|
8004266: d1cb bne.n 8004200 <xTaskResumeAll+0x4c>
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if( pxTCB != NULL )
|
||
|
|
8004268: 68fb ldr r3, [r7, #12]
|
||
|
|
800426a: 2b00 cmp r3, #0
|
||
|
|
800426c: d001 beq.n 8004272 <xTaskResumeAll+0xbe>
|
||
|
|
which may have prevented the next unblock time from being
|
||
|
|
re-calculated, in which case re-calculate it now. Mainly
|
||
|
|
important for low power tickless implementations, where
|
||
|
|
this can prevent an unnecessary exit from low power
|
||
|
|
state. */
|
||
|
|
prvResetNextTaskUnblockTime();
|
||
|
|
800426e: f000 fb69 bl 8004944 <prvResetNextTaskUnblockTime>
|
||
|
|
/* If any ticks occurred while the scheduler was suspended then
|
||
|
|
they should be processed now. This ensures the tick count does
|
||
|
|
not slip, and that any delayed tasks are resumed at the correct
|
||
|
|
time. */
|
||
|
|
{
|
||
|
|
TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
|
||
|
|
8004272: 4b1d ldr r3, [pc, #116] ; (80042e8 <xTaskResumeAll+0x134>)
|
||
|
|
8004274: 681b ldr r3, [r3, #0]
|
||
|
|
8004276: 607b str r3, [r7, #4]
|
||
|
|
|
||
|
|
if( xPendedCounts > ( TickType_t ) 0U )
|
||
|
|
8004278: 687b ldr r3, [r7, #4]
|
||
|
|
800427a: 2b00 cmp r3, #0
|
||
|
|
800427c: d010 beq.n 80042a0 <xTaskResumeAll+0xec>
|
||
|
|
{
|
||
|
|
do
|
||
|
|
{
|
||
|
|
if( xTaskIncrementTick() != pdFALSE )
|
||
|
|
800427e: f000 f847 bl 8004310 <xTaskIncrementTick>
|
||
|
|
8004282: 4603 mov r3, r0
|
||
|
|
8004284: 2b00 cmp r3, #0
|
||
|
|
8004286: d002 beq.n 800428e <xTaskResumeAll+0xda>
|
||
|
|
{
|
||
|
|
xYieldPending = pdTRUE;
|
||
|
|
8004288: 4b16 ldr r3, [pc, #88] ; (80042e4 <xTaskResumeAll+0x130>)
|
||
|
|
800428a: 2201 movs r2, #1
|
||
|
|
800428c: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
--xPendedCounts;
|
||
|
|
800428e: 687b ldr r3, [r7, #4]
|
||
|
|
8004290: 3b01 subs r3, #1
|
||
|
|
8004292: 607b str r3, [r7, #4]
|
||
|
|
} while( xPendedCounts > ( TickType_t ) 0U );
|
||
|
|
8004294: 687b ldr r3, [r7, #4]
|
||
|
|
8004296: 2b00 cmp r3, #0
|
||
|
|
8004298: d1f1 bne.n 800427e <xTaskResumeAll+0xca>
|
||
|
|
|
||
|
|
xPendedTicks = 0;
|
||
|
|
800429a: 4b13 ldr r3, [pc, #76] ; (80042e8 <xTaskResumeAll+0x134>)
|
||
|
|
800429c: 2200 movs r2, #0
|
||
|
|
800429e: 601a str r2, [r3, #0]
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if( xYieldPending != pdFALSE )
|
||
|
|
80042a0: 4b10 ldr r3, [pc, #64] ; (80042e4 <xTaskResumeAll+0x130>)
|
||
|
|
80042a2: 681b ldr r3, [r3, #0]
|
||
|
|
80042a4: 2b00 cmp r3, #0
|
||
|
|
80042a6: d009 beq.n 80042bc <xTaskResumeAll+0x108>
|
||
|
|
{
|
||
|
|
#if( configUSE_PREEMPTION != 0 )
|
||
|
|
{
|
||
|
|
xAlreadyYielded = pdTRUE;
|
||
|
|
80042a8: 2301 movs r3, #1
|
||
|
|
80042aa: 60bb str r3, [r7, #8]
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
taskYIELD_IF_USING_PREEMPTION();
|
||
|
|
80042ac: 4b0f ldr r3, [pc, #60] ; (80042ec <xTaskResumeAll+0x138>)
|
||
|
|
80042ae: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
80042b2: 601a str r2, [r3, #0]
|
||
|
|
80042b4: f3bf 8f4f dsb sy
|
||
|
|
80042b8: f3bf 8f6f isb sy
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
80042bc: f001 f8ea bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
return xAlreadyYielded;
|
||
|
|
80042c0: 68bb ldr r3, [r7, #8]
|
||
|
|
}
|
||
|
|
80042c2: 4618 mov r0, r3
|
||
|
|
80042c4: 3710 adds r7, #16
|
||
|
|
80042c6: 46bd mov sp, r7
|
||
|
|
80042c8: bd80 pop {r7, pc}
|
||
|
|
80042ca: bf00 nop
|
||
|
|
80042cc: 20003cc4 .word 0x20003cc4
|
||
|
|
80042d0: 20003c9c .word 0x20003c9c
|
||
|
|
80042d4: 20003c5c .word 0x20003c5c
|
||
|
|
80042d8: 20003ca4 .word 0x20003ca4
|
||
|
|
80042dc: 200037cc .word 0x200037cc
|
||
|
|
80042e0: 200037c8 .word 0x200037c8
|
||
|
|
80042e4: 20003cb0 .word 0x20003cb0
|
||
|
|
80042e8: 20003cac .word 0x20003cac
|
||
|
|
80042ec: e000ed04 .word 0xe000ed04
|
||
|
|
|
||
|
|
080042f0 <xTaskGetTickCount>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
TickType_t xTaskGetTickCount( void )
|
||
|
|
{
|
||
|
|
80042f0: b480 push {r7}
|
||
|
|
80042f2: b083 sub sp, #12
|
||
|
|
80042f4: af00 add r7, sp, #0
|
||
|
|
TickType_t xTicks;
|
||
|
|
|
||
|
|
/* Critical section required if running on a 16 bit processor. */
|
||
|
|
portTICK_TYPE_ENTER_CRITICAL();
|
||
|
|
{
|
||
|
|
xTicks = xTickCount;
|
||
|
|
80042f6: 4b05 ldr r3, [pc, #20] ; (800430c <xTaskGetTickCount+0x1c>)
|
||
|
|
80042f8: 681b ldr r3, [r3, #0]
|
||
|
|
80042fa: 607b str r3, [r7, #4]
|
||
|
|
}
|
||
|
|
portTICK_TYPE_EXIT_CRITICAL();
|
||
|
|
|
||
|
|
return xTicks;
|
||
|
|
80042fc: 687b ldr r3, [r7, #4]
|
||
|
|
}
|
||
|
|
80042fe: 4618 mov r0, r3
|
||
|
|
8004300: 370c adds r7, #12
|
||
|
|
8004302: 46bd mov sp, r7
|
||
|
|
8004304: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8004308: 4770 bx lr
|
||
|
|
800430a: bf00 nop
|
||
|
|
800430c: 20003ca0 .word 0x20003ca0
|
||
|
|
|
||
|
|
08004310 <xTaskIncrementTick>:
|
||
|
|
|
||
|
|
#endif /* INCLUDE_xTaskAbortDelay */
|
||
|
|
/*----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xTaskIncrementTick( void )
|
||
|
|
{
|
||
|
|
8004310: b580 push {r7, lr}
|
||
|
|
8004312: b086 sub sp, #24
|
||
|
|
8004314: af00 add r7, sp, #0
|
||
|
|
TCB_t * pxTCB;
|
||
|
|
TickType_t xItemValue;
|
||
|
|
BaseType_t xSwitchRequired = pdFALSE;
|
||
|
|
8004316: 2300 movs r3, #0
|
||
|
|
8004318: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Called by the portable layer each time a tick interrupt occurs.
|
||
|
|
Increments the tick then checks to see if the new tick value will cause any
|
||
|
|
tasks to be unblocked. */
|
||
|
|
traceTASK_INCREMENT_TICK( xTickCount );
|
||
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
||
|
|
800431a: 4b53 ldr r3, [pc, #332] ; (8004468 <xTaskIncrementTick+0x158>)
|
||
|
|
800431c: 681b ldr r3, [r3, #0]
|
||
|
|
800431e: 2b00 cmp r3, #0
|
||
|
|
8004320: f040 8095 bne.w 800444e <xTaskIncrementTick+0x13e>
|
||
|
|
{
|
||
|
|
/* Minor optimisation. The tick count cannot change in this
|
||
|
|
block. */
|
||
|
|
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
|
||
|
|
8004324: 4b51 ldr r3, [pc, #324] ; (800446c <xTaskIncrementTick+0x15c>)
|
||
|
|
8004326: 681b ldr r3, [r3, #0]
|
||
|
|
8004328: 3301 adds r3, #1
|
||
|
|
800432a: 613b str r3, [r7, #16]
|
||
|
|
|
||
|
|
/* Increment the RTOS tick, switching the delayed and overflowed
|
||
|
|
delayed lists if it wraps to 0. */
|
||
|
|
xTickCount = xConstTickCount;
|
||
|
|
800432c: 4a4f ldr r2, [pc, #316] ; (800446c <xTaskIncrementTick+0x15c>)
|
||
|
|
800432e: 693b ldr r3, [r7, #16]
|
||
|
|
8004330: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
|
||
|
|
8004332: 693b ldr r3, [r7, #16]
|
||
|
|
8004334: 2b00 cmp r3, #0
|
||
|
|
8004336: d120 bne.n 800437a <xTaskIncrementTick+0x6a>
|
||
|
|
{
|
||
|
|
taskSWITCH_DELAYED_LISTS();
|
||
|
|
8004338: 4b4d ldr r3, [pc, #308] ; (8004470 <xTaskIncrementTick+0x160>)
|
||
|
|
800433a: 681b ldr r3, [r3, #0]
|
||
|
|
800433c: 681b ldr r3, [r3, #0]
|
||
|
|
800433e: 2b00 cmp r3, #0
|
||
|
|
8004340: d00a beq.n 8004358 <xTaskIncrementTick+0x48>
|
||
|
|
__asm volatile
|
||
|
|
8004342: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004346: f383 8811 msr BASEPRI, r3
|
||
|
|
800434a: f3bf 8f6f isb sy
|
||
|
|
800434e: f3bf 8f4f dsb sy
|
||
|
|
8004352: 603b str r3, [r7, #0]
|
||
|
|
}
|
||
|
|
8004354: bf00 nop
|
||
|
|
8004356: e7fe b.n 8004356 <xTaskIncrementTick+0x46>
|
||
|
|
8004358: 4b45 ldr r3, [pc, #276] ; (8004470 <xTaskIncrementTick+0x160>)
|
||
|
|
800435a: 681b ldr r3, [r3, #0]
|
||
|
|
800435c: 60fb str r3, [r7, #12]
|
||
|
|
800435e: 4b45 ldr r3, [pc, #276] ; (8004474 <xTaskIncrementTick+0x164>)
|
||
|
|
8004360: 681b ldr r3, [r3, #0]
|
||
|
|
8004362: 4a43 ldr r2, [pc, #268] ; (8004470 <xTaskIncrementTick+0x160>)
|
||
|
|
8004364: 6013 str r3, [r2, #0]
|
||
|
|
8004366: 4a43 ldr r2, [pc, #268] ; (8004474 <xTaskIncrementTick+0x164>)
|
||
|
|
8004368: 68fb ldr r3, [r7, #12]
|
||
|
|
800436a: 6013 str r3, [r2, #0]
|
||
|
|
800436c: 4b42 ldr r3, [pc, #264] ; (8004478 <xTaskIncrementTick+0x168>)
|
||
|
|
800436e: 681b ldr r3, [r3, #0]
|
||
|
|
8004370: 3301 adds r3, #1
|
||
|
|
8004372: 4a41 ldr r2, [pc, #260] ; (8004478 <xTaskIncrementTick+0x168>)
|
||
|
|
8004374: 6013 str r3, [r2, #0]
|
||
|
|
8004376: f000 fae5 bl 8004944 <prvResetNextTaskUnblockTime>
|
||
|
|
|
||
|
|
/* See if this tick has made a timeout expire. Tasks are stored in
|
||
|
|
the queue in the order of their wake time - meaning once one task
|
||
|
|
has been found whose block time has not expired there is no need to
|
||
|
|
look any further down the list. */
|
||
|
|
if( xConstTickCount >= xNextTaskUnblockTime )
|
||
|
|
800437a: 4b40 ldr r3, [pc, #256] ; (800447c <xTaskIncrementTick+0x16c>)
|
||
|
|
800437c: 681b ldr r3, [r3, #0]
|
||
|
|
800437e: 693a ldr r2, [r7, #16]
|
||
|
|
8004380: 429a cmp r2, r3
|
||
|
|
8004382: d349 bcc.n 8004418 <xTaskIncrementTick+0x108>
|
||
|
|
{
|
||
|
|
for( ;; )
|
||
|
|
{
|
||
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
||
|
|
8004384: 4b3a ldr r3, [pc, #232] ; (8004470 <xTaskIncrementTick+0x160>)
|
||
|
|
8004386: 681b ldr r3, [r3, #0]
|
||
|
|
8004388: 681b ldr r3, [r3, #0]
|
||
|
|
800438a: 2b00 cmp r3, #0
|
||
|
|
800438c: d104 bne.n 8004398 <xTaskIncrementTick+0x88>
|
||
|
|
/* The delayed list is empty. Set xNextTaskUnblockTime
|
||
|
|
to the maximum possible value so it is extremely
|
||
|
|
unlikely that the
|
||
|
|
if( xTickCount >= xNextTaskUnblockTime ) test will pass
|
||
|
|
next time through. */
|
||
|
|
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
||
|
|
800438e: 4b3b ldr r3, [pc, #236] ; (800447c <xTaskIncrementTick+0x16c>)
|
||
|
|
8004390: f04f 32ff mov.w r2, #4294967295
|
||
|
|
8004394: 601a str r2, [r3, #0]
|
||
|
|
break;
|
||
|
|
8004396: e03f b.n 8004418 <xTaskIncrementTick+0x108>
|
||
|
|
{
|
||
|
|
/* The delayed list is not empty, get the value of the
|
||
|
|
item at the head of the delayed list. This is the time
|
||
|
|
at which the task at the head of the delayed list must
|
||
|
|
be removed from the Blocked state. */
|
||
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
||
|
|
8004398: 4b35 ldr r3, [pc, #212] ; (8004470 <xTaskIncrementTick+0x160>)
|
||
|
|
800439a: 681b ldr r3, [r3, #0]
|
||
|
|
800439c: 68db ldr r3, [r3, #12]
|
||
|
|
800439e: 68db ldr r3, [r3, #12]
|
||
|
|
80043a0: 60bb str r3, [r7, #8]
|
||
|
|
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
|
||
|
|
80043a2: 68bb ldr r3, [r7, #8]
|
||
|
|
80043a4: 685b ldr r3, [r3, #4]
|
||
|
|
80043a6: 607b str r3, [r7, #4]
|
||
|
|
|
||
|
|
if( xConstTickCount < xItemValue )
|
||
|
|
80043a8: 693a ldr r2, [r7, #16]
|
||
|
|
80043aa: 687b ldr r3, [r7, #4]
|
||
|
|
80043ac: 429a cmp r2, r3
|
||
|
|
80043ae: d203 bcs.n 80043b8 <xTaskIncrementTick+0xa8>
|
||
|
|
/* It is not time to unblock this item yet, but the
|
||
|
|
item value is the time at which the task at the head
|
||
|
|
of the blocked list must be removed from the Blocked
|
||
|
|
state - so record the item value in
|
||
|
|
xNextTaskUnblockTime. */
|
||
|
|
xNextTaskUnblockTime = xItemValue;
|
||
|
|
80043b0: 4a32 ldr r2, [pc, #200] ; (800447c <xTaskIncrementTick+0x16c>)
|
||
|
|
80043b2: 687b ldr r3, [r7, #4]
|
||
|
|
80043b4: 6013 str r3, [r2, #0]
|
||
|
|
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
|
||
|
|
80043b6: e02f b.n 8004418 <xTaskIncrementTick+0x108>
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* It is time to remove the item from the Blocked state. */
|
||
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
||
|
|
80043b8: 68bb ldr r3, [r7, #8]
|
||
|
|
80043ba: 3304 adds r3, #4
|
||
|
|
80043bc: 4618 mov r0, r3
|
||
|
|
80043be: f7fe ff79 bl 80032b4 <uxListRemove>
|
||
|
|
|
||
|
|
/* Is the task waiting on an event also? If so remove
|
||
|
|
it from the event list. */
|
||
|
|
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
|
||
|
|
80043c2: 68bb ldr r3, [r7, #8]
|
||
|
|
80043c4: 6a9b ldr r3, [r3, #40] ; 0x28
|
||
|
|
80043c6: 2b00 cmp r3, #0
|
||
|
|
80043c8: d004 beq.n 80043d4 <xTaskIncrementTick+0xc4>
|
||
|
|
{
|
||
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
||
|
|
80043ca: 68bb ldr r3, [r7, #8]
|
||
|
|
80043cc: 3318 adds r3, #24
|
||
|
|
80043ce: 4618 mov r0, r3
|
||
|
|
80043d0: f7fe ff70 bl 80032b4 <uxListRemove>
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Place the unblocked task into the appropriate ready
|
||
|
|
list. */
|
||
|
|
prvAddTaskToReadyList( pxTCB );
|
||
|
|
80043d4: 68bb ldr r3, [r7, #8]
|
||
|
|
80043d6: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
80043d8: 4b29 ldr r3, [pc, #164] ; (8004480 <xTaskIncrementTick+0x170>)
|
||
|
|
80043da: 681b ldr r3, [r3, #0]
|
||
|
|
80043dc: 429a cmp r2, r3
|
||
|
|
80043de: d903 bls.n 80043e8 <xTaskIncrementTick+0xd8>
|
||
|
|
80043e0: 68bb ldr r3, [r7, #8]
|
||
|
|
80043e2: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
80043e4: 4a26 ldr r2, [pc, #152] ; (8004480 <xTaskIncrementTick+0x170>)
|
||
|
|
80043e6: 6013 str r3, [r2, #0]
|
||
|
|
80043e8: 68bb ldr r3, [r7, #8]
|
||
|
|
80043ea: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
80043ec: 4613 mov r3, r2
|
||
|
|
80043ee: 009b lsls r3, r3, #2
|
||
|
|
80043f0: 4413 add r3, r2
|
||
|
|
80043f2: 009b lsls r3, r3, #2
|
||
|
|
80043f4: 4a23 ldr r2, [pc, #140] ; (8004484 <xTaskIncrementTick+0x174>)
|
||
|
|
80043f6: 441a add r2, r3
|
||
|
|
80043f8: 68bb ldr r3, [r7, #8]
|
||
|
|
80043fa: 3304 adds r3, #4
|
||
|
|
80043fc: 4619 mov r1, r3
|
||
|
|
80043fe: 4610 mov r0, r2
|
||
|
|
8004400: f7fe fefb bl 80031fa <vListInsertEnd>
|
||
|
|
{
|
||
|
|
/* Preemption is on, but a context switch should
|
||
|
|
only be performed if the unblocked task has a
|
||
|
|
priority that is equal to or higher than the
|
||
|
|
currently executing task. */
|
||
|
|
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
|
||
|
|
8004404: 68bb ldr r3, [r7, #8]
|
||
|
|
8004406: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8004408: 4b1f ldr r3, [pc, #124] ; (8004488 <xTaskIncrementTick+0x178>)
|
||
|
|
800440a: 681b ldr r3, [r3, #0]
|
||
|
|
800440c: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
800440e: 429a cmp r2, r3
|
||
|
|
8004410: d3b8 bcc.n 8004384 <xTaskIncrementTick+0x74>
|
||
|
|
{
|
||
|
|
xSwitchRequired = pdTRUE;
|
||
|
|
8004412: 2301 movs r3, #1
|
||
|
|
8004414: 617b str r3, [r7, #20]
|
||
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
||
|
|
8004416: e7b5 b.n 8004384 <xTaskIncrementTick+0x74>
|
||
|
|
/* Tasks of equal priority to the currently running task will share
|
||
|
|
processing time (time slice) if preemption is on, and the application
|
||
|
|
writer has not explicitly turned time slicing off. */
|
||
|
|
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
|
||
|
|
{
|
||
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
|
||
|
|
8004418: 4b1b ldr r3, [pc, #108] ; (8004488 <xTaskIncrementTick+0x178>)
|
||
|
|
800441a: 681b ldr r3, [r3, #0]
|
||
|
|
800441c: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
800441e: 4919 ldr r1, [pc, #100] ; (8004484 <xTaskIncrementTick+0x174>)
|
||
|
|
8004420: 4613 mov r3, r2
|
||
|
|
8004422: 009b lsls r3, r3, #2
|
||
|
|
8004424: 4413 add r3, r2
|
||
|
|
8004426: 009b lsls r3, r3, #2
|
||
|
|
8004428: 440b add r3, r1
|
||
|
|
800442a: 681b ldr r3, [r3, #0]
|
||
|
|
800442c: 2b01 cmp r3, #1
|
||
|
|
800442e: d901 bls.n 8004434 <xTaskIncrementTick+0x124>
|
||
|
|
{
|
||
|
|
xSwitchRequired = pdTRUE;
|
||
|
|
8004430: 2301 movs r3, #1
|
||
|
|
8004432: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
#if ( configUSE_TICK_HOOK == 1 )
|
||
|
|
{
|
||
|
|
/* Guard against the tick hook being called when the pended tick
|
||
|
|
count is being unwound (when the scheduler is being unlocked). */
|
||
|
|
if( xPendedTicks == ( TickType_t ) 0 )
|
||
|
|
8004434: 4b15 ldr r3, [pc, #84] ; (800448c <xTaskIncrementTick+0x17c>)
|
||
|
|
8004436: 681b ldr r3, [r3, #0]
|
||
|
|
8004438: 2b00 cmp r3, #0
|
||
|
|
800443a: d101 bne.n 8004440 <xTaskIncrementTick+0x130>
|
||
|
|
{
|
||
|
|
vApplicationTickHook();
|
||
|
|
800443c: f7fc f851 bl 80004e2 <vApplicationTickHook>
|
||
|
|
}
|
||
|
|
#endif /* configUSE_TICK_HOOK */
|
||
|
|
|
||
|
|
#if ( configUSE_PREEMPTION == 1 )
|
||
|
|
{
|
||
|
|
if( xYieldPending != pdFALSE )
|
||
|
|
8004440: 4b13 ldr r3, [pc, #76] ; (8004490 <xTaskIncrementTick+0x180>)
|
||
|
|
8004442: 681b ldr r3, [r3, #0]
|
||
|
|
8004444: 2b00 cmp r3, #0
|
||
|
|
8004446: d009 beq.n 800445c <xTaskIncrementTick+0x14c>
|
||
|
|
{
|
||
|
|
xSwitchRequired = pdTRUE;
|
||
|
|
8004448: 2301 movs r3, #1
|
||
|
|
800444a: 617b str r3, [r7, #20]
|
||
|
|
800444c: e006 b.n 800445c <xTaskIncrementTick+0x14c>
|
||
|
|
}
|
||
|
|
#endif /* configUSE_PREEMPTION */
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
++xPendedTicks;
|
||
|
|
800444e: 4b0f ldr r3, [pc, #60] ; (800448c <xTaskIncrementTick+0x17c>)
|
||
|
|
8004450: 681b ldr r3, [r3, #0]
|
||
|
|
8004452: 3301 adds r3, #1
|
||
|
|
8004454: 4a0d ldr r2, [pc, #52] ; (800448c <xTaskIncrementTick+0x17c>)
|
||
|
|
8004456: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* The tick hook gets called at regular intervals, even if the
|
||
|
|
scheduler is locked. */
|
||
|
|
#if ( configUSE_TICK_HOOK == 1 )
|
||
|
|
{
|
||
|
|
vApplicationTickHook();
|
||
|
|
8004458: f7fc f843 bl 80004e2 <vApplicationTickHook>
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
return xSwitchRequired;
|
||
|
|
800445c: 697b ldr r3, [r7, #20]
|
||
|
|
}
|
||
|
|
800445e: 4618 mov r0, r3
|
||
|
|
8004460: 3718 adds r7, #24
|
||
|
|
8004462: 46bd mov sp, r7
|
||
|
|
8004464: bd80 pop {r7, pc}
|
||
|
|
8004466: bf00 nop
|
||
|
|
8004468: 20003cc4 .word 0x20003cc4
|
||
|
|
800446c: 20003ca0 .word 0x20003ca0
|
||
|
|
8004470: 20003c54 .word 0x20003c54
|
||
|
|
8004474: 20003c58 .word 0x20003c58
|
||
|
|
8004478: 20003cb4 .word 0x20003cb4
|
||
|
|
800447c: 20003cbc .word 0x20003cbc
|
||
|
|
8004480: 20003ca4 .word 0x20003ca4
|
||
|
|
8004484: 200037cc .word 0x200037cc
|
||
|
|
8004488: 200037c8 .word 0x200037c8
|
||
|
|
800448c: 20003cac .word 0x20003cac
|
||
|
|
8004490: 20003cb0 .word 0x20003cb0
|
||
|
|
|
||
|
|
08004494 <vTaskSwitchContext>:
|
||
|
|
|
||
|
|
#endif /* configUSE_APPLICATION_TASK_TAG */
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vTaskSwitchContext( void )
|
||
|
|
{
|
||
|
|
8004494: b480 push {r7}
|
||
|
|
8004496: b085 sub sp, #20
|
||
|
|
8004498: af00 add r7, sp, #0
|
||
|
|
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
|
||
|
|
800449a: 4b2a ldr r3, [pc, #168] ; (8004544 <vTaskSwitchContext+0xb0>)
|
||
|
|
800449c: 681b ldr r3, [r3, #0]
|
||
|
|
800449e: 2b00 cmp r3, #0
|
||
|
|
80044a0: d003 beq.n 80044aa <vTaskSwitchContext+0x16>
|
||
|
|
{
|
||
|
|
/* The scheduler is currently suspended - do not allow a context
|
||
|
|
switch. */
|
||
|
|
xYieldPending = pdTRUE;
|
||
|
|
80044a2: 4b29 ldr r3, [pc, #164] ; (8004548 <vTaskSwitchContext+0xb4>)
|
||
|
|
80044a4: 2201 movs r2, #1
|
||
|
|
80044a6: 601a str r2, [r3, #0]
|
||
|
|
for additional information. */
|
||
|
|
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
|
||
|
|
}
|
||
|
|
#endif /* configUSE_NEWLIB_REENTRANT */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
80044a8: e046 b.n 8004538 <vTaskSwitchContext+0xa4>
|
||
|
|
xYieldPending = pdFALSE;
|
||
|
|
80044aa: 4b27 ldr r3, [pc, #156] ; (8004548 <vTaskSwitchContext+0xb4>)
|
||
|
|
80044ac: 2200 movs r2, #0
|
||
|
|
80044ae: 601a str r2, [r3, #0]
|
||
|
|
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
||
|
|
80044b0: 4b26 ldr r3, [pc, #152] ; (800454c <vTaskSwitchContext+0xb8>)
|
||
|
|
80044b2: 681b ldr r3, [r3, #0]
|
||
|
|
80044b4: 60fb str r3, [r7, #12]
|
||
|
|
80044b6: e010 b.n 80044da <vTaskSwitchContext+0x46>
|
||
|
|
80044b8: 68fb ldr r3, [r7, #12]
|
||
|
|
80044ba: 2b00 cmp r3, #0
|
||
|
|
80044bc: d10a bne.n 80044d4 <vTaskSwitchContext+0x40>
|
||
|
|
__asm volatile
|
||
|
|
80044be: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80044c2: f383 8811 msr BASEPRI, r3
|
||
|
|
80044c6: f3bf 8f6f isb sy
|
||
|
|
80044ca: f3bf 8f4f dsb sy
|
||
|
|
80044ce: 607b str r3, [r7, #4]
|
||
|
|
}
|
||
|
|
80044d0: bf00 nop
|
||
|
|
80044d2: e7fe b.n 80044d2 <vTaskSwitchContext+0x3e>
|
||
|
|
80044d4: 68fb ldr r3, [r7, #12]
|
||
|
|
80044d6: 3b01 subs r3, #1
|
||
|
|
80044d8: 60fb str r3, [r7, #12]
|
||
|
|
80044da: 491d ldr r1, [pc, #116] ; (8004550 <vTaskSwitchContext+0xbc>)
|
||
|
|
80044dc: 68fa ldr r2, [r7, #12]
|
||
|
|
80044de: 4613 mov r3, r2
|
||
|
|
80044e0: 009b lsls r3, r3, #2
|
||
|
|
80044e2: 4413 add r3, r2
|
||
|
|
80044e4: 009b lsls r3, r3, #2
|
||
|
|
80044e6: 440b add r3, r1
|
||
|
|
80044e8: 681b ldr r3, [r3, #0]
|
||
|
|
80044ea: 2b00 cmp r3, #0
|
||
|
|
80044ec: d0e4 beq.n 80044b8 <vTaskSwitchContext+0x24>
|
||
|
|
80044ee: 68fa ldr r2, [r7, #12]
|
||
|
|
80044f0: 4613 mov r3, r2
|
||
|
|
80044f2: 009b lsls r3, r3, #2
|
||
|
|
80044f4: 4413 add r3, r2
|
||
|
|
80044f6: 009b lsls r3, r3, #2
|
||
|
|
80044f8: 4a15 ldr r2, [pc, #84] ; (8004550 <vTaskSwitchContext+0xbc>)
|
||
|
|
80044fa: 4413 add r3, r2
|
||
|
|
80044fc: 60bb str r3, [r7, #8]
|
||
|
|
80044fe: 68bb ldr r3, [r7, #8]
|
||
|
|
8004500: 685b ldr r3, [r3, #4]
|
||
|
|
8004502: 685a ldr r2, [r3, #4]
|
||
|
|
8004504: 68bb ldr r3, [r7, #8]
|
||
|
|
8004506: 605a str r2, [r3, #4]
|
||
|
|
8004508: 68bb ldr r3, [r7, #8]
|
||
|
|
800450a: 685a ldr r2, [r3, #4]
|
||
|
|
800450c: 68bb ldr r3, [r7, #8]
|
||
|
|
800450e: 3308 adds r3, #8
|
||
|
|
8004510: 429a cmp r2, r3
|
||
|
|
8004512: d104 bne.n 800451e <vTaskSwitchContext+0x8a>
|
||
|
|
8004514: 68bb ldr r3, [r7, #8]
|
||
|
|
8004516: 685b ldr r3, [r3, #4]
|
||
|
|
8004518: 685a ldr r2, [r3, #4]
|
||
|
|
800451a: 68bb ldr r3, [r7, #8]
|
||
|
|
800451c: 605a str r2, [r3, #4]
|
||
|
|
800451e: 68bb ldr r3, [r7, #8]
|
||
|
|
8004520: 685b ldr r3, [r3, #4]
|
||
|
|
8004522: 68db ldr r3, [r3, #12]
|
||
|
|
8004524: 4a0b ldr r2, [pc, #44] ; (8004554 <vTaskSwitchContext+0xc0>)
|
||
|
|
8004526: 6013 str r3, [r2, #0]
|
||
|
|
8004528: 4a08 ldr r2, [pc, #32] ; (800454c <vTaskSwitchContext+0xb8>)
|
||
|
|
800452a: 68fb ldr r3, [r7, #12]
|
||
|
|
800452c: 6013 str r3, [r2, #0]
|
||
|
|
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
|
||
|
|
800452e: 4b09 ldr r3, [pc, #36] ; (8004554 <vTaskSwitchContext+0xc0>)
|
||
|
|
8004530: 681b ldr r3, [r3, #0]
|
||
|
|
8004532: 3354 adds r3, #84 ; 0x54
|
||
|
|
8004534: 4a08 ldr r2, [pc, #32] ; (8004558 <vTaskSwitchContext+0xc4>)
|
||
|
|
8004536: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
8004538: bf00 nop
|
||
|
|
800453a: 3714 adds r7, #20
|
||
|
|
800453c: 46bd mov sp, r7
|
||
|
|
800453e: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8004542: 4770 bx lr
|
||
|
|
8004544: 20003cc4 .word 0x20003cc4
|
||
|
|
8004548: 20003cb0 .word 0x20003cb0
|
||
|
|
800454c: 20003ca4 .word 0x20003ca4
|
||
|
|
8004550: 200037cc .word 0x200037cc
|
||
|
|
8004554: 200037c8 .word 0x200037c8
|
||
|
|
8004558: 20000020 .word 0x20000020
|
||
|
|
|
||
|
|
0800455c <vTaskPlaceOnEventList>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
|
||
|
|
{
|
||
|
|
800455c: b580 push {r7, lr}
|
||
|
|
800455e: b084 sub sp, #16
|
||
|
|
8004560: af00 add r7, sp, #0
|
||
|
|
8004562: 6078 str r0, [r7, #4]
|
||
|
|
8004564: 6039 str r1, [r7, #0]
|
||
|
|
configASSERT( pxEventList );
|
||
|
|
8004566: 687b ldr r3, [r7, #4]
|
||
|
|
8004568: 2b00 cmp r3, #0
|
||
|
|
800456a: d10a bne.n 8004582 <vTaskPlaceOnEventList+0x26>
|
||
|
|
__asm volatile
|
||
|
|
800456c: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004570: f383 8811 msr BASEPRI, r3
|
||
|
|
8004574: f3bf 8f6f isb sy
|
||
|
|
8004578: f3bf 8f4f dsb sy
|
||
|
|
800457c: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
800457e: bf00 nop
|
||
|
|
8004580: e7fe b.n 8004580 <vTaskPlaceOnEventList+0x24>
|
||
|
|
|
||
|
|
/* Place the event list item of the TCB in the appropriate event list.
|
||
|
|
This is placed in the list in priority order so the highest priority task
|
||
|
|
is the first to be woken by the event. The queue that contains the event
|
||
|
|
list is locked, preventing simultaneous access from interrupts. */
|
||
|
|
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
|
||
|
|
8004582: 4b07 ldr r3, [pc, #28] ; (80045a0 <vTaskPlaceOnEventList+0x44>)
|
||
|
|
8004584: 681b ldr r3, [r3, #0]
|
||
|
|
8004586: 3318 adds r3, #24
|
||
|
|
8004588: 4619 mov r1, r3
|
||
|
|
800458a: 6878 ldr r0, [r7, #4]
|
||
|
|
800458c: f7fe fe59 bl 8003242 <vListInsert>
|
||
|
|
|
||
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
|
||
|
|
8004590: 2101 movs r1, #1
|
||
|
|
8004592: 6838 ldr r0, [r7, #0]
|
||
|
|
8004594: f000 fa82 bl 8004a9c <prvAddCurrentTaskToDelayedList>
|
||
|
|
}
|
||
|
|
8004598: bf00 nop
|
||
|
|
800459a: 3710 adds r7, #16
|
||
|
|
800459c: 46bd mov sp, r7
|
||
|
|
800459e: bd80 pop {r7, pc}
|
||
|
|
80045a0: 200037c8 .word 0x200037c8
|
||
|
|
|
||
|
|
080045a4 <vTaskPlaceOnEventListRestricted>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
#if( configUSE_TIMERS == 1 )
|
||
|
|
|
||
|
|
void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
|
||
|
|
{
|
||
|
|
80045a4: b580 push {r7, lr}
|
||
|
|
80045a6: b086 sub sp, #24
|
||
|
|
80045a8: af00 add r7, sp, #0
|
||
|
|
80045aa: 60f8 str r0, [r7, #12]
|
||
|
|
80045ac: 60b9 str r1, [r7, #8]
|
||
|
|
80045ae: 607a str r2, [r7, #4]
|
||
|
|
configASSERT( pxEventList );
|
||
|
|
80045b0: 68fb ldr r3, [r7, #12]
|
||
|
|
80045b2: 2b00 cmp r3, #0
|
||
|
|
80045b4: d10a bne.n 80045cc <vTaskPlaceOnEventListRestricted+0x28>
|
||
|
|
__asm volatile
|
||
|
|
80045b6: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80045ba: f383 8811 msr BASEPRI, r3
|
||
|
|
80045be: f3bf 8f6f isb sy
|
||
|
|
80045c2: f3bf 8f4f dsb sy
|
||
|
|
80045c6: 617b str r3, [r7, #20]
|
||
|
|
}
|
||
|
|
80045c8: bf00 nop
|
||
|
|
80045ca: e7fe b.n 80045ca <vTaskPlaceOnEventListRestricted+0x26>
|
||
|
|
|
||
|
|
/* Place the event list item of the TCB in the appropriate event list.
|
||
|
|
In this case it is assume that this is the only task that is going to
|
||
|
|
be waiting on this event list, so the faster vListInsertEnd() function
|
||
|
|
can be used in place of vListInsert. */
|
||
|
|
vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
|
||
|
|
80045cc: 4b0a ldr r3, [pc, #40] ; (80045f8 <vTaskPlaceOnEventListRestricted+0x54>)
|
||
|
|
80045ce: 681b ldr r3, [r3, #0]
|
||
|
|
80045d0: 3318 adds r3, #24
|
||
|
|
80045d2: 4619 mov r1, r3
|
||
|
|
80045d4: 68f8 ldr r0, [r7, #12]
|
||
|
|
80045d6: f7fe fe10 bl 80031fa <vListInsertEnd>
|
||
|
|
|
||
|
|
/* If the task should block indefinitely then set the block time to a
|
||
|
|
value that will be recognised as an indefinite delay inside the
|
||
|
|
prvAddCurrentTaskToDelayedList() function. */
|
||
|
|
if( xWaitIndefinitely != pdFALSE )
|
||
|
|
80045da: 687b ldr r3, [r7, #4]
|
||
|
|
80045dc: 2b00 cmp r3, #0
|
||
|
|
80045de: d002 beq.n 80045e6 <vTaskPlaceOnEventListRestricted+0x42>
|
||
|
|
{
|
||
|
|
xTicksToWait = portMAX_DELAY;
|
||
|
|
80045e0: f04f 33ff mov.w r3, #4294967295
|
||
|
|
80045e4: 60bb str r3, [r7, #8]
|
||
|
|
}
|
||
|
|
|
||
|
|
traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
|
||
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
|
||
|
|
80045e6: 6879 ldr r1, [r7, #4]
|
||
|
|
80045e8: 68b8 ldr r0, [r7, #8]
|
||
|
|
80045ea: f000 fa57 bl 8004a9c <prvAddCurrentTaskToDelayedList>
|
||
|
|
}
|
||
|
|
80045ee: bf00 nop
|
||
|
|
80045f0: 3718 adds r7, #24
|
||
|
|
80045f2: 46bd mov sp, r7
|
||
|
|
80045f4: bd80 pop {r7, pc}
|
||
|
|
80045f6: bf00 nop
|
||
|
|
80045f8: 200037c8 .word 0x200037c8
|
||
|
|
|
||
|
|
080045fc <xTaskRemoveFromEventList>:
|
||
|
|
|
||
|
|
#endif /* configUSE_TIMERS */
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
|
||
|
|
{
|
||
|
|
80045fc: b580 push {r7, lr}
|
||
|
|
80045fe: b086 sub sp, #24
|
||
|
|
8004600: af00 add r7, sp, #0
|
||
|
|
8004602: 6078 str r0, [r7, #4]
|
||
|
|
get called - the lock count on the queue will get modified instead. This
|
||
|
|
means exclusive access to the event list is guaranteed here.
|
||
|
|
|
||
|
|
This function assumes that a check has already been made to ensure that
|
||
|
|
pxEventList is not empty. */
|
||
|
|
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
||
|
|
8004604: 687b ldr r3, [r7, #4]
|
||
|
|
8004606: 68db ldr r3, [r3, #12]
|
||
|
|
8004608: 68db ldr r3, [r3, #12]
|
||
|
|
800460a: 613b str r3, [r7, #16]
|
||
|
|
configASSERT( pxUnblockedTCB );
|
||
|
|
800460c: 693b ldr r3, [r7, #16]
|
||
|
|
800460e: 2b00 cmp r3, #0
|
||
|
|
8004610: d10a bne.n 8004628 <xTaskRemoveFromEventList+0x2c>
|
||
|
|
__asm volatile
|
||
|
|
8004612: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004616: f383 8811 msr BASEPRI, r3
|
||
|
|
800461a: f3bf 8f6f isb sy
|
||
|
|
800461e: f3bf 8f4f dsb sy
|
||
|
|
8004622: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
8004624: bf00 nop
|
||
|
|
8004626: e7fe b.n 8004626 <xTaskRemoveFromEventList+0x2a>
|
||
|
|
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
|
||
|
|
8004628: 693b ldr r3, [r7, #16]
|
||
|
|
800462a: 3318 adds r3, #24
|
||
|
|
800462c: 4618 mov r0, r3
|
||
|
|
800462e: f7fe fe41 bl 80032b4 <uxListRemove>
|
||
|
|
|
||
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
||
|
|
8004632: 4b1e ldr r3, [pc, #120] ; (80046ac <xTaskRemoveFromEventList+0xb0>)
|
||
|
|
8004634: 681b ldr r3, [r3, #0]
|
||
|
|
8004636: 2b00 cmp r3, #0
|
||
|
|
8004638: d11d bne.n 8004676 <xTaskRemoveFromEventList+0x7a>
|
||
|
|
{
|
||
|
|
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
|
||
|
|
800463a: 693b ldr r3, [r7, #16]
|
||
|
|
800463c: 3304 adds r3, #4
|
||
|
|
800463e: 4618 mov r0, r3
|
||
|
|
8004640: f7fe fe38 bl 80032b4 <uxListRemove>
|
||
|
|
prvAddTaskToReadyList( pxUnblockedTCB );
|
||
|
|
8004644: 693b ldr r3, [r7, #16]
|
||
|
|
8004646: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8004648: 4b19 ldr r3, [pc, #100] ; (80046b0 <xTaskRemoveFromEventList+0xb4>)
|
||
|
|
800464a: 681b ldr r3, [r3, #0]
|
||
|
|
800464c: 429a cmp r2, r3
|
||
|
|
800464e: d903 bls.n 8004658 <xTaskRemoveFromEventList+0x5c>
|
||
|
|
8004650: 693b ldr r3, [r7, #16]
|
||
|
|
8004652: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
8004654: 4a16 ldr r2, [pc, #88] ; (80046b0 <xTaskRemoveFromEventList+0xb4>)
|
||
|
|
8004656: 6013 str r3, [r2, #0]
|
||
|
|
8004658: 693b ldr r3, [r7, #16]
|
||
|
|
800465a: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
800465c: 4613 mov r3, r2
|
||
|
|
800465e: 009b lsls r3, r3, #2
|
||
|
|
8004660: 4413 add r3, r2
|
||
|
|
8004662: 009b lsls r3, r3, #2
|
||
|
|
8004664: 4a13 ldr r2, [pc, #76] ; (80046b4 <xTaskRemoveFromEventList+0xb8>)
|
||
|
|
8004666: 441a add r2, r3
|
||
|
|
8004668: 693b ldr r3, [r7, #16]
|
||
|
|
800466a: 3304 adds r3, #4
|
||
|
|
800466c: 4619 mov r1, r3
|
||
|
|
800466e: 4610 mov r0, r2
|
||
|
|
8004670: f7fe fdc3 bl 80031fa <vListInsertEnd>
|
||
|
|
8004674: e005 b.n 8004682 <xTaskRemoveFromEventList+0x86>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* The delayed and ready lists cannot be accessed, so hold this task
|
||
|
|
pending until the scheduler is resumed. */
|
||
|
|
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
|
||
|
|
8004676: 693b ldr r3, [r7, #16]
|
||
|
|
8004678: 3318 adds r3, #24
|
||
|
|
800467a: 4619 mov r1, r3
|
||
|
|
800467c: 480e ldr r0, [pc, #56] ; (80046b8 <xTaskRemoveFromEventList+0xbc>)
|
||
|
|
800467e: f7fe fdbc bl 80031fa <vListInsertEnd>
|
||
|
|
}
|
||
|
|
|
||
|
|
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
|
||
|
|
8004682: 693b ldr r3, [r7, #16]
|
||
|
|
8004684: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8004686: 4b0d ldr r3, [pc, #52] ; (80046bc <xTaskRemoveFromEventList+0xc0>)
|
||
|
|
8004688: 681b ldr r3, [r3, #0]
|
||
|
|
800468a: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
800468c: 429a cmp r2, r3
|
||
|
|
800468e: d905 bls.n 800469c <xTaskRemoveFromEventList+0xa0>
|
||
|
|
{
|
||
|
|
/* Return true if the task removed from the event list has a higher
|
||
|
|
priority than the calling task. This allows the calling task to know if
|
||
|
|
it should force a context switch now. */
|
||
|
|
xReturn = pdTRUE;
|
||
|
|
8004690: 2301 movs r3, #1
|
||
|
|
8004692: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Mark that a yield is pending in case the user is not using the
|
||
|
|
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
|
||
|
|
xYieldPending = pdTRUE;
|
||
|
|
8004694: 4b0a ldr r3, [pc, #40] ; (80046c0 <xTaskRemoveFromEventList+0xc4>)
|
||
|
|
8004696: 2201 movs r2, #1
|
||
|
|
8004698: 601a str r2, [r3, #0]
|
||
|
|
800469a: e001 b.n 80046a0 <xTaskRemoveFromEventList+0xa4>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
xReturn = pdFALSE;
|
||
|
|
800469c: 2300 movs r3, #0
|
||
|
|
800469e: 617b str r3, [r7, #20]
|
||
|
|
}
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
80046a0: 697b ldr r3, [r7, #20]
|
||
|
|
}
|
||
|
|
80046a2: 4618 mov r0, r3
|
||
|
|
80046a4: 3718 adds r7, #24
|
||
|
|
80046a6: 46bd mov sp, r7
|
||
|
|
80046a8: bd80 pop {r7, pc}
|
||
|
|
80046aa: bf00 nop
|
||
|
|
80046ac: 20003cc4 .word 0x20003cc4
|
||
|
|
80046b0: 20003ca4 .word 0x20003ca4
|
||
|
|
80046b4: 200037cc .word 0x200037cc
|
||
|
|
80046b8: 20003c5c .word 0x20003c5c
|
||
|
|
80046bc: 200037c8 .word 0x200037c8
|
||
|
|
80046c0: 20003cb0 .word 0x20003cb0
|
||
|
|
|
||
|
|
080046c4 <vTaskInternalSetTimeOutState>:
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
|
||
|
|
{
|
||
|
|
80046c4: b480 push {r7}
|
||
|
|
80046c6: b083 sub sp, #12
|
||
|
|
80046c8: af00 add r7, sp, #0
|
||
|
|
80046ca: 6078 str r0, [r7, #4]
|
||
|
|
/* For internal use only as it does not use a critical section. */
|
||
|
|
pxTimeOut->xOverflowCount = xNumOfOverflows;
|
||
|
|
80046cc: 4b06 ldr r3, [pc, #24] ; (80046e8 <vTaskInternalSetTimeOutState+0x24>)
|
||
|
|
80046ce: 681a ldr r2, [r3, #0]
|
||
|
|
80046d0: 687b ldr r3, [r7, #4]
|
||
|
|
80046d2: 601a str r2, [r3, #0]
|
||
|
|
pxTimeOut->xTimeOnEntering = xTickCount;
|
||
|
|
80046d4: 4b05 ldr r3, [pc, #20] ; (80046ec <vTaskInternalSetTimeOutState+0x28>)
|
||
|
|
80046d6: 681a ldr r2, [r3, #0]
|
||
|
|
80046d8: 687b ldr r3, [r7, #4]
|
||
|
|
80046da: 605a str r2, [r3, #4]
|
||
|
|
}
|
||
|
|
80046dc: bf00 nop
|
||
|
|
80046de: 370c adds r7, #12
|
||
|
|
80046e0: 46bd mov sp, r7
|
||
|
|
80046e2: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80046e6: 4770 bx lr
|
||
|
|
80046e8: 20003cb4 .word 0x20003cb4
|
||
|
|
80046ec: 20003ca0 .word 0x20003ca0
|
||
|
|
|
||
|
|
080046f0 <xTaskCheckForTimeOut>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
|
||
|
|
{
|
||
|
|
80046f0: b580 push {r7, lr}
|
||
|
|
80046f2: b088 sub sp, #32
|
||
|
|
80046f4: af00 add r7, sp, #0
|
||
|
|
80046f6: 6078 str r0, [r7, #4]
|
||
|
|
80046f8: 6039 str r1, [r7, #0]
|
||
|
|
BaseType_t xReturn;
|
||
|
|
|
||
|
|
configASSERT( pxTimeOut );
|
||
|
|
80046fa: 687b ldr r3, [r7, #4]
|
||
|
|
80046fc: 2b00 cmp r3, #0
|
||
|
|
80046fe: d10a bne.n 8004716 <xTaskCheckForTimeOut+0x26>
|
||
|
|
__asm volatile
|
||
|
|
8004700: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004704: f383 8811 msr BASEPRI, r3
|
||
|
|
8004708: f3bf 8f6f isb sy
|
||
|
|
800470c: f3bf 8f4f dsb sy
|
||
|
|
8004710: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
8004712: bf00 nop
|
||
|
|
8004714: e7fe b.n 8004714 <xTaskCheckForTimeOut+0x24>
|
||
|
|
configASSERT( pxTicksToWait );
|
||
|
|
8004716: 683b ldr r3, [r7, #0]
|
||
|
|
8004718: 2b00 cmp r3, #0
|
||
|
|
800471a: d10a bne.n 8004732 <xTaskCheckForTimeOut+0x42>
|
||
|
|
__asm volatile
|
||
|
|
800471c: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004720: f383 8811 msr BASEPRI, r3
|
||
|
|
8004724: f3bf 8f6f isb sy
|
||
|
|
8004728: f3bf 8f4f dsb sy
|
||
|
|
800472c: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
800472e: bf00 nop
|
||
|
|
8004730: e7fe b.n 8004730 <xTaskCheckForTimeOut+0x40>
|
||
|
|
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
8004732: f000 fe7f bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
/* Minor optimisation. The tick count cannot change in this block. */
|
||
|
|
const TickType_t xConstTickCount = xTickCount;
|
||
|
|
8004736: 4b1d ldr r3, [pc, #116] ; (80047ac <xTaskCheckForTimeOut+0xbc>)
|
||
|
|
8004738: 681b ldr r3, [r3, #0]
|
||
|
|
800473a: 61bb str r3, [r7, #24]
|
||
|
|
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
|
||
|
|
800473c: 687b ldr r3, [r7, #4]
|
||
|
|
800473e: 685b ldr r3, [r3, #4]
|
||
|
|
8004740: 69ba ldr r2, [r7, #24]
|
||
|
|
8004742: 1ad3 subs r3, r2, r3
|
||
|
|
8004744: 617b str r3, [r7, #20]
|
||
|
|
}
|
||
|
|
else
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
||
|
|
if( *pxTicksToWait == portMAX_DELAY )
|
||
|
|
8004746: 683b ldr r3, [r7, #0]
|
||
|
|
8004748: 681b ldr r3, [r3, #0]
|
||
|
|
800474a: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
800474e: d102 bne.n 8004756 <xTaskCheckForTimeOut+0x66>
|
||
|
|
{
|
||
|
|
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
|
||
|
|
specified is the maximum block time then the task should block
|
||
|
|
indefinitely, and therefore never time out. */
|
||
|
|
xReturn = pdFALSE;
|
||
|
|
8004750: 2300 movs r3, #0
|
||
|
|
8004752: 61fb str r3, [r7, #28]
|
||
|
|
8004754: e023 b.n 800479e <xTaskCheckForTimeOut+0xae>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
#endif
|
||
|
|
|
||
|
|
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
|
||
|
|
8004756: 687b ldr r3, [r7, #4]
|
||
|
|
8004758: 681a ldr r2, [r3, #0]
|
||
|
|
800475a: 4b15 ldr r3, [pc, #84] ; (80047b0 <xTaskCheckForTimeOut+0xc0>)
|
||
|
|
800475c: 681b ldr r3, [r3, #0]
|
||
|
|
800475e: 429a cmp r2, r3
|
||
|
|
8004760: d007 beq.n 8004772 <xTaskCheckForTimeOut+0x82>
|
||
|
|
8004762: 687b ldr r3, [r7, #4]
|
||
|
|
8004764: 685b ldr r3, [r3, #4]
|
||
|
|
8004766: 69ba ldr r2, [r7, #24]
|
||
|
|
8004768: 429a cmp r2, r3
|
||
|
|
800476a: d302 bcc.n 8004772 <xTaskCheckForTimeOut+0x82>
|
||
|
|
/* The tick count is greater than the time at which
|
||
|
|
vTaskSetTimeout() was called, but has also overflowed since
|
||
|
|
vTaskSetTimeOut() was called. It must have wrapped all the way
|
||
|
|
around and gone past again. This passed since vTaskSetTimeout()
|
||
|
|
was called. */
|
||
|
|
xReturn = pdTRUE;
|
||
|
|
800476c: 2301 movs r3, #1
|
||
|
|
800476e: 61fb str r3, [r7, #28]
|
||
|
|
8004770: e015 b.n 800479e <xTaskCheckForTimeOut+0xae>
|
||
|
|
}
|
||
|
|
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
|
||
|
|
8004772: 683b ldr r3, [r7, #0]
|
||
|
|
8004774: 681b ldr r3, [r3, #0]
|
||
|
|
8004776: 697a ldr r2, [r7, #20]
|
||
|
|
8004778: 429a cmp r2, r3
|
||
|
|
800477a: d20b bcs.n 8004794 <xTaskCheckForTimeOut+0xa4>
|
||
|
|
{
|
||
|
|
/* Not a genuine timeout. Adjust parameters for time remaining. */
|
||
|
|
*pxTicksToWait -= xElapsedTime;
|
||
|
|
800477c: 683b ldr r3, [r7, #0]
|
||
|
|
800477e: 681a ldr r2, [r3, #0]
|
||
|
|
8004780: 697b ldr r3, [r7, #20]
|
||
|
|
8004782: 1ad2 subs r2, r2, r3
|
||
|
|
8004784: 683b ldr r3, [r7, #0]
|
||
|
|
8004786: 601a str r2, [r3, #0]
|
||
|
|
vTaskInternalSetTimeOutState( pxTimeOut );
|
||
|
|
8004788: 6878 ldr r0, [r7, #4]
|
||
|
|
800478a: f7ff ff9b bl 80046c4 <vTaskInternalSetTimeOutState>
|
||
|
|
xReturn = pdFALSE;
|
||
|
|
800478e: 2300 movs r3, #0
|
||
|
|
8004790: 61fb str r3, [r7, #28]
|
||
|
|
8004792: e004 b.n 800479e <xTaskCheckForTimeOut+0xae>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
*pxTicksToWait = 0;
|
||
|
|
8004794: 683b ldr r3, [r7, #0]
|
||
|
|
8004796: 2200 movs r2, #0
|
||
|
|
8004798: 601a str r2, [r3, #0]
|
||
|
|
xReturn = pdTRUE;
|
||
|
|
800479a: 2301 movs r3, #1
|
||
|
|
800479c: 61fb str r3, [r7, #28]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
800479e: f000 fe79 bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
80047a2: 69fb ldr r3, [r7, #28]
|
||
|
|
}
|
||
|
|
80047a4: 4618 mov r0, r3
|
||
|
|
80047a6: 3720 adds r7, #32
|
||
|
|
80047a8: 46bd mov sp, r7
|
||
|
|
80047aa: bd80 pop {r7, pc}
|
||
|
|
80047ac: 20003ca0 .word 0x20003ca0
|
||
|
|
80047b0: 20003cb4 .word 0x20003cb4
|
||
|
|
|
||
|
|
080047b4 <vTaskMissedYield>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vTaskMissedYield( void )
|
||
|
|
{
|
||
|
|
80047b4: b480 push {r7}
|
||
|
|
80047b6: af00 add r7, sp, #0
|
||
|
|
xYieldPending = pdTRUE;
|
||
|
|
80047b8: 4b03 ldr r3, [pc, #12] ; (80047c8 <vTaskMissedYield+0x14>)
|
||
|
|
80047ba: 2201 movs r2, #1
|
||
|
|
80047bc: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
80047be: bf00 nop
|
||
|
|
80047c0: 46bd mov sp, r7
|
||
|
|
80047c2: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80047c6: 4770 bx lr
|
||
|
|
80047c8: 20003cb0 .word 0x20003cb0
|
||
|
|
|
||
|
|
080047cc <prvIdleTask>:
|
||
|
|
*
|
||
|
|
* void prvIdleTask( void *pvParameters );
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
static portTASK_FUNCTION( prvIdleTask, pvParameters )
|
||
|
|
{
|
||
|
|
80047cc: b580 push {r7, lr}
|
||
|
|
80047ce: b082 sub sp, #8
|
||
|
|
80047d0: af00 add r7, sp, #0
|
||
|
|
80047d2: 6078 str r0, [r7, #4]
|
||
|
|
|
||
|
|
for( ;; )
|
||
|
|
{
|
||
|
|
/* See if any tasks have deleted themselves - if so then the idle task
|
||
|
|
is responsible for freeing the deleted task's TCB and stack. */
|
||
|
|
prvCheckTasksWaitingTermination();
|
||
|
|
80047d4: f000 f854 bl 8004880 <prvCheckTasksWaitingTermination>
|
||
|
|
|
||
|
|
A critical region is not required here as we are just reading from
|
||
|
|
the list, and an occasional incorrect value will not matter. If
|
||
|
|
the ready list at the idle priority contains more than one task
|
||
|
|
then a task other than the idle task is ready to execute. */
|
||
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
|
||
|
|
80047d8: 4b07 ldr r3, [pc, #28] ; (80047f8 <prvIdleTask+0x2c>)
|
||
|
|
80047da: 681b ldr r3, [r3, #0]
|
||
|
|
80047dc: 2b01 cmp r3, #1
|
||
|
|
80047de: d907 bls.n 80047f0 <prvIdleTask+0x24>
|
||
|
|
{
|
||
|
|
taskYIELD();
|
||
|
|
80047e0: 4b06 ldr r3, [pc, #24] ; (80047fc <prvIdleTask+0x30>)
|
||
|
|
80047e2: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
80047e6: 601a str r2, [r3, #0]
|
||
|
|
80047e8: f3bf 8f4f dsb sy
|
||
|
|
80047ec: f3bf 8f6f isb sy
|
||
|
|
/* Call the user defined function from within the idle task. This
|
||
|
|
allows the application designer to add background functionality
|
||
|
|
without the overhead of a separate task.
|
||
|
|
NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
|
||
|
|
CALL A FUNCTION THAT MIGHT BLOCK. */
|
||
|
|
vApplicationIdleHook();
|
||
|
|
80047f0: f7fb fe70 bl 80004d4 <vApplicationIdleHook>
|
||
|
|
prvCheckTasksWaitingTermination();
|
||
|
|
80047f4: e7ee b.n 80047d4 <prvIdleTask+0x8>
|
||
|
|
80047f6: bf00 nop
|
||
|
|
80047f8: 200037cc .word 0x200037cc
|
||
|
|
80047fc: e000ed04 .word 0xe000ed04
|
||
|
|
|
||
|
|
08004800 <prvInitialiseTaskLists>:
|
||
|
|
|
||
|
|
#endif /* portUSING_MPU_WRAPPERS */
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvInitialiseTaskLists( void )
|
||
|
|
{
|
||
|
|
8004800: b580 push {r7, lr}
|
||
|
|
8004802: b082 sub sp, #8
|
||
|
|
8004804: af00 add r7, sp, #0
|
||
|
|
UBaseType_t uxPriority;
|
||
|
|
|
||
|
|
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
|
||
|
|
8004806: 2300 movs r3, #0
|
||
|
|
8004808: 607b str r3, [r7, #4]
|
||
|
|
800480a: e00c b.n 8004826 <prvInitialiseTaskLists+0x26>
|
||
|
|
{
|
||
|
|
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
|
||
|
|
800480c: 687a ldr r2, [r7, #4]
|
||
|
|
800480e: 4613 mov r3, r2
|
||
|
|
8004810: 009b lsls r3, r3, #2
|
||
|
|
8004812: 4413 add r3, r2
|
||
|
|
8004814: 009b lsls r3, r3, #2
|
||
|
|
8004816: 4a12 ldr r2, [pc, #72] ; (8004860 <prvInitialiseTaskLists+0x60>)
|
||
|
|
8004818: 4413 add r3, r2
|
||
|
|
800481a: 4618 mov r0, r3
|
||
|
|
800481c: f7fe fcc0 bl 80031a0 <vListInitialise>
|
||
|
|
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
|
||
|
|
8004820: 687b ldr r3, [r7, #4]
|
||
|
|
8004822: 3301 adds r3, #1
|
||
|
|
8004824: 607b str r3, [r7, #4]
|
||
|
|
8004826: 687b ldr r3, [r7, #4]
|
||
|
|
8004828: 2b37 cmp r3, #55 ; 0x37
|
||
|
|
800482a: d9ef bls.n 800480c <prvInitialiseTaskLists+0xc>
|
||
|
|
}
|
||
|
|
|
||
|
|
vListInitialise( &xDelayedTaskList1 );
|
||
|
|
800482c: 480d ldr r0, [pc, #52] ; (8004864 <prvInitialiseTaskLists+0x64>)
|
||
|
|
800482e: f7fe fcb7 bl 80031a0 <vListInitialise>
|
||
|
|
vListInitialise( &xDelayedTaskList2 );
|
||
|
|
8004832: 480d ldr r0, [pc, #52] ; (8004868 <prvInitialiseTaskLists+0x68>)
|
||
|
|
8004834: f7fe fcb4 bl 80031a0 <vListInitialise>
|
||
|
|
vListInitialise( &xPendingReadyList );
|
||
|
|
8004838: 480c ldr r0, [pc, #48] ; (800486c <prvInitialiseTaskLists+0x6c>)
|
||
|
|
800483a: f7fe fcb1 bl 80031a0 <vListInitialise>
|
||
|
|
|
||
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
||
|
|
{
|
||
|
|
vListInitialise( &xTasksWaitingTermination );
|
||
|
|
800483e: 480c ldr r0, [pc, #48] ; (8004870 <prvInitialiseTaskLists+0x70>)
|
||
|
|
8004840: f7fe fcae bl 80031a0 <vListInitialise>
|
||
|
|
}
|
||
|
|
#endif /* INCLUDE_vTaskDelete */
|
||
|
|
|
||
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
||
|
|
{
|
||
|
|
vListInitialise( &xSuspendedTaskList );
|
||
|
|
8004844: 480b ldr r0, [pc, #44] ; (8004874 <prvInitialiseTaskLists+0x74>)
|
||
|
|
8004846: f7fe fcab bl 80031a0 <vListInitialise>
|
||
|
|
}
|
||
|
|
#endif /* INCLUDE_vTaskSuspend */
|
||
|
|
|
||
|
|
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
|
||
|
|
using list2. */
|
||
|
|
pxDelayedTaskList = &xDelayedTaskList1;
|
||
|
|
800484a: 4b0b ldr r3, [pc, #44] ; (8004878 <prvInitialiseTaskLists+0x78>)
|
||
|
|
800484c: 4a05 ldr r2, [pc, #20] ; (8004864 <prvInitialiseTaskLists+0x64>)
|
||
|
|
800484e: 601a str r2, [r3, #0]
|
||
|
|
pxOverflowDelayedTaskList = &xDelayedTaskList2;
|
||
|
|
8004850: 4b0a ldr r3, [pc, #40] ; (800487c <prvInitialiseTaskLists+0x7c>)
|
||
|
|
8004852: 4a05 ldr r2, [pc, #20] ; (8004868 <prvInitialiseTaskLists+0x68>)
|
||
|
|
8004854: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
8004856: bf00 nop
|
||
|
|
8004858: 3708 adds r7, #8
|
||
|
|
800485a: 46bd mov sp, r7
|
||
|
|
800485c: bd80 pop {r7, pc}
|
||
|
|
800485e: bf00 nop
|
||
|
|
8004860: 200037cc .word 0x200037cc
|
||
|
|
8004864: 20003c2c .word 0x20003c2c
|
||
|
|
8004868: 20003c40 .word 0x20003c40
|
||
|
|
800486c: 20003c5c .word 0x20003c5c
|
||
|
|
8004870: 20003c70 .word 0x20003c70
|
||
|
|
8004874: 20003c88 .word 0x20003c88
|
||
|
|
8004878: 20003c54 .word 0x20003c54
|
||
|
|
800487c: 20003c58 .word 0x20003c58
|
||
|
|
|
||
|
|
08004880 <prvCheckTasksWaitingTermination>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvCheckTasksWaitingTermination( void )
|
||
|
|
{
|
||
|
|
8004880: b580 push {r7, lr}
|
||
|
|
8004882: b082 sub sp, #8
|
||
|
|
8004884: af00 add r7, sp, #0
|
||
|
|
{
|
||
|
|
TCB_t *pxTCB;
|
||
|
|
|
||
|
|
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
|
||
|
|
being called too often in the idle task. */
|
||
|
|
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
|
||
|
|
8004886: e019 b.n 80048bc <prvCheckTasksWaitingTermination+0x3c>
|
||
|
|
{
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
8004888: f000 fdd4 bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
||
|
|
800488c: 4b10 ldr r3, [pc, #64] ; (80048d0 <prvCheckTasksWaitingTermination+0x50>)
|
||
|
|
800488e: 68db ldr r3, [r3, #12]
|
||
|
|
8004890: 68db ldr r3, [r3, #12]
|
||
|
|
8004892: 607b str r3, [r7, #4]
|
||
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
||
|
|
8004894: 687b ldr r3, [r7, #4]
|
||
|
|
8004896: 3304 adds r3, #4
|
||
|
|
8004898: 4618 mov r0, r3
|
||
|
|
800489a: f7fe fd0b bl 80032b4 <uxListRemove>
|
||
|
|
--uxCurrentNumberOfTasks;
|
||
|
|
800489e: 4b0d ldr r3, [pc, #52] ; (80048d4 <prvCheckTasksWaitingTermination+0x54>)
|
||
|
|
80048a0: 681b ldr r3, [r3, #0]
|
||
|
|
80048a2: 3b01 subs r3, #1
|
||
|
|
80048a4: 4a0b ldr r2, [pc, #44] ; (80048d4 <prvCheckTasksWaitingTermination+0x54>)
|
||
|
|
80048a6: 6013 str r3, [r2, #0]
|
||
|
|
--uxDeletedTasksWaitingCleanUp;
|
||
|
|
80048a8: 4b0b ldr r3, [pc, #44] ; (80048d8 <prvCheckTasksWaitingTermination+0x58>)
|
||
|
|
80048aa: 681b ldr r3, [r3, #0]
|
||
|
|
80048ac: 3b01 subs r3, #1
|
||
|
|
80048ae: 4a0a ldr r2, [pc, #40] ; (80048d8 <prvCheckTasksWaitingTermination+0x58>)
|
||
|
|
80048b0: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
80048b2: f000 fdef bl 8005494 <vPortExitCritical>
|
||
|
|
|
||
|
|
prvDeleteTCB( pxTCB );
|
||
|
|
80048b6: 6878 ldr r0, [r7, #4]
|
||
|
|
80048b8: f000 f810 bl 80048dc <prvDeleteTCB>
|
||
|
|
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
|
||
|
|
80048bc: 4b06 ldr r3, [pc, #24] ; (80048d8 <prvCheckTasksWaitingTermination+0x58>)
|
||
|
|
80048be: 681b ldr r3, [r3, #0]
|
||
|
|
80048c0: 2b00 cmp r3, #0
|
||
|
|
80048c2: d1e1 bne.n 8004888 <prvCheckTasksWaitingTermination+0x8>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* INCLUDE_vTaskDelete */
|
||
|
|
}
|
||
|
|
80048c4: bf00 nop
|
||
|
|
80048c6: bf00 nop
|
||
|
|
80048c8: 3708 adds r7, #8
|
||
|
|
80048ca: 46bd mov sp, r7
|
||
|
|
80048cc: bd80 pop {r7, pc}
|
||
|
|
80048ce: bf00 nop
|
||
|
|
80048d0: 20003c70 .word 0x20003c70
|
||
|
|
80048d4: 20003c9c .word 0x20003c9c
|
||
|
|
80048d8: 20003c84 .word 0x20003c84
|
||
|
|
|
||
|
|
080048dc <prvDeleteTCB>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
||
|
|
|
||
|
|
static void prvDeleteTCB( TCB_t *pxTCB )
|
||
|
|
{
|
||
|
|
80048dc: b580 push {r7, lr}
|
||
|
|
80048de: b084 sub sp, #16
|
||
|
|
80048e0: af00 add r7, sp, #0
|
||
|
|
80048e2: 6078 str r0, [r7, #4]
|
||
|
|
to the task to free any memory allocated at the application level.
|
||
|
|
See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
|
||
|
|
for additional information. */
|
||
|
|
#if ( configUSE_NEWLIB_REENTRANT == 1 )
|
||
|
|
{
|
||
|
|
_reclaim_reent( &( pxTCB->xNewLib_reent ) );
|
||
|
|
80048e4: 687b ldr r3, [r7, #4]
|
||
|
|
80048e6: 3354 adds r3, #84 ; 0x54
|
||
|
|
80048e8: 4618 mov r0, r3
|
||
|
|
80048ea: f001 f939 bl 8005b60 <_reclaim_reent>
|
||
|
|
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
|
||
|
|
{
|
||
|
|
/* The task could have been allocated statically or dynamically, so
|
||
|
|
check what was statically allocated before trying to free the
|
||
|
|
memory. */
|
||
|
|
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
|
||
|
|
80048ee: 687b ldr r3, [r7, #4]
|
||
|
|
80048f0: f893 30b9 ldrb.w r3, [r3, #185] ; 0xb9
|
||
|
|
80048f4: 2b00 cmp r3, #0
|
||
|
|
80048f6: d108 bne.n 800490a <prvDeleteTCB+0x2e>
|
||
|
|
{
|
||
|
|
/* Both the stack and TCB were allocated dynamically, so both
|
||
|
|
must be freed. */
|
||
|
|
vPortFree( pxTCB->pxStack );
|
||
|
|
80048f8: 687b ldr r3, [r7, #4]
|
||
|
|
80048fa: 6b1b ldr r3, [r3, #48] ; 0x30
|
||
|
|
80048fc: 4618 mov r0, r3
|
||
|
|
80048fe: f000 ff5f bl 80057c0 <vPortFree>
|
||
|
|
vPortFree( pxTCB );
|
||
|
|
8004902: 6878 ldr r0, [r7, #4]
|
||
|
|
8004904: f000 ff5c bl 80057c0 <vPortFree>
|
||
|
|
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
||
|
|
}
|
||
|
|
8004908: e018 b.n 800493c <prvDeleteTCB+0x60>
|
||
|
|
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
|
||
|
|
800490a: 687b ldr r3, [r7, #4]
|
||
|
|
800490c: f893 30b9 ldrb.w r3, [r3, #185] ; 0xb9
|
||
|
|
8004910: 2b01 cmp r3, #1
|
||
|
|
8004912: d103 bne.n 800491c <prvDeleteTCB+0x40>
|
||
|
|
vPortFree( pxTCB );
|
||
|
|
8004914: 6878 ldr r0, [r7, #4]
|
||
|
|
8004916: f000 ff53 bl 80057c0 <vPortFree>
|
||
|
|
}
|
||
|
|
800491a: e00f b.n 800493c <prvDeleteTCB+0x60>
|
||
|
|
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
|
||
|
|
800491c: 687b ldr r3, [r7, #4]
|
||
|
|
800491e: f893 30b9 ldrb.w r3, [r3, #185] ; 0xb9
|
||
|
|
8004922: 2b02 cmp r3, #2
|
||
|
|
8004924: d00a beq.n 800493c <prvDeleteTCB+0x60>
|
||
|
|
__asm volatile
|
||
|
|
8004926: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
800492a: f383 8811 msr BASEPRI, r3
|
||
|
|
800492e: f3bf 8f6f isb sy
|
||
|
|
8004932: f3bf 8f4f dsb sy
|
||
|
|
8004936: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
8004938: bf00 nop
|
||
|
|
800493a: e7fe b.n 800493a <prvDeleteTCB+0x5e>
|
||
|
|
}
|
||
|
|
800493c: bf00 nop
|
||
|
|
800493e: 3710 adds r7, #16
|
||
|
|
8004940: 46bd mov sp, r7
|
||
|
|
8004942: bd80 pop {r7, pc}
|
||
|
|
|
||
|
|
08004944 <prvResetNextTaskUnblockTime>:
|
||
|
|
|
||
|
|
#endif /* INCLUDE_vTaskDelete */
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvResetNextTaskUnblockTime( void )
|
||
|
|
{
|
||
|
|
8004944: b480 push {r7}
|
||
|
|
8004946: b083 sub sp, #12
|
||
|
|
8004948: af00 add r7, sp, #0
|
||
|
|
TCB_t *pxTCB;
|
||
|
|
|
||
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
||
|
|
800494a: 4b0c ldr r3, [pc, #48] ; (800497c <prvResetNextTaskUnblockTime+0x38>)
|
||
|
|
800494c: 681b ldr r3, [r3, #0]
|
||
|
|
800494e: 681b ldr r3, [r3, #0]
|
||
|
|
8004950: 2b00 cmp r3, #0
|
||
|
|
8004952: d104 bne.n 800495e <prvResetNextTaskUnblockTime+0x1a>
|
||
|
|
{
|
||
|
|
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
|
||
|
|
the maximum possible value so it is extremely unlikely that the
|
||
|
|
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
|
||
|
|
there is an item in the delayed list. */
|
||
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
||
|
|
8004954: 4b0a ldr r3, [pc, #40] ; (8004980 <prvResetNextTaskUnblockTime+0x3c>)
|
||
|
|
8004956: f04f 32ff mov.w r2, #4294967295
|
||
|
|
800495a: 601a str r2, [r3, #0]
|
||
|
|
which the task at the head of the delayed list should be removed
|
||
|
|
from the Blocked state. */
|
||
|
|
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
||
|
|
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
|
||
|
|
}
|
||
|
|
}
|
||
|
|
800495c: e008 b.n 8004970 <prvResetNextTaskUnblockTime+0x2c>
|
||
|
|
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
||
|
|
800495e: 4b07 ldr r3, [pc, #28] ; (800497c <prvResetNextTaskUnblockTime+0x38>)
|
||
|
|
8004960: 681b ldr r3, [r3, #0]
|
||
|
|
8004962: 68db ldr r3, [r3, #12]
|
||
|
|
8004964: 68db ldr r3, [r3, #12]
|
||
|
|
8004966: 607b str r3, [r7, #4]
|
||
|
|
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
|
||
|
|
8004968: 687b ldr r3, [r7, #4]
|
||
|
|
800496a: 685b ldr r3, [r3, #4]
|
||
|
|
800496c: 4a04 ldr r2, [pc, #16] ; (8004980 <prvResetNextTaskUnblockTime+0x3c>)
|
||
|
|
800496e: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
8004970: bf00 nop
|
||
|
|
8004972: 370c adds r7, #12
|
||
|
|
8004974: 46bd mov sp, r7
|
||
|
|
8004976: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
800497a: 4770 bx lr
|
||
|
|
800497c: 20003c54 .word 0x20003c54
|
||
|
|
8004980: 20003cbc .word 0x20003cbc
|
||
|
|
|
||
|
|
08004984 <xTaskGetSchedulerState>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||
|
|
|
||
|
|
BaseType_t xTaskGetSchedulerState( void )
|
||
|
|
{
|
||
|
|
8004984: b480 push {r7}
|
||
|
|
8004986: b083 sub sp, #12
|
||
|
|
8004988: af00 add r7, sp, #0
|
||
|
|
BaseType_t xReturn;
|
||
|
|
|
||
|
|
if( xSchedulerRunning == pdFALSE )
|
||
|
|
800498a: 4b0b ldr r3, [pc, #44] ; (80049b8 <xTaskGetSchedulerState+0x34>)
|
||
|
|
800498c: 681b ldr r3, [r3, #0]
|
||
|
|
800498e: 2b00 cmp r3, #0
|
||
|
|
8004990: d102 bne.n 8004998 <xTaskGetSchedulerState+0x14>
|
||
|
|
{
|
||
|
|
xReturn = taskSCHEDULER_NOT_STARTED;
|
||
|
|
8004992: 2301 movs r3, #1
|
||
|
|
8004994: 607b str r3, [r7, #4]
|
||
|
|
8004996: e008 b.n 80049aa <xTaskGetSchedulerState+0x26>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
||
|
|
8004998: 4b08 ldr r3, [pc, #32] ; (80049bc <xTaskGetSchedulerState+0x38>)
|
||
|
|
800499a: 681b ldr r3, [r3, #0]
|
||
|
|
800499c: 2b00 cmp r3, #0
|
||
|
|
800499e: d102 bne.n 80049a6 <xTaskGetSchedulerState+0x22>
|
||
|
|
{
|
||
|
|
xReturn = taskSCHEDULER_RUNNING;
|
||
|
|
80049a0: 2302 movs r3, #2
|
||
|
|
80049a2: 607b str r3, [r7, #4]
|
||
|
|
80049a4: e001 b.n 80049aa <xTaskGetSchedulerState+0x26>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
xReturn = taskSCHEDULER_SUSPENDED;
|
||
|
|
80049a6: 2300 movs r3, #0
|
||
|
|
80049a8: 607b str r3, [r7, #4]
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
80049aa: 687b ldr r3, [r7, #4]
|
||
|
|
}
|
||
|
|
80049ac: 4618 mov r0, r3
|
||
|
|
80049ae: 370c adds r7, #12
|
||
|
|
80049b0: 46bd mov sp, r7
|
||
|
|
80049b2: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80049b6: 4770 bx lr
|
||
|
|
80049b8: 20003ca8 .word 0x20003ca8
|
||
|
|
80049bc: 20003cc4 .word 0x20003cc4
|
||
|
|
|
||
|
|
080049c0 <xTaskPriorityDisinherit>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
#if ( configUSE_MUTEXES == 1 )
|
||
|
|
|
||
|
|
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
|
||
|
|
{
|
||
|
|
80049c0: b580 push {r7, lr}
|
||
|
|
80049c2: b086 sub sp, #24
|
||
|
|
80049c4: af00 add r7, sp, #0
|
||
|
|
80049c6: 6078 str r0, [r7, #4]
|
||
|
|
TCB_t * const pxTCB = pxMutexHolder;
|
||
|
|
80049c8: 687b ldr r3, [r7, #4]
|
||
|
|
80049ca: 613b str r3, [r7, #16]
|
||
|
|
BaseType_t xReturn = pdFALSE;
|
||
|
|
80049cc: 2300 movs r3, #0
|
||
|
|
80049ce: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
if( pxMutexHolder != NULL )
|
||
|
|
80049d0: 687b ldr r3, [r7, #4]
|
||
|
|
80049d2: 2b00 cmp r3, #0
|
||
|
|
80049d4: d056 beq.n 8004a84 <xTaskPriorityDisinherit+0xc4>
|
||
|
|
{
|
||
|
|
/* A task can only have an inherited priority if it holds the mutex.
|
||
|
|
If the mutex is held by a task then it cannot be given from an
|
||
|
|
interrupt, and if a mutex is given by the holding task then it must
|
||
|
|
be the running state task. */
|
||
|
|
configASSERT( pxTCB == pxCurrentTCB );
|
||
|
|
80049d6: 4b2e ldr r3, [pc, #184] ; (8004a90 <xTaskPriorityDisinherit+0xd0>)
|
||
|
|
80049d8: 681b ldr r3, [r3, #0]
|
||
|
|
80049da: 693a ldr r2, [r7, #16]
|
||
|
|
80049dc: 429a cmp r2, r3
|
||
|
|
80049de: d00a beq.n 80049f6 <xTaskPriorityDisinherit+0x36>
|
||
|
|
__asm volatile
|
||
|
|
80049e0: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80049e4: f383 8811 msr BASEPRI, r3
|
||
|
|
80049e8: f3bf 8f6f isb sy
|
||
|
|
80049ec: f3bf 8f4f dsb sy
|
||
|
|
80049f0: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
80049f2: bf00 nop
|
||
|
|
80049f4: e7fe b.n 80049f4 <xTaskPriorityDisinherit+0x34>
|
||
|
|
configASSERT( pxTCB->uxMutexesHeld );
|
||
|
|
80049f6: 693b ldr r3, [r7, #16]
|
||
|
|
80049f8: 6d1b ldr r3, [r3, #80] ; 0x50
|
||
|
|
80049fa: 2b00 cmp r3, #0
|
||
|
|
80049fc: d10a bne.n 8004a14 <xTaskPriorityDisinherit+0x54>
|
||
|
|
__asm volatile
|
||
|
|
80049fe: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004a02: f383 8811 msr BASEPRI, r3
|
||
|
|
8004a06: f3bf 8f6f isb sy
|
||
|
|
8004a0a: f3bf 8f4f dsb sy
|
||
|
|
8004a0e: 60bb str r3, [r7, #8]
|
||
|
|
}
|
||
|
|
8004a10: bf00 nop
|
||
|
|
8004a12: e7fe b.n 8004a12 <xTaskPriorityDisinherit+0x52>
|
||
|
|
( pxTCB->uxMutexesHeld )--;
|
||
|
|
8004a14: 693b ldr r3, [r7, #16]
|
||
|
|
8004a16: 6d1b ldr r3, [r3, #80] ; 0x50
|
||
|
|
8004a18: 1e5a subs r2, r3, #1
|
||
|
|
8004a1a: 693b ldr r3, [r7, #16]
|
||
|
|
8004a1c: 651a str r2, [r3, #80] ; 0x50
|
||
|
|
|
||
|
|
/* Has the holder of the mutex inherited the priority of another
|
||
|
|
task? */
|
||
|
|
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
|
||
|
|
8004a1e: 693b ldr r3, [r7, #16]
|
||
|
|
8004a20: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8004a22: 693b ldr r3, [r7, #16]
|
||
|
|
8004a24: 6cdb ldr r3, [r3, #76] ; 0x4c
|
||
|
|
8004a26: 429a cmp r2, r3
|
||
|
|
8004a28: d02c beq.n 8004a84 <xTaskPriorityDisinherit+0xc4>
|
||
|
|
{
|
||
|
|
/* Only disinherit if no other mutexes are held. */
|
||
|
|
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
|
||
|
|
8004a2a: 693b ldr r3, [r7, #16]
|
||
|
|
8004a2c: 6d1b ldr r3, [r3, #80] ; 0x50
|
||
|
|
8004a2e: 2b00 cmp r3, #0
|
||
|
|
8004a30: d128 bne.n 8004a84 <xTaskPriorityDisinherit+0xc4>
|
||
|
|
/* A task can only have an inherited priority if it holds
|
||
|
|
the mutex. If the mutex is held by a task then it cannot be
|
||
|
|
given from an interrupt, and if a mutex is given by the
|
||
|
|
holding task then it must be the running state task. Remove
|
||
|
|
the holding task from the ready/delayed list. */
|
||
|
|
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
||
|
|
8004a32: 693b ldr r3, [r7, #16]
|
||
|
|
8004a34: 3304 adds r3, #4
|
||
|
|
8004a36: 4618 mov r0, r3
|
||
|
|
8004a38: f7fe fc3c bl 80032b4 <uxListRemove>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Disinherit the priority before adding the task into the
|
||
|
|
new ready list. */
|
||
|
|
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
|
||
|
|
pxTCB->uxPriority = pxTCB->uxBasePriority;
|
||
|
|
8004a3c: 693b ldr r3, [r7, #16]
|
||
|
|
8004a3e: 6cda ldr r2, [r3, #76] ; 0x4c
|
||
|
|
8004a40: 693b ldr r3, [r7, #16]
|
||
|
|
8004a42: 62da str r2, [r3, #44] ; 0x2c
|
||
|
|
|
||
|
|
/* Reset the event list item value. It cannot be in use for
|
||
|
|
any other purpose if this task is running, and it must be
|
||
|
|
running to give back the mutex. */
|
||
|
|
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
||
|
|
8004a44: 693b ldr r3, [r7, #16]
|
||
|
|
8004a46: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
8004a48: f1c3 0238 rsb r2, r3, #56 ; 0x38
|
||
|
|
8004a4c: 693b ldr r3, [r7, #16]
|
||
|
|
8004a4e: 619a str r2, [r3, #24]
|
||
|
|
prvAddTaskToReadyList( pxTCB );
|
||
|
|
8004a50: 693b ldr r3, [r7, #16]
|
||
|
|
8004a52: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8004a54: 4b0f ldr r3, [pc, #60] ; (8004a94 <xTaskPriorityDisinherit+0xd4>)
|
||
|
|
8004a56: 681b ldr r3, [r3, #0]
|
||
|
|
8004a58: 429a cmp r2, r3
|
||
|
|
8004a5a: d903 bls.n 8004a64 <xTaskPriorityDisinherit+0xa4>
|
||
|
|
8004a5c: 693b ldr r3, [r7, #16]
|
||
|
|
8004a5e: 6adb ldr r3, [r3, #44] ; 0x2c
|
||
|
|
8004a60: 4a0c ldr r2, [pc, #48] ; (8004a94 <xTaskPriorityDisinherit+0xd4>)
|
||
|
|
8004a62: 6013 str r3, [r2, #0]
|
||
|
|
8004a64: 693b ldr r3, [r7, #16]
|
||
|
|
8004a66: 6ada ldr r2, [r3, #44] ; 0x2c
|
||
|
|
8004a68: 4613 mov r3, r2
|
||
|
|
8004a6a: 009b lsls r3, r3, #2
|
||
|
|
8004a6c: 4413 add r3, r2
|
||
|
|
8004a6e: 009b lsls r3, r3, #2
|
||
|
|
8004a70: 4a09 ldr r2, [pc, #36] ; (8004a98 <xTaskPriorityDisinherit+0xd8>)
|
||
|
|
8004a72: 441a add r2, r3
|
||
|
|
8004a74: 693b ldr r3, [r7, #16]
|
||
|
|
8004a76: 3304 adds r3, #4
|
||
|
|
8004a78: 4619 mov r1, r3
|
||
|
|
8004a7a: 4610 mov r0, r2
|
||
|
|
8004a7c: f7fe fbbd bl 80031fa <vListInsertEnd>
|
||
|
|
in an order different to that in which they were taken.
|
||
|
|
If a context switch did not occur when the first mutex was
|
||
|
|
returned, even if a task was waiting on it, then a context
|
||
|
|
switch should occur when the last mutex is returned whether
|
||
|
|
a task is waiting on it or not. */
|
||
|
|
xReturn = pdTRUE;
|
||
|
|
8004a80: 2301 movs r3, #1
|
||
|
|
8004a82: 617b str r3, [r7, #20]
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
8004a84: 697b ldr r3, [r7, #20]
|
||
|
|
}
|
||
|
|
8004a86: 4618 mov r0, r3
|
||
|
|
8004a88: 3718 adds r7, #24
|
||
|
|
8004a8a: 46bd mov sp, r7
|
||
|
|
8004a8c: bd80 pop {r7, pc}
|
||
|
|
8004a8e: bf00 nop
|
||
|
|
8004a90: 200037c8 .word 0x200037c8
|
||
|
|
8004a94: 20003ca4 .word 0x20003ca4
|
||
|
|
8004a98: 200037cc .word 0x200037cc
|
||
|
|
|
||
|
|
08004a9c <prvAddCurrentTaskToDelayedList>:
|
||
|
|
|
||
|
|
#endif
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
|
||
|
|
{
|
||
|
|
8004a9c: b580 push {r7, lr}
|
||
|
|
8004a9e: b084 sub sp, #16
|
||
|
|
8004aa0: af00 add r7, sp, #0
|
||
|
|
8004aa2: 6078 str r0, [r7, #4]
|
||
|
|
8004aa4: 6039 str r1, [r7, #0]
|
||
|
|
TickType_t xTimeToWake;
|
||
|
|
const TickType_t xConstTickCount = xTickCount;
|
||
|
|
8004aa6: 4b21 ldr r3, [pc, #132] ; (8004b2c <prvAddCurrentTaskToDelayedList+0x90>)
|
||
|
|
8004aa8: 681b ldr r3, [r3, #0]
|
||
|
|
8004aaa: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Remove the task from the ready list before adding it to the blocked list
|
||
|
|
as the same list item is used for both lists. */
|
||
|
|
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
||
|
|
8004aac: 4b20 ldr r3, [pc, #128] ; (8004b30 <prvAddCurrentTaskToDelayedList+0x94>)
|
||
|
|
8004aae: 681b ldr r3, [r3, #0]
|
||
|
|
8004ab0: 3304 adds r3, #4
|
||
|
|
8004ab2: 4618 mov r0, r3
|
||
|
|
8004ab4: f7fe fbfe bl 80032b4 <uxListRemove>
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
||
|
|
{
|
||
|
|
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
|
||
|
|
8004ab8: 687b ldr r3, [r7, #4]
|
||
|
|
8004aba: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
8004abe: d10a bne.n 8004ad6 <prvAddCurrentTaskToDelayedList+0x3a>
|
||
|
|
8004ac0: 683b ldr r3, [r7, #0]
|
||
|
|
8004ac2: 2b00 cmp r3, #0
|
||
|
|
8004ac4: d007 beq.n 8004ad6 <prvAddCurrentTaskToDelayedList+0x3a>
|
||
|
|
{
|
||
|
|
/* Add the task to the suspended task list instead of a delayed task
|
||
|
|
list to ensure it is not woken by a timing event. It will block
|
||
|
|
indefinitely. */
|
||
|
|
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
||
|
|
8004ac6: 4b1a ldr r3, [pc, #104] ; (8004b30 <prvAddCurrentTaskToDelayedList+0x94>)
|
||
|
|
8004ac8: 681b ldr r3, [r3, #0]
|
||
|
|
8004aca: 3304 adds r3, #4
|
||
|
|
8004acc: 4619 mov r1, r3
|
||
|
|
8004ace: 4819 ldr r0, [pc, #100] ; (8004b34 <prvAddCurrentTaskToDelayedList+0x98>)
|
||
|
|
8004ad0: f7fe fb93 bl 80031fa <vListInsertEnd>
|
||
|
|
|
||
|
|
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
|
||
|
|
( void ) xCanBlockIndefinitely;
|
||
|
|
}
|
||
|
|
#endif /* INCLUDE_vTaskSuspend */
|
||
|
|
}
|
||
|
|
8004ad4: e026 b.n 8004b24 <prvAddCurrentTaskToDelayedList+0x88>
|
||
|
|
xTimeToWake = xConstTickCount + xTicksToWait;
|
||
|
|
8004ad6: 68fa ldr r2, [r7, #12]
|
||
|
|
8004ad8: 687b ldr r3, [r7, #4]
|
||
|
|
8004ada: 4413 add r3, r2
|
||
|
|
8004adc: 60bb str r3, [r7, #8]
|
||
|
|
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
|
||
|
|
8004ade: 4b14 ldr r3, [pc, #80] ; (8004b30 <prvAddCurrentTaskToDelayedList+0x94>)
|
||
|
|
8004ae0: 681b ldr r3, [r3, #0]
|
||
|
|
8004ae2: 68ba ldr r2, [r7, #8]
|
||
|
|
8004ae4: 605a str r2, [r3, #4]
|
||
|
|
if( xTimeToWake < xConstTickCount )
|
||
|
|
8004ae6: 68ba ldr r2, [r7, #8]
|
||
|
|
8004ae8: 68fb ldr r3, [r7, #12]
|
||
|
|
8004aea: 429a cmp r2, r3
|
||
|
|
8004aec: d209 bcs.n 8004b02 <prvAddCurrentTaskToDelayedList+0x66>
|
||
|
|
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
||
|
|
8004aee: 4b12 ldr r3, [pc, #72] ; (8004b38 <prvAddCurrentTaskToDelayedList+0x9c>)
|
||
|
|
8004af0: 681a ldr r2, [r3, #0]
|
||
|
|
8004af2: 4b0f ldr r3, [pc, #60] ; (8004b30 <prvAddCurrentTaskToDelayedList+0x94>)
|
||
|
|
8004af4: 681b ldr r3, [r3, #0]
|
||
|
|
8004af6: 3304 adds r3, #4
|
||
|
|
8004af8: 4619 mov r1, r3
|
||
|
|
8004afa: 4610 mov r0, r2
|
||
|
|
8004afc: f7fe fba1 bl 8003242 <vListInsert>
|
||
|
|
}
|
||
|
|
8004b00: e010 b.n 8004b24 <prvAddCurrentTaskToDelayedList+0x88>
|
||
|
|
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
||
|
|
8004b02: 4b0e ldr r3, [pc, #56] ; (8004b3c <prvAddCurrentTaskToDelayedList+0xa0>)
|
||
|
|
8004b04: 681a ldr r2, [r3, #0]
|
||
|
|
8004b06: 4b0a ldr r3, [pc, #40] ; (8004b30 <prvAddCurrentTaskToDelayedList+0x94>)
|
||
|
|
8004b08: 681b ldr r3, [r3, #0]
|
||
|
|
8004b0a: 3304 adds r3, #4
|
||
|
|
8004b0c: 4619 mov r1, r3
|
||
|
|
8004b0e: 4610 mov r0, r2
|
||
|
|
8004b10: f7fe fb97 bl 8003242 <vListInsert>
|
||
|
|
if( xTimeToWake < xNextTaskUnblockTime )
|
||
|
|
8004b14: 4b0a ldr r3, [pc, #40] ; (8004b40 <prvAddCurrentTaskToDelayedList+0xa4>)
|
||
|
|
8004b16: 681b ldr r3, [r3, #0]
|
||
|
|
8004b18: 68ba ldr r2, [r7, #8]
|
||
|
|
8004b1a: 429a cmp r2, r3
|
||
|
|
8004b1c: d202 bcs.n 8004b24 <prvAddCurrentTaskToDelayedList+0x88>
|
||
|
|
xNextTaskUnblockTime = xTimeToWake;
|
||
|
|
8004b1e: 4a08 ldr r2, [pc, #32] ; (8004b40 <prvAddCurrentTaskToDelayedList+0xa4>)
|
||
|
|
8004b20: 68bb ldr r3, [r7, #8]
|
||
|
|
8004b22: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
8004b24: bf00 nop
|
||
|
|
8004b26: 3710 adds r7, #16
|
||
|
|
8004b28: 46bd mov sp, r7
|
||
|
|
8004b2a: bd80 pop {r7, pc}
|
||
|
|
8004b2c: 20003ca0 .word 0x20003ca0
|
||
|
|
8004b30: 200037c8 .word 0x200037c8
|
||
|
|
8004b34: 20003c88 .word 0x20003c88
|
||
|
|
8004b38: 20003c58 .word 0x20003c58
|
||
|
|
8004b3c: 20003c54 .word 0x20003c54
|
||
|
|
8004b40: 20003cbc .word 0x20003cbc
|
||
|
|
|
||
|
|
08004b44 <xTimerCreateTimerTask>:
|
||
|
|
TimerCallbackFunction_t pxCallbackFunction,
|
||
|
|
Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xTimerCreateTimerTask( void )
|
||
|
|
{
|
||
|
|
8004b44: b580 push {r7, lr}
|
||
|
|
8004b46: b08a sub sp, #40 ; 0x28
|
||
|
|
8004b48: af04 add r7, sp, #16
|
||
|
|
BaseType_t xReturn = pdFAIL;
|
||
|
|
8004b4a: 2300 movs r3, #0
|
||
|
|
8004b4c: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* This function is called when the scheduler is started if
|
||
|
|
configUSE_TIMERS is set to 1. Check that the infrastructure used by the
|
||
|
|
timer service task has been created/initialised. If timers have already
|
||
|
|
been created then the initialisation will already have been performed. */
|
||
|
|
prvCheckForValidListAndQueue();
|
||
|
|
8004b4e: f000 fb07 bl 8005160 <prvCheckForValidListAndQueue>
|
||
|
|
|
||
|
|
if( xTimerQueue != NULL )
|
||
|
|
8004b52: 4b1c ldr r3, [pc, #112] ; (8004bc4 <xTimerCreateTimerTask+0x80>)
|
||
|
|
8004b54: 681b ldr r3, [r3, #0]
|
||
|
|
8004b56: 2b00 cmp r3, #0
|
||
|
|
8004b58: d021 beq.n 8004b9e <xTimerCreateTimerTask+0x5a>
|
||
|
|
{
|
||
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
||
|
|
{
|
||
|
|
StaticTask_t *pxTimerTaskTCBBuffer = NULL;
|
||
|
|
8004b5a: 2300 movs r3, #0
|
||
|
|
8004b5c: 60fb str r3, [r7, #12]
|
||
|
|
StackType_t *pxTimerTaskStackBuffer = NULL;
|
||
|
|
8004b5e: 2300 movs r3, #0
|
||
|
|
8004b60: 60bb str r3, [r7, #8]
|
||
|
|
uint32_t ulTimerTaskStackSize;
|
||
|
|
|
||
|
|
vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
|
||
|
|
8004b62: 1d3a adds r2, r7, #4
|
||
|
|
8004b64: f107 0108 add.w r1, r7, #8
|
||
|
|
8004b68: f107 030c add.w r3, r7, #12
|
||
|
|
8004b6c: 4618 mov r0, r3
|
||
|
|
8004b6e: f7fe fafd bl 800316c <vApplicationGetTimerTaskMemory>
|
||
|
|
xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
|
||
|
|
8004b72: 6879 ldr r1, [r7, #4]
|
||
|
|
8004b74: 68bb ldr r3, [r7, #8]
|
||
|
|
8004b76: 68fa ldr r2, [r7, #12]
|
||
|
|
8004b78: 9202 str r2, [sp, #8]
|
||
|
|
8004b7a: 9301 str r3, [sp, #4]
|
||
|
|
8004b7c: 2302 movs r3, #2
|
||
|
|
8004b7e: 9300 str r3, [sp, #0]
|
||
|
|
8004b80: 2300 movs r3, #0
|
||
|
|
8004b82: 460a mov r2, r1
|
||
|
|
8004b84: 4910 ldr r1, [pc, #64] ; (8004bc8 <xTimerCreateTimerTask+0x84>)
|
||
|
|
8004b86: 4811 ldr r0, [pc, #68] ; (8004bcc <xTimerCreateTimerTask+0x88>)
|
||
|
|
8004b88: f7ff f8aa bl 8003ce0 <xTaskCreateStatic>
|
||
|
|
8004b8c: 4603 mov r3, r0
|
||
|
|
8004b8e: 4a10 ldr r2, [pc, #64] ; (8004bd0 <xTimerCreateTimerTask+0x8c>)
|
||
|
|
8004b90: 6013 str r3, [r2, #0]
|
||
|
|
NULL,
|
||
|
|
( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
|
||
|
|
pxTimerTaskStackBuffer,
|
||
|
|
pxTimerTaskTCBBuffer );
|
||
|
|
|
||
|
|
if( xTimerTaskHandle != NULL )
|
||
|
|
8004b92: 4b0f ldr r3, [pc, #60] ; (8004bd0 <xTimerCreateTimerTask+0x8c>)
|
||
|
|
8004b94: 681b ldr r3, [r3, #0]
|
||
|
|
8004b96: 2b00 cmp r3, #0
|
||
|
|
8004b98: d001 beq.n 8004b9e <xTimerCreateTimerTask+0x5a>
|
||
|
|
{
|
||
|
|
xReturn = pdPASS;
|
||
|
|
8004b9a: 2301 movs r3, #1
|
||
|
|
8004b9c: 617b str r3, [r7, #20]
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
configASSERT( xReturn );
|
||
|
|
8004b9e: 697b ldr r3, [r7, #20]
|
||
|
|
8004ba0: 2b00 cmp r3, #0
|
||
|
|
8004ba2: d10a bne.n 8004bba <xTimerCreateTimerTask+0x76>
|
||
|
|
__asm volatile
|
||
|
|
8004ba4: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004ba8: f383 8811 msr BASEPRI, r3
|
||
|
|
8004bac: f3bf 8f6f isb sy
|
||
|
|
8004bb0: f3bf 8f4f dsb sy
|
||
|
|
8004bb4: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
8004bb6: bf00 nop
|
||
|
|
8004bb8: e7fe b.n 8004bb8 <xTimerCreateTimerTask+0x74>
|
||
|
|
return xReturn;
|
||
|
|
8004bba: 697b ldr r3, [r7, #20]
|
||
|
|
}
|
||
|
|
8004bbc: 4618 mov r0, r3
|
||
|
|
8004bbe: 3718 adds r7, #24
|
||
|
|
8004bc0: 46bd mov sp, r7
|
||
|
|
8004bc2: bd80 pop {r7, pc}
|
||
|
|
8004bc4: 20003cf8 .word 0x20003cf8
|
||
|
|
8004bc8: 08005cf4 .word 0x08005cf4
|
||
|
|
8004bcc: 08004d09 .word 0x08004d09
|
||
|
|
8004bd0: 20003cfc .word 0x20003cfc
|
||
|
|
|
||
|
|
08004bd4 <xTimerGenericCommand>:
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
|
||
|
|
{
|
||
|
|
8004bd4: b580 push {r7, lr}
|
||
|
|
8004bd6: b08a sub sp, #40 ; 0x28
|
||
|
|
8004bd8: af00 add r7, sp, #0
|
||
|
|
8004bda: 60f8 str r0, [r7, #12]
|
||
|
|
8004bdc: 60b9 str r1, [r7, #8]
|
||
|
|
8004bde: 607a str r2, [r7, #4]
|
||
|
|
8004be0: 603b str r3, [r7, #0]
|
||
|
|
BaseType_t xReturn = pdFAIL;
|
||
|
|
8004be2: 2300 movs r3, #0
|
||
|
|
8004be4: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
DaemonTaskMessage_t xMessage;
|
||
|
|
|
||
|
|
configASSERT( xTimer );
|
||
|
|
8004be6: 68fb ldr r3, [r7, #12]
|
||
|
|
8004be8: 2b00 cmp r3, #0
|
||
|
|
8004bea: d10a bne.n 8004c02 <xTimerGenericCommand+0x2e>
|
||
|
|
__asm volatile
|
||
|
|
8004bec: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004bf0: f383 8811 msr BASEPRI, r3
|
||
|
|
8004bf4: f3bf 8f6f isb sy
|
||
|
|
8004bf8: f3bf 8f4f dsb sy
|
||
|
|
8004bfc: 623b str r3, [r7, #32]
|
||
|
|
}
|
||
|
|
8004bfe: bf00 nop
|
||
|
|
8004c00: e7fe b.n 8004c00 <xTimerGenericCommand+0x2c>
|
||
|
|
|
||
|
|
/* Send a message to the timer service task to perform a particular action
|
||
|
|
on a particular timer definition. */
|
||
|
|
if( xTimerQueue != NULL )
|
||
|
|
8004c02: 4b1a ldr r3, [pc, #104] ; (8004c6c <xTimerGenericCommand+0x98>)
|
||
|
|
8004c04: 681b ldr r3, [r3, #0]
|
||
|
|
8004c06: 2b00 cmp r3, #0
|
||
|
|
8004c08: d02a beq.n 8004c60 <xTimerGenericCommand+0x8c>
|
||
|
|
{
|
||
|
|
/* Send a command to the timer service task to start the xTimer timer. */
|
||
|
|
xMessage.xMessageID = xCommandID;
|
||
|
|
8004c0a: 68bb ldr r3, [r7, #8]
|
||
|
|
8004c0c: 613b str r3, [r7, #16]
|
||
|
|
xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
|
||
|
|
8004c0e: 687b ldr r3, [r7, #4]
|
||
|
|
8004c10: 617b str r3, [r7, #20]
|
||
|
|
xMessage.u.xTimerParameters.pxTimer = xTimer;
|
||
|
|
8004c12: 68fb ldr r3, [r7, #12]
|
||
|
|
8004c14: 61bb str r3, [r7, #24]
|
||
|
|
|
||
|
|
if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
|
||
|
|
8004c16: 68bb ldr r3, [r7, #8]
|
||
|
|
8004c18: 2b05 cmp r3, #5
|
||
|
|
8004c1a: dc18 bgt.n 8004c4e <xTimerGenericCommand+0x7a>
|
||
|
|
{
|
||
|
|
if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
|
||
|
|
8004c1c: f7ff feb2 bl 8004984 <xTaskGetSchedulerState>
|
||
|
|
8004c20: 4603 mov r3, r0
|
||
|
|
8004c22: 2b02 cmp r3, #2
|
||
|
|
8004c24: d109 bne.n 8004c3a <xTimerGenericCommand+0x66>
|
||
|
|
{
|
||
|
|
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
|
||
|
|
8004c26: 4b11 ldr r3, [pc, #68] ; (8004c6c <xTimerGenericCommand+0x98>)
|
||
|
|
8004c28: 6818 ldr r0, [r3, #0]
|
||
|
|
8004c2a: f107 0110 add.w r1, r7, #16
|
||
|
|
8004c2e: 2300 movs r3, #0
|
||
|
|
8004c30: 6b3a ldr r2, [r7, #48] ; 0x30
|
||
|
|
8004c32: f7fe fc6d bl 8003510 <xQueueGenericSend>
|
||
|
|
8004c36: 6278 str r0, [r7, #36] ; 0x24
|
||
|
|
8004c38: e012 b.n 8004c60 <xTimerGenericCommand+0x8c>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
|
||
|
|
8004c3a: 4b0c ldr r3, [pc, #48] ; (8004c6c <xTimerGenericCommand+0x98>)
|
||
|
|
8004c3c: 6818 ldr r0, [r3, #0]
|
||
|
|
8004c3e: f107 0110 add.w r1, r7, #16
|
||
|
|
8004c42: 2300 movs r3, #0
|
||
|
|
8004c44: 2200 movs r2, #0
|
||
|
|
8004c46: f7fe fc63 bl 8003510 <xQueueGenericSend>
|
||
|
|
8004c4a: 6278 str r0, [r7, #36] ; 0x24
|
||
|
|
8004c4c: e008 b.n 8004c60 <xTimerGenericCommand+0x8c>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
|
||
|
|
8004c4e: 4b07 ldr r3, [pc, #28] ; (8004c6c <xTimerGenericCommand+0x98>)
|
||
|
|
8004c50: 6818 ldr r0, [r3, #0]
|
||
|
|
8004c52: f107 0110 add.w r1, r7, #16
|
||
|
|
8004c56: 2300 movs r3, #0
|
||
|
|
8004c58: 683a ldr r2, [r7, #0]
|
||
|
|
8004c5a: f7fe fd57 bl 800370c <xQueueGenericSendFromISR>
|
||
|
|
8004c5e: 6278 str r0, [r7, #36] ; 0x24
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
return xReturn;
|
||
|
|
8004c60: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
}
|
||
|
|
8004c62: 4618 mov r0, r3
|
||
|
|
8004c64: 3728 adds r7, #40 ; 0x28
|
||
|
|
8004c66: 46bd mov sp, r7
|
||
|
|
8004c68: bd80 pop {r7, pc}
|
||
|
|
8004c6a: bf00 nop
|
||
|
|
8004c6c: 20003cf8 .word 0x20003cf8
|
||
|
|
|
||
|
|
08004c70 <prvProcessExpiredTimer>:
|
||
|
|
return pxTimer->pcTimerName;
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
|
||
|
|
{
|
||
|
|
8004c70: b580 push {r7, lr}
|
||
|
|
8004c72: b088 sub sp, #32
|
||
|
|
8004c74: af02 add r7, sp, #8
|
||
|
|
8004c76: 6078 str r0, [r7, #4]
|
||
|
|
8004c78: 6039 str r1, [r7, #0]
|
||
|
|
BaseType_t xResult;
|
||
|
|
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
||
|
|
8004c7a: 4b22 ldr r3, [pc, #136] ; (8004d04 <prvProcessExpiredTimer+0x94>)
|
||
|
|
8004c7c: 681b ldr r3, [r3, #0]
|
||
|
|
8004c7e: 68db ldr r3, [r3, #12]
|
||
|
|
8004c80: 68db ldr r3, [r3, #12]
|
||
|
|
8004c82: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* Remove the timer from the list of active timers. A check has already
|
||
|
|
been performed to ensure the list is not empty. */
|
||
|
|
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
|
||
|
|
8004c84: 697b ldr r3, [r7, #20]
|
||
|
|
8004c86: 3304 adds r3, #4
|
||
|
|
8004c88: 4618 mov r0, r3
|
||
|
|
8004c8a: f7fe fb13 bl 80032b4 <uxListRemove>
|
||
|
|
traceTIMER_EXPIRED( pxTimer );
|
||
|
|
|
||
|
|
/* If the timer is an auto-reload timer then calculate the next
|
||
|
|
expiry time and re-insert the timer in the list of active timers. */
|
||
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
|
||
|
|
8004c8e: 697b ldr r3, [r7, #20]
|
||
|
|
8004c90: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
|
||
|
|
8004c94: f003 0304 and.w r3, r3, #4
|
||
|
|
8004c98: 2b00 cmp r3, #0
|
||
|
|
8004c9a: d022 beq.n 8004ce2 <prvProcessExpiredTimer+0x72>
|
||
|
|
{
|
||
|
|
/* The timer is inserted into a list using a time relative to anything
|
||
|
|
other than the current time. It will therefore be inserted into the
|
||
|
|
correct list relative to the time this task thinks it is now. */
|
||
|
|
if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
|
||
|
|
8004c9c: 697b ldr r3, [r7, #20]
|
||
|
|
8004c9e: 699a ldr r2, [r3, #24]
|
||
|
|
8004ca0: 687b ldr r3, [r7, #4]
|
||
|
|
8004ca2: 18d1 adds r1, r2, r3
|
||
|
|
8004ca4: 687b ldr r3, [r7, #4]
|
||
|
|
8004ca6: 683a ldr r2, [r7, #0]
|
||
|
|
8004ca8: 6978 ldr r0, [r7, #20]
|
||
|
|
8004caa: f000 f8d1 bl 8004e50 <prvInsertTimerInActiveList>
|
||
|
|
8004cae: 4603 mov r3, r0
|
||
|
|
8004cb0: 2b00 cmp r3, #0
|
||
|
|
8004cb2: d01f beq.n 8004cf4 <prvProcessExpiredTimer+0x84>
|
||
|
|
{
|
||
|
|
/* The timer expired before it was added to the active timer
|
||
|
|
list. Reload it now. */
|
||
|
|
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
|
||
|
|
8004cb4: 2300 movs r3, #0
|
||
|
|
8004cb6: 9300 str r3, [sp, #0]
|
||
|
|
8004cb8: 2300 movs r3, #0
|
||
|
|
8004cba: 687a ldr r2, [r7, #4]
|
||
|
|
8004cbc: 2100 movs r1, #0
|
||
|
|
8004cbe: 6978 ldr r0, [r7, #20]
|
||
|
|
8004cc0: f7ff ff88 bl 8004bd4 <xTimerGenericCommand>
|
||
|
|
8004cc4: 6138 str r0, [r7, #16]
|
||
|
|
configASSERT( xResult );
|
||
|
|
8004cc6: 693b ldr r3, [r7, #16]
|
||
|
|
8004cc8: 2b00 cmp r3, #0
|
||
|
|
8004cca: d113 bne.n 8004cf4 <prvProcessExpiredTimer+0x84>
|
||
|
|
__asm volatile
|
||
|
|
8004ccc: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004cd0: f383 8811 msr BASEPRI, r3
|
||
|
|
8004cd4: f3bf 8f6f isb sy
|
||
|
|
8004cd8: f3bf 8f4f dsb sy
|
||
|
|
8004cdc: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
8004cde: bf00 nop
|
||
|
|
8004ce0: e7fe b.n 8004ce0 <prvProcessExpiredTimer+0x70>
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
|
||
|
|
8004ce2: 697b ldr r3, [r7, #20]
|
||
|
|
8004ce4: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
|
||
|
|
8004ce8: f023 0301 bic.w r3, r3, #1
|
||
|
|
8004cec: b2da uxtb r2, r3
|
||
|
|
8004cee: 697b ldr r3, [r7, #20]
|
||
|
|
8004cf0: f883 2028 strb.w r2, [r3, #40] ; 0x28
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Call the timer callback. */
|
||
|
|
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
|
||
|
|
8004cf4: 697b ldr r3, [r7, #20]
|
||
|
|
8004cf6: 6a1b ldr r3, [r3, #32]
|
||
|
|
8004cf8: 6978 ldr r0, [r7, #20]
|
||
|
|
8004cfa: 4798 blx r3
|
||
|
|
}
|
||
|
|
8004cfc: bf00 nop
|
||
|
|
8004cfe: 3718 adds r7, #24
|
||
|
|
8004d00: 46bd mov sp, r7
|
||
|
|
8004d02: bd80 pop {r7, pc}
|
||
|
|
8004d04: 20003cf0 .word 0x20003cf0
|
||
|
|
|
||
|
|
08004d08 <prvTimerTask>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static portTASK_FUNCTION( prvTimerTask, pvParameters )
|
||
|
|
{
|
||
|
|
8004d08: b580 push {r7, lr}
|
||
|
|
8004d0a: b084 sub sp, #16
|
||
|
|
8004d0c: af00 add r7, sp, #0
|
||
|
|
8004d0e: 6078 str r0, [r7, #4]
|
||
|
|
|
||
|
|
for( ;; )
|
||
|
|
{
|
||
|
|
/* Query the timers list to see if it contains any timers, and if so,
|
||
|
|
obtain the time at which the next timer will expire. */
|
||
|
|
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
|
||
|
|
8004d10: f107 0308 add.w r3, r7, #8
|
||
|
|
8004d14: 4618 mov r0, r3
|
||
|
|
8004d16: f000 f857 bl 8004dc8 <prvGetNextExpireTime>
|
||
|
|
8004d1a: 60f8 str r0, [r7, #12]
|
||
|
|
|
||
|
|
/* If a timer has expired, process it. Otherwise, block this task
|
||
|
|
until either a timer does expire, or a command is received. */
|
||
|
|
prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
|
||
|
|
8004d1c: 68bb ldr r3, [r7, #8]
|
||
|
|
8004d1e: 4619 mov r1, r3
|
||
|
|
8004d20: 68f8 ldr r0, [r7, #12]
|
||
|
|
8004d22: f000 f803 bl 8004d2c <prvProcessTimerOrBlockTask>
|
||
|
|
|
||
|
|
/* Empty the command queue. */
|
||
|
|
prvProcessReceivedCommands();
|
||
|
|
8004d26: f000 f8d5 bl 8004ed4 <prvProcessReceivedCommands>
|
||
|
|
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
|
||
|
|
8004d2a: e7f1 b.n 8004d10 <prvTimerTask+0x8>
|
||
|
|
|
||
|
|
08004d2c <prvProcessTimerOrBlockTask>:
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
|
||
|
|
{
|
||
|
|
8004d2c: b580 push {r7, lr}
|
||
|
|
8004d2e: b084 sub sp, #16
|
||
|
|
8004d30: af00 add r7, sp, #0
|
||
|
|
8004d32: 6078 str r0, [r7, #4]
|
||
|
|
8004d34: 6039 str r1, [r7, #0]
|
||
|
|
TickType_t xTimeNow;
|
||
|
|
BaseType_t xTimerListsWereSwitched;
|
||
|
|
|
||
|
|
vTaskSuspendAll();
|
||
|
|
8004d36: f7ff fa2f bl 8004198 <vTaskSuspendAll>
|
||
|
|
/* Obtain the time now to make an assessment as to whether the timer
|
||
|
|
has expired or not. If obtaining the time causes the lists to switch
|
||
|
|
then don't process this timer as any timers that remained in the list
|
||
|
|
when the lists were switched will have been processed within the
|
||
|
|
prvSampleTimeNow() function. */
|
||
|
|
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
|
||
|
|
8004d3a: f107 0308 add.w r3, r7, #8
|
||
|
|
8004d3e: 4618 mov r0, r3
|
||
|
|
8004d40: f000 f866 bl 8004e10 <prvSampleTimeNow>
|
||
|
|
8004d44: 60f8 str r0, [r7, #12]
|
||
|
|
if( xTimerListsWereSwitched == pdFALSE )
|
||
|
|
8004d46: 68bb ldr r3, [r7, #8]
|
||
|
|
8004d48: 2b00 cmp r3, #0
|
||
|
|
8004d4a: d130 bne.n 8004dae <prvProcessTimerOrBlockTask+0x82>
|
||
|
|
{
|
||
|
|
/* The tick count has not overflowed, has the timer expired? */
|
||
|
|
if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
|
||
|
|
8004d4c: 683b ldr r3, [r7, #0]
|
||
|
|
8004d4e: 2b00 cmp r3, #0
|
||
|
|
8004d50: d10a bne.n 8004d68 <prvProcessTimerOrBlockTask+0x3c>
|
||
|
|
8004d52: 687a ldr r2, [r7, #4]
|
||
|
|
8004d54: 68fb ldr r3, [r7, #12]
|
||
|
|
8004d56: 429a cmp r2, r3
|
||
|
|
8004d58: d806 bhi.n 8004d68 <prvProcessTimerOrBlockTask+0x3c>
|
||
|
|
{
|
||
|
|
( void ) xTaskResumeAll();
|
||
|
|
8004d5a: f7ff fa2b bl 80041b4 <xTaskResumeAll>
|
||
|
|
prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
|
||
|
|
8004d5e: 68f9 ldr r1, [r7, #12]
|
||
|
|
8004d60: 6878 ldr r0, [r7, #4]
|
||
|
|
8004d62: f7ff ff85 bl 8004c70 <prvProcessExpiredTimer>
|
||
|
|
else
|
||
|
|
{
|
||
|
|
( void ) xTaskResumeAll();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8004d66: e024 b.n 8004db2 <prvProcessTimerOrBlockTask+0x86>
|
||
|
|
if( xListWasEmpty != pdFALSE )
|
||
|
|
8004d68: 683b ldr r3, [r7, #0]
|
||
|
|
8004d6a: 2b00 cmp r3, #0
|
||
|
|
8004d6c: d008 beq.n 8004d80 <prvProcessTimerOrBlockTask+0x54>
|
||
|
|
xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
|
||
|
|
8004d6e: 4b13 ldr r3, [pc, #76] ; (8004dbc <prvProcessTimerOrBlockTask+0x90>)
|
||
|
|
8004d70: 681b ldr r3, [r3, #0]
|
||
|
|
8004d72: 681b ldr r3, [r3, #0]
|
||
|
|
8004d74: 2b00 cmp r3, #0
|
||
|
|
8004d76: d101 bne.n 8004d7c <prvProcessTimerOrBlockTask+0x50>
|
||
|
|
8004d78: 2301 movs r3, #1
|
||
|
|
8004d7a: e000 b.n 8004d7e <prvProcessTimerOrBlockTask+0x52>
|
||
|
|
8004d7c: 2300 movs r3, #0
|
||
|
|
8004d7e: 603b str r3, [r7, #0]
|
||
|
|
vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
|
||
|
|
8004d80: 4b0f ldr r3, [pc, #60] ; (8004dc0 <prvProcessTimerOrBlockTask+0x94>)
|
||
|
|
8004d82: 6818 ldr r0, [r3, #0]
|
||
|
|
8004d84: 687a ldr r2, [r7, #4]
|
||
|
|
8004d86: 68fb ldr r3, [r7, #12]
|
||
|
|
8004d88: 1ad3 subs r3, r2, r3
|
||
|
|
8004d8a: 683a ldr r2, [r7, #0]
|
||
|
|
8004d8c: 4619 mov r1, r3
|
||
|
|
8004d8e: f7fe ff73 bl 8003c78 <vQueueWaitForMessageRestricted>
|
||
|
|
if( xTaskResumeAll() == pdFALSE )
|
||
|
|
8004d92: f7ff fa0f bl 80041b4 <xTaskResumeAll>
|
||
|
|
8004d96: 4603 mov r3, r0
|
||
|
|
8004d98: 2b00 cmp r3, #0
|
||
|
|
8004d9a: d10a bne.n 8004db2 <prvProcessTimerOrBlockTask+0x86>
|
||
|
|
portYIELD_WITHIN_API();
|
||
|
|
8004d9c: 4b09 ldr r3, [pc, #36] ; (8004dc4 <prvProcessTimerOrBlockTask+0x98>)
|
||
|
|
8004d9e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
8004da2: 601a str r2, [r3, #0]
|
||
|
|
8004da4: f3bf 8f4f dsb sy
|
||
|
|
8004da8: f3bf 8f6f isb sy
|
||
|
|
}
|
||
|
|
8004dac: e001 b.n 8004db2 <prvProcessTimerOrBlockTask+0x86>
|
||
|
|
( void ) xTaskResumeAll();
|
||
|
|
8004dae: f7ff fa01 bl 80041b4 <xTaskResumeAll>
|
||
|
|
}
|
||
|
|
8004db2: bf00 nop
|
||
|
|
8004db4: 3710 adds r7, #16
|
||
|
|
8004db6: 46bd mov sp, r7
|
||
|
|
8004db8: bd80 pop {r7, pc}
|
||
|
|
8004dba: bf00 nop
|
||
|
|
8004dbc: 20003cf4 .word 0x20003cf4
|
||
|
|
8004dc0: 20003cf8 .word 0x20003cf8
|
||
|
|
8004dc4: e000ed04 .word 0xe000ed04
|
||
|
|
|
||
|
|
08004dc8 <prvGetNextExpireTime>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
|
||
|
|
{
|
||
|
|
8004dc8: b480 push {r7}
|
||
|
|
8004dca: b085 sub sp, #20
|
||
|
|
8004dcc: af00 add r7, sp, #0
|
||
|
|
8004dce: 6078 str r0, [r7, #4]
|
||
|
|
the timer with the nearest expiry time will expire. If there are no
|
||
|
|
active timers then just set the next expire time to 0. That will cause
|
||
|
|
this task to unblock when the tick count overflows, at which point the
|
||
|
|
timer lists will be switched and the next expiry time can be
|
||
|
|
re-assessed. */
|
||
|
|
*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
|
||
|
|
8004dd0: 4b0e ldr r3, [pc, #56] ; (8004e0c <prvGetNextExpireTime+0x44>)
|
||
|
|
8004dd2: 681b ldr r3, [r3, #0]
|
||
|
|
8004dd4: 681b ldr r3, [r3, #0]
|
||
|
|
8004dd6: 2b00 cmp r3, #0
|
||
|
|
8004dd8: d101 bne.n 8004dde <prvGetNextExpireTime+0x16>
|
||
|
|
8004dda: 2201 movs r2, #1
|
||
|
|
8004ddc: e000 b.n 8004de0 <prvGetNextExpireTime+0x18>
|
||
|
|
8004dde: 2200 movs r2, #0
|
||
|
|
8004de0: 687b ldr r3, [r7, #4]
|
||
|
|
8004de2: 601a str r2, [r3, #0]
|
||
|
|
if( *pxListWasEmpty == pdFALSE )
|
||
|
|
8004de4: 687b ldr r3, [r7, #4]
|
||
|
|
8004de6: 681b ldr r3, [r3, #0]
|
||
|
|
8004de8: 2b00 cmp r3, #0
|
||
|
|
8004dea: d105 bne.n 8004df8 <prvGetNextExpireTime+0x30>
|
||
|
|
{
|
||
|
|
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
|
||
|
|
8004dec: 4b07 ldr r3, [pc, #28] ; (8004e0c <prvGetNextExpireTime+0x44>)
|
||
|
|
8004dee: 681b ldr r3, [r3, #0]
|
||
|
|
8004df0: 68db ldr r3, [r3, #12]
|
||
|
|
8004df2: 681b ldr r3, [r3, #0]
|
||
|
|
8004df4: 60fb str r3, [r7, #12]
|
||
|
|
8004df6: e001 b.n 8004dfc <prvGetNextExpireTime+0x34>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Ensure the task unblocks when the tick count rolls over. */
|
||
|
|
xNextExpireTime = ( TickType_t ) 0U;
|
||
|
|
8004df8: 2300 movs r3, #0
|
||
|
|
8004dfa: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
|
||
|
|
return xNextExpireTime;
|
||
|
|
8004dfc: 68fb ldr r3, [r7, #12]
|
||
|
|
}
|
||
|
|
8004dfe: 4618 mov r0, r3
|
||
|
|
8004e00: 3714 adds r7, #20
|
||
|
|
8004e02: 46bd mov sp, r7
|
||
|
|
8004e04: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8004e08: 4770 bx lr
|
||
|
|
8004e0a: bf00 nop
|
||
|
|
8004e0c: 20003cf0 .word 0x20003cf0
|
||
|
|
|
||
|
|
08004e10 <prvSampleTimeNow>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
|
||
|
|
{
|
||
|
|
8004e10: b580 push {r7, lr}
|
||
|
|
8004e12: b084 sub sp, #16
|
||
|
|
8004e14: af00 add r7, sp, #0
|
||
|
|
8004e16: 6078 str r0, [r7, #4]
|
||
|
|
TickType_t xTimeNow;
|
||
|
|
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
|
||
|
|
|
||
|
|
xTimeNow = xTaskGetTickCount();
|
||
|
|
8004e18: f7ff fa6a bl 80042f0 <xTaskGetTickCount>
|
||
|
|
8004e1c: 60f8 str r0, [r7, #12]
|
||
|
|
|
||
|
|
if( xTimeNow < xLastTime )
|
||
|
|
8004e1e: 4b0b ldr r3, [pc, #44] ; (8004e4c <prvSampleTimeNow+0x3c>)
|
||
|
|
8004e20: 681b ldr r3, [r3, #0]
|
||
|
|
8004e22: 68fa ldr r2, [r7, #12]
|
||
|
|
8004e24: 429a cmp r2, r3
|
||
|
|
8004e26: d205 bcs.n 8004e34 <prvSampleTimeNow+0x24>
|
||
|
|
{
|
||
|
|
prvSwitchTimerLists();
|
||
|
|
8004e28: f000 f936 bl 8005098 <prvSwitchTimerLists>
|
||
|
|
*pxTimerListsWereSwitched = pdTRUE;
|
||
|
|
8004e2c: 687b ldr r3, [r7, #4]
|
||
|
|
8004e2e: 2201 movs r2, #1
|
||
|
|
8004e30: 601a str r2, [r3, #0]
|
||
|
|
8004e32: e002 b.n 8004e3a <prvSampleTimeNow+0x2a>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
*pxTimerListsWereSwitched = pdFALSE;
|
||
|
|
8004e34: 687b ldr r3, [r7, #4]
|
||
|
|
8004e36: 2200 movs r2, #0
|
||
|
|
8004e38: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
|
||
|
|
xLastTime = xTimeNow;
|
||
|
|
8004e3a: 4a04 ldr r2, [pc, #16] ; (8004e4c <prvSampleTimeNow+0x3c>)
|
||
|
|
8004e3c: 68fb ldr r3, [r7, #12]
|
||
|
|
8004e3e: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
return xTimeNow;
|
||
|
|
8004e40: 68fb ldr r3, [r7, #12]
|
||
|
|
}
|
||
|
|
8004e42: 4618 mov r0, r3
|
||
|
|
8004e44: 3710 adds r7, #16
|
||
|
|
8004e46: 46bd mov sp, r7
|
||
|
|
8004e48: bd80 pop {r7, pc}
|
||
|
|
8004e4a: bf00 nop
|
||
|
|
8004e4c: 20003d00 .word 0x20003d00
|
||
|
|
|
||
|
|
08004e50 <prvInsertTimerInActiveList>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
|
||
|
|
{
|
||
|
|
8004e50: b580 push {r7, lr}
|
||
|
|
8004e52: b086 sub sp, #24
|
||
|
|
8004e54: af00 add r7, sp, #0
|
||
|
|
8004e56: 60f8 str r0, [r7, #12]
|
||
|
|
8004e58: 60b9 str r1, [r7, #8]
|
||
|
|
8004e5a: 607a str r2, [r7, #4]
|
||
|
|
8004e5c: 603b str r3, [r7, #0]
|
||
|
|
BaseType_t xProcessTimerNow = pdFALSE;
|
||
|
|
8004e5e: 2300 movs r3, #0
|
||
|
|
8004e60: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
|
||
|
|
8004e62: 68fb ldr r3, [r7, #12]
|
||
|
|
8004e64: 68ba ldr r2, [r7, #8]
|
||
|
|
8004e66: 605a str r2, [r3, #4]
|
||
|
|
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
|
||
|
|
8004e68: 68fb ldr r3, [r7, #12]
|
||
|
|
8004e6a: 68fa ldr r2, [r7, #12]
|
||
|
|
8004e6c: 611a str r2, [r3, #16]
|
||
|
|
|
||
|
|
if( xNextExpiryTime <= xTimeNow )
|
||
|
|
8004e6e: 68ba ldr r2, [r7, #8]
|
||
|
|
8004e70: 687b ldr r3, [r7, #4]
|
||
|
|
8004e72: 429a cmp r2, r3
|
||
|
|
8004e74: d812 bhi.n 8004e9c <prvInsertTimerInActiveList+0x4c>
|
||
|
|
{
|
||
|
|
/* Has the expiry time elapsed between the command to start/reset a
|
||
|
|
timer was issued, and the time the command was processed? */
|
||
|
|
if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
||
|
|
8004e76: 687a ldr r2, [r7, #4]
|
||
|
|
8004e78: 683b ldr r3, [r7, #0]
|
||
|
|
8004e7a: 1ad2 subs r2, r2, r3
|
||
|
|
8004e7c: 68fb ldr r3, [r7, #12]
|
||
|
|
8004e7e: 699b ldr r3, [r3, #24]
|
||
|
|
8004e80: 429a cmp r2, r3
|
||
|
|
8004e82: d302 bcc.n 8004e8a <prvInsertTimerInActiveList+0x3a>
|
||
|
|
{
|
||
|
|
/* The time between a command being issued and the command being
|
||
|
|
processed actually exceeds the timers period. */
|
||
|
|
xProcessTimerNow = pdTRUE;
|
||
|
|
8004e84: 2301 movs r3, #1
|
||
|
|
8004e86: 617b str r3, [r7, #20]
|
||
|
|
8004e88: e01b b.n 8004ec2 <prvInsertTimerInActiveList+0x72>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
|
||
|
|
8004e8a: 4b10 ldr r3, [pc, #64] ; (8004ecc <prvInsertTimerInActiveList+0x7c>)
|
||
|
|
8004e8c: 681a ldr r2, [r3, #0]
|
||
|
|
8004e8e: 68fb ldr r3, [r7, #12]
|
||
|
|
8004e90: 3304 adds r3, #4
|
||
|
|
8004e92: 4619 mov r1, r3
|
||
|
|
8004e94: 4610 mov r0, r2
|
||
|
|
8004e96: f7fe f9d4 bl 8003242 <vListInsert>
|
||
|
|
8004e9a: e012 b.n 8004ec2 <prvInsertTimerInActiveList+0x72>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
|
||
|
|
8004e9c: 687a ldr r2, [r7, #4]
|
||
|
|
8004e9e: 683b ldr r3, [r7, #0]
|
||
|
|
8004ea0: 429a cmp r2, r3
|
||
|
|
8004ea2: d206 bcs.n 8004eb2 <prvInsertTimerInActiveList+0x62>
|
||
|
|
8004ea4: 68ba ldr r2, [r7, #8]
|
||
|
|
8004ea6: 683b ldr r3, [r7, #0]
|
||
|
|
8004ea8: 429a cmp r2, r3
|
||
|
|
8004eaa: d302 bcc.n 8004eb2 <prvInsertTimerInActiveList+0x62>
|
||
|
|
{
|
||
|
|
/* If, since the command was issued, the tick count has overflowed
|
||
|
|
but the expiry time has not, then the timer must have already passed
|
||
|
|
its expiry time and should be processed immediately. */
|
||
|
|
xProcessTimerNow = pdTRUE;
|
||
|
|
8004eac: 2301 movs r3, #1
|
||
|
|
8004eae: 617b str r3, [r7, #20]
|
||
|
|
8004eb0: e007 b.n 8004ec2 <prvInsertTimerInActiveList+0x72>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
|
||
|
|
8004eb2: 4b07 ldr r3, [pc, #28] ; (8004ed0 <prvInsertTimerInActiveList+0x80>)
|
||
|
|
8004eb4: 681a ldr r2, [r3, #0]
|
||
|
|
8004eb6: 68fb ldr r3, [r7, #12]
|
||
|
|
8004eb8: 3304 adds r3, #4
|
||
|
|
8004eba: 4619 mov r1, r3
|
||
|
|
8004ebc: 4610 mov r0, r2
|
||
|
|
8004ebe: f7fe f9c0 bl 8003242 <vListInsert>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return xProcessTimerNow;
|
||
|
|
8004ec2: 697b ldr r3, [r7, #20]
|
||
|
|
}
|
||
|
|
8004ec4: 4618 mov r0, r3
|
||
|
|
8004ec6: 3718 adds r7, #24
|
||
|
|
8004ec8: 46bd mov sp, r7
|
||
|
|
8004eca: bd80 pop {r7, pc}
|
||
|
|
8004ecc: 20003cf4 .word 0x20003cf4
|
||
|
|
8004ed0: 20003cf0 .word 0x20003cf0
|
||
|
|
|
||
|
|
08004ed4 <prvProcessReceivedCommands>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvProcessReceivedCommands( void )
|
||
|
|
{
|
||
|
|
8004ed4: b580 push {r7, lr}
|
||
|
|
8004ed6: b08e sub sp, #56 ; 0x38
|
||
|
|
8004ed8: af02 add r7, sp, #8
|
||
|
|
DaemonTaskMessage_t xMessage;
|
||
|
|
Timer_t *pxTimer;
|
||
|
|
BaseType_t xTimerListsWereSwitched, xResult;
|
||
|
|
TickType_t xTimeNow;
|
||
|
|
|
||
|
|
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
|
||
|
|
8004eda: e0ca b.n 8005072 <prvProcessReceivedCommands+0x19e>
|
||
|
|
{
|
||
|
|
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
|
||
|
|
{
|
||
|
|
/* Negative commands are pended function calls rather than timer
|
||
|
|
commands. */
|
||
|
|
if( xMessage.xMessageID < ( BaseType_t ) 0 )
|
||
|
|
8004edc: 687b ldr r3, [r7, #4]
|
||
|
|
8004ede: 2b00 cmp r3, #0
|
||
|
|
8004ee0: da18 bge.n 8004f14 <prvProcessReceivedCommands+0x40>
|
||
|
|
{
|
||
|
|
const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
|
||
|
|
8004ee2: 1d3b adds r3, r7, #4
|
||
|
|
8004ee4: 3304 adds r3, #4
|
||
|
|
8004ee6: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
|
||
|
|
/* The timer uses the xCallbackParameters member to request a
|
||
|
|
callback be executed. Check the callback is not NULL. */
|
||
|
|
configASSERT( pxCallback );
|
||
|
|
8004ee8: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8004eea: 2b00 cmp r3, #0
|
||
|
|
8004eec: d10a bne.n 8004f04 <prvProcessReceivedCommands+0x30>
|
||
|
|
__asm volatile
|
||
|
|
8004eee: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004ef2: f383 8811 msr BASEPRI, r3
|
||
|
|
8004ef6: f3bf 8f6f isb sy
|
||
|
|
8004efa: f3bf 8f4f dsb sy
|
||
|
|
8004efe: 61fb str r3, [r7, #28]
|
||
|
|
}
|
||
|
|
8004f00: bf00 nop
|
||
|
|
8004f02: e7fe b.n 8004f02 <prvProcessReceivedCommands+0x2e>
|
||
|
|
|
||
|
|
/* Call the function. */
|
||
|
|
pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
|
||
|
|
8004f04: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8004f06: 681b ldr r3, [r3, #0]
|
||
|
|
8004f08: 6afa ldr r2, [r7, #44] ; 0x2c
|
||
|
|
8004f0a: 6850 ldr r0, [r2, #4]
|
||
|
|
8004f0c: 6afa ldr r2, [r7, #44] ; 0x2c
|
||
|
|
8004f0e: 6892 ldr r2, [r2, #8]
|
||
|
|
8004f10: 4611 mov r1, r2
|
||
|
|
8004f12: 4798 blx r3
|
||
|
|
}
|
||
|
|
#endif /* INCLUDE_xTimerPendFunctionCall */
|
||
|
|
|
||
|
|
/* Commands that are positive are timer commands rather than pended
|
||
|
|
function calls. */
|
||
|
|
if( xMessage.xMessageID >= ( BaseType_t ) 0 )
|
||
|
|
8004f14: 687b ldr r3, [r7, #4]
|
||
|
|
8004f16: 2b00 cmp r3, #0
|
||
|
|
8004f18: f2c0 80aa blt.w 8005070 <prvProcessReceivedCommands+0x19c>
|
||
|
|
{
|
||
|
|
/* The messages uses the xTimerParameters member to work on a
|
||
|
|
software timer. */
|
||
|
|
pxTimer = xMessage.u.xTimerParameters.pxTimer;
|
||
|
|
8004f1c: 68fb ldr r3, [r7, #12]
|
||
|
|
8004f1e: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
|
||
|
|
if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
|
||
|
|
8004f20: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004f22: 695b ldr r3, [r3, #20]
|
||
|
|
8004f24: 2b00 cmp r3, #0
|
||
|
|
8004f26: d004 beq.n 8004f32 <prvProcessReceivedCommands+0x5e>
|
||
|
|
{
|
||
|
|
/* The timer is in a list, remove it. */
|
||
|
|
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
|
||
|
|
8004f28: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004f2a: 3304 adds r3, #4
|
||
|
|
8004f2c: 4618 mov r0, r3
|
||
|
|
8004f2e: f7fe f9c1 bl 80032b4 <uxListRemove>
|
||
|
|
it must be present in the function call. prvSampleTimeNow() must be
|
||
|
|
called after the message is received from xTimerQueue so there is no
|
||
|
|
possibility of a higher priority task adding a message to the message
|
||
|
|
queue with a time that is ahead of the timer daemon task (because it
|
||
|
|
pre-empted the timer daemon task after the xTimeNow value was set). */
|
||
|
|
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
|
||
|
|
8004f32: 463b mov r3, r7
|
||
|
|
8004f34: 4618 mov r0, r3
|
||
|
|
8004f36: f7ff ff6b bl 8004e10 <prvSampleTimeNow>
|
||
|
|
8004f3a: 6278 str r0, [r7, #36] ; 0x24
|
||
|
|
|
||
|
|
switch( xMessage.xMessageID )
|
||
|
|
8004f3c: 687b ldr r3, [r7, #4]
|
||
|
|
8004f3e: 2b09 cmp r3, #9
|
||
|
|
8004f40: f200 8097 bhi.w 8005072 <prvProcessReceivedCommands+0x19e>
|
||
|
|
8004f44: a201 add r2, pc, #4 ; (adr r2, 8004f4c <prvProcessReceivedCommands+0x78>)
|
||
|
|
8004f46: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
||
|
|
8004f4a: bf00 nop
|
||
|
|
8004f4c: 08004f75 .word 0x08004f75
|
||
|
|
8004f50: 08004f75 .word 0x08004f75
|
||
|
|
8004f54: 08004f75 .word 0x08004f75
|
||
|
|
8004f58: 08004fe9 .word 0x08004fe9
|
||
|
|
8004f5c: 08004ffd .word 0x08004ffd
|
||
|
|
8004f60: 08005047 .word 0x08005047
|
||
|
|
8004f64: 08004f75 .word 0x08004f75
|
||
|
|
8004f68: 08004f75 .word 0x08004f75
|
||
|
|
8004f6c: 08004fe9 .word 0x08004fe9
|
||
|
|
8004f70: 08004ffd .word 0x08004ffd
|
||
|
|
case tmrCOMMAND_START_FROM_ISR :
|
||
|
|
case tmrCOMMAND_RESET :
|
||
|
|
case tmrCOMMAND_RESET_FROM_ISR :
|
||
|
|
case tmrCOMMAND_START_DONT_TRACE :
|
||
|
|
/* Start or restart a timer. */
|
||
|
|
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
|
||
|
|
8004f74: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004f76: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
|
||
|
|
8004f7a: f043 0301 orr.w r3, r3, #1
|
||
|
|
8004f7e: b2da uxtb r2, r3
|
||
|
|
8004f80: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004f82: f883 2028 strb.w r2, [r3, #40] ; 0x28
|
||
|
|
if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
|
||
|
|
8004f86: 68ba ldr r2, [r7, #8]
|
||
|
|
8004f88: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004f8a: 699b ldr r3, [r3, #24]
|
||
|
|
8004f8c: 18d1 adds r1, r2, r3
|
||
|
|
8004f8e: 68bb ldr r3, [r7, #8]
|
||
|
|
8004f90: 6a7a ldr r2, [r7, #36] ; 0x24
|
||
|
|
8004f92: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
8004f94: f7ff ff5c bl 8004e50 <prvInsertTimerInActiveList>
|
||
|
|
8004f98: 4603 mov r3, r0
|
||
|
|
8004f9a: 2b00 cmp r3, #0
|
||
|
|
8004f9c: d069 beq.n 8005072 <prvProcessReceivedCommands+0x19e>
|
||
|
|
{
|
||
|
|
/* The timer expired before it was added to the active
|
||
|
|
timer list. Process it now. */
|
||
|
|
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
|
||
|
|
8004f9e: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004fa0: 6a1b ldr r3, [r3, #32]
|
||
|
|
8004fa2: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
8004fa4: 4798 blx r3
|
||
|
|
traceTIMER_EXPIRED( pxTimer );
|
||
|
|
|
||
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
|
||
|
|
8004fa6: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004fa8: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
|
||
|
|
8004fac: f003 0304 and.w r3, r3, #4
|
||
|
|
8004fb0: 2b00 cmp r3, #0
|
||
|
|
8004fb2: d05e beq.n 8005072 <prvProcessReceivedCommands+0x19e>
|
||
|
|
{
|
||
|
|
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
|
||
|
|
8004fb4: 68ba ldr r2, [r7, #8]
|
||
|
|
8004fb6: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004fb8: 699b ldr r3, [r3, #24]
|
||
|
|
8004fba: 441a add r2, r3
|
||
|
|
8004fbc: 2300 movs r3, #0
|
||
|
|
8004fbe: 9300 str r3, [sp, #0]
|
||
|
|
8004fc0: 2300 movs r3, #0
|
||
|
|
8004fc2: 2100 movs r1, #0
|
||
|
|
8004fc4: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
8004fc6: f7ff fe05 bl 8004bd4 <xTimerGenericCommand>
|
||
|
|
8004fca: 6238 str r0, [r7, #32]
|
||
|
|
configASSERT( xResult );
|
||
|
|
8004fcc: 6a3b ldr r3, [r7, #32]
|
||
|
|
8004fce: 2b00 cmp r3, #0
|
||
|
|
8004fd0: d14f bne.n 8005072 <prvProcessReceivedCommands+0x19e>
|
||
|
|
__asm volatile
|
||
|
|
8004fd2: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8004fd6: f383 8811 msr BASEPRI, r3
|
||
|
|
8004fda: f3bf 8f6f isb sy
|
||
|
|
8004fde: f3bf 8f4f dsb sy
|
||
|
|
8004fe2: 61bb str r3, [r7, #24]
|
||
|
|
}
|
||
|
|
8004fe4: bf00 nop
|
||
|
|
8004fe6: e7fe b.n 8004fe6 <prvProcessReceivedCommands+0x112>
|
||
|
|
break;
|
||
|
|
|
||
|
|
case tmrCOMMAND_STOP :
|
||
|
|
case tmrCOMMAND_STOP_FROM_ISR :
|
||
|
|
/* The timer has already been removed from the active list. */
|
||
|
|
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
|
||
|
|
8004fe8: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004fea: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
|
||
|
|
8004fee: f023 0301 bic.w r3, r3, #1
|
||
|
|
8004ff2: b2da uxtb r2, r3
|
||
|
|
8004ff4: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004ff6: f883 2028 strb.w r2, [r3, #40] ; 0x28
|
||
|
|
break;
|
||
|
|
8004ffa: e03a b.n 8005072 <prvProcessReceivedCommands+0x19e>
|
||
|
|
|
||
|
|
case tmrCOMMAND_CHANGE_PERIOD :
|
||
|
|
case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
|
||
|
|
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
|
||
|
|
8004ffc: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8004ffe: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
|
||
|
|
8005002: f043 0301 orr.w r3, r3, #1
|
||
|
|
8005006: b2da uxtb r2, r3
|
||
|
|
8005008: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
800500a: f883 2028 strb.w r2, [r3, #40] ; 0x28
|
||
|
|
pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
|
||
|
|
800500e: 68ba ldr r2, [r7, #8]
|
||
|
|
8005010: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8005012: 619a str r2, [r3, #24]
|
||
|
|
configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
|
||
|
|
8005014: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8005016: 699b ldr r3, [r3, #24]
|
||
|
|
8005018: 2b00 cmp r3, #0
|
||
|
|
800501a: d10a bne.n 8005032 <prvProcessReceivedCommands+0x15e>
|
||
|
|
__asm volatile
|
||
|
|
800501c: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005020: f383 8811 msr BASEPRI, r3
|
||
|
|
8005024: f3bf 8f6f isb sy
|
||
|
|
8005028: f3bf 8f4f dsb sy
|
||
|
|
800502c: 617b str r3, [r7, #20]
|
||
|
|
}
|
||
|
|
800502e: bf00 nop
|
||
|
|
8005030: e7fe b.n 8005030 <prvProcessReceivedCommands+0x15c>
|
||
|
|
be longer or shorter than the old one. The command time is
|
||
|
|
therefore set to the current time, and as the period cannot
|
||
|
|
be zero the next expiry time can only be in the future,
|
||
|
|
meaning (unlike for the xTimerStart() case above) there is
|
||
|
|
no fail case that needs to be handled here. */
|
||
|
|
( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
|
||
|
|
8005032: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8005034: 699a ldr r2, [r3, #24]
|
||
|
|
8005036: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8005038: 18d1 adds r1, r2, r3
|
||
|
|
800503a: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
800503c: 6a7a ldr r2, [r7, #36] ; 0x24
|
||
|
|
800503e: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
8005040: f7ff ff06 bl 8004e50 <prvInsertTimerInActiveList>
|
||
|
|
break;
|
||
|
|
8005044: e015 b.n 8005072 <prvProcessReceivedCommands+0x19e>
|
||
|
|
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
||
|
|
{
|
||
|
|
/* The timer has already been removed from the active list,
|
||
|
|
just free up the memory if the memory was dynamically
|
||
|
|
allocated. */
|
||
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
|
||
|
|
8005046: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8005048: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
|
||
|
|
800504c: f003 0302 and.w r3, r3, #2
|
||
|
|
8005050: 2b00 cmp r3, #0
|
||
|
|
8005052: d103 bne.n 800505c <prvProcessReceivedCommands+0x188>
|
||
|
|
{
|
||
|
|
vPortFree( pxTimer );
|
||
|
|
8005054: 6ab8 ldr r0, [r7, #40] ; 0x28
|
||
|
|
8005056: f000 fbb3 bl 80057c0 <vPortFree>
|
||
|
|
800505a: e00a b.n 8005072 <prvProcessReceivedCommands+0x19e>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
|
||
|
|
800505c: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
800505e: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
|
||
|
|
8005062: f023 0301 bic.w r3, r3, #1
|
||
|
|
8005066: b2da uxtb r2, r3
|
||
|
|
8005068: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
800506a: f883 2028 strb.w r2, [r3, #40] ; 0x28
|
||
|
|
no need to free the memory - just mark the timer as
|
||
|
|
"not active". */
|
||
|
|
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
|
||
|
|
}
|
||
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
||
|
|
break;
|
||
|
|
800506e: e000 b.n 8005072 <prvProcessReceivedCommands+0x19e>
|
||
|
|
|
||
|
|
default :
|
||
|
|
/* Don't expect to get here. */
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8005070: bf00 nop
|
||
|
|
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
|
||
|
|
8005072: 4b08 ldr r3, [pc, #32] ; (8005094 <prvProcessReceivedCommands+0x1c0>)
|
||
|
|
8005074: 681b ldr r3, [r3, #0]
|
||
|
|
8005076: 1d39 adds r1, r7, #4
|
||
|
|
8005078: 2200 movs r2, #0
|
||
|
|
800507a: 4618 mov r0, r3
|
||
|
|
800507c: f7fe fbe2 bl 8003844 <xQueueReceive>
|
||
|
|
8005080: 4603 mov r3, r0
|
||
|
|
8005082: 2b00 cmp r3, #0
|
||
|
|
8005084: f47f af2a bne.w 8004edc <prvProcessReceivedCommands+0x8>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8005088: bf00 nop
|
||
|
|
800508a: bf00 nop
|
||
|
|
800508c: 3730 adds r7, #48 ; 0x30
|
||
|
|
800508e: 46bd mov sp, r7
|
||
|
|
8005090: bd80 pop {r7, pc}
|
||
|
|
8005092: bf00 nop
|
||
|
|
8005094: 20003cf8 .word 0x20003cf8
|
||
|
|
|
||
|
|
08005098 <prvSwitchTimerLists>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvSwitchTimerLists( void )
|
||
|
|
{
|
||
|
|
8005098: b580 push {r7, lr}
|
||
|
|
800509a: b088 sub sp, #32
|
||
|
|
800509c: af02 add r7, sp, #8
|
||
|
|
|
||
|
|
/* The tick count has overflowed. The timer lists must be switched.
|
||
|
|
If there are any timers still referenced from the current timer list
|
||
|
|
then they must have expired and should be processed before the lists
|
||
|
|
are switched. */
|
||
|
|
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
|
||
|
|
800509e: e048 b.n 8005132 <prvSwitchTimerLists+0x9a>
|
||
|
|
{
|
||
|
|
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
|
||
|
|
80050a0: 4b2d ldr r3, [pc, #180] ; (8005158 <prvSwitchTimerLists+0xc0>)
|
||
|
|
80050a2: 681b ldr r3, [r3, #0]
|
||
|
|
80050a4: 68db ldr r3, [r3, #12]
|
||
|
|
80050a6: 681b ldr r3, [r3, #0]
|
||
|
|
80050a8: 613b str r3, [r7, #16]
|
||
|
|
|
||
|
|
/* Remove the timer from the list. */
|
||
|
|
pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
||
|
|
80050aa: 4b2b ldr r3, [pc, #172] ; (8005158 <prvSwitchTimerLists+0xc0>)
|
||
|
|
80050ac: 681b ldr r3, [r3, #0]
|
||
|
|
80050ae: 68db ldr r3, [r3, #12]
|
||
|
|
80050b0: 68db ldr r3, [r3, #12]
|
||
|
|
80050b2: 60fb str r3, [r7, #12]
|
||
|
|
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
|
||
|
|
80050b4: 68fb ldr r3, [r7, #12]
|
||
|
|
80050b6: 3304 adds r3, #4
|
||
|
|
80050b8: 4618 mov r0, r3
|
||
|
|
80050ba: f7fe f8fb bl 80032b4 <uxListRemove>
|
||
|
|
traceTIMER_EXPIRED( pxTimer );
|
||
|
|
|
||
|
|
/* Execute its callback, then send a command to restart the timer if
|
||
|
|
it is an auto-reload timer. It cannot be restarted here as the lists
|
||
|
|
have not yet been switched. */
|
||
|
|
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
|
||
|
|
80050be: 68fb ldr r3, [r7, #12]
|
||
|
|
80050c0: 6a1b ldr r3, [r3, #32]
|
||
|
|
80050c2: 68f8 ldr r0, [r7, #12]
|
||
|
|
80050c4: 4798 blx r3
|
||
|
|
|
||
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
|
||
|
|
80050c6: 68fb ldr r3, [r7, #12]
|
||
|
|
80050c8: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
|
||
|
|
80050cc: f003 0304 and.w r3, r3, #4
|
||
|
|
80050d0: 2b00 cmp r3, #0
|
||
|
|
80050d2: d02e beq.n 8005132 <prvSwitchTimerLists+0x9a>
|
||
|
|
the timer going into the same timer list then it has already expired
|
||
|
|
and the timer should be re-inserted into the current list so it is
|
||
|
|
processed again within this loop. Otherwise a command should be sent
|
||
|
|
to restart the timer to ensure it is only inserted into a list after
|
||
|
|
the lists have been swapped. */
|
||
|
|
xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
|
||
|
|
80050d4: 68fb ldr r3, [r7, #12]
|
||
|
|
80050d6: 699b ldr r3, [r3, #24]
|
||
|
|
80050d8: 693a ldr r2, [r7, #16]
|
||
|
|
80050da: 4413 add r3, r2
|
||
|
|
80050dc: 60bb str r3, [r7, #8]
|
||
|
|
if( xReloadTime > xNextExpireTime )
|
||
|
|
80050de: 68ba ldr r2, [r7, #8]
|
||
|
|
80050e0: 693b ldr r3, [r7, #16]
|
||
|
|
80050e2: 429a cmp r2, r3
|
||
|
|
80050e4: d90e bls.n 8005104 <prvSwitchTimerLists+0x6c>
|
||
|
|
{
|
||
|
|
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
|
||
|
|
80050e6: 68fb ldr r3, [r7, #12]
|
||
|
|
80050e8: 68ba ldr r2, [r7, #8]
|
||
|
|
80050ea: 605a str r2, [r3, #4]
|
||
|
|
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
|
||
|
|
80050ec: 68fb ldr r3, [r7, #12]
|
||
|
|
80050ee: 68fa ldr r2, [r7, #12]
|
||
|
|
80050f0: 611a str r2, [r3, #16]
|
||
|
|
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
|
||
|
|
80050f2: 4b19 ldr r3, [pc, #100] ; (8005158 <prvSwitchTimerLists+0xc0>)
|
||
|
|
80050f4: 681a ldr r2, [r3, #0]
|
||
|
|
80050f6: 68fb ldr r3, [r7, #12]
|
||
|
|
80050f8: 3304 adds r3, #4
|
||
|
|
80050fa: 4619 mov r1, r3
|
||
|
|
80050fc: 4610 mov r0, r2
|
||
|
|
80050fe: f7fe f8a0 bl 8003242 <vListInsert>
|
||
|
|
8005102: e016 b.n 8005132 <prvSwitchTimerLists+0x9a>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
|
||
|
|
8005104: 2300 movs r3, #0
|
||
|
|
8005106: 9300 str r3, [sp, #0]
|
||
|
|
8005108: 2300 movs r3, #0
|
||
|
|
800510a: 693a ldr r2, [r7, #16]
|
||
|
|
800510c: 2100 movs r1, #0
|
||
|
|
800510e: 68f8 ldr r0, [r7, #12]
|
||
|
|
8005110: f7ff fd60 bl 8004bd4 <xTimerGenericCommand>
|
||
|
|
8005114: 6078 str r0, [r7, #4]
|
||
|
|
configASSERT( xResult );
|
||
|
|
8005116: 687b ldr r3, [r7, #4]
|
||
|
|
8005118: 2b00 cmp r3, #0
|
||
|
|
800511a: d10a bne.n 8005132 <prvSwitchTimerLists+0x9a>
|
||
|
|
__asm volatile
|
||
|
|
800511c: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005120: f383 8811 msr BASEPRI, r3
|
||
|
|
8005124: f3bf 8f6f isb sy
|
||
|
|
8005128: f3bf 8f4f dsb sy
|
||
|
|
800512c: 603b str r3, [r7, #0]
|
||
|
|
}
|
||
|
|
800512e: bf00 nop
|
||
|
|
8005130: e7fe b.n 8005130 <prvSwitchTimerLists+0x98>
|
||
|
|
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
|
||
|
|
8005132: 4b09 ldr r3, [pc, #36] ; (8005158 <prvSwitchTimerLists+0xc0>)
|
||
|
|
8005134: 681b ldr r3, [r3, #0]
|
||
|
|
8005136: 681b ldr r3, [r3, #0]
|
||
|
|
8005138: 2b00 cmp r3, #0
|
||
|
|
800513a: d1b1 bne.n 80050a0 <prvSwitchTimerLists+0x8>
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
pxTemp = pxCurrentTimerList;
|
||
|
|
800513c: 4b06 ldr r3, [pc, #24] ; (8005158 <prvSwitchTimerLists+0xc0>)
|
||
|
|
800513e: 681b ldr r3, [r3, #0]
|
||
|
|
8005140: 617b str r3, [r7, #20]
|
||
|
|
pxCurrentTimerList = pxOverflowTimerList;
|
||
|
|
8005142: 4b06 ldr r3, [pc, #24] ; (800515c <prvSwitchTimerLists+0xc4>)
|
||
|
|
8005144: 681b ldr r3, [r3, #0]
|
||
|
|
8005146: 4a04 ldr r2, [pc, #16] ; (8005158 <prvSwitchTimerLists+0xc0>)
|
||
|
|
8005148: 6013 str r3, [r2, #0]
|
||
|
|
pxOverflowTimerList = pxTemp;
|
||
|
|
800514a: 4a04 ldr r2, [pc, #16] ; (800515c <prvSwitchTimerLists+0xc4>)
|
||
|
|
800514c: 697b ldr r3, [r7, #20]
|
||
|
|
800514e: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
8005150: bf00 nop
|
||
|
|
8005152: 3718 adds r7, #24
|
||
|
|
8005154: 46bd mov sp, r7
|
||
|
|
8005156: bd80 pop {r7, pc}
|
||
|
|
8005158: 20003cf0 .word 0x20003cf0
|
||
|
|
800515c: 20003cf4 .word 0x20003cf4
|
||
|
|
|
||
|
|
08005160 <prvCheckForValidListAndQueue>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvCheckForValidListAndQueue( void )
|
||
|
|
{
|
||
|
|
8005160: b580 push {r7, lr}
|
||
|
|
8005162: b082 sub sp, #8
|
||
|
|
8005164: af02 add r7, sp, #8
|
||
|
|
/* Check that the list from which active timers are referenced, and the
|
||
|
|
queue used to communicate with the timer service, have been
|
||
|
|
initialised. */
|
||
|
|
taskENTER_CRITICAL();
|
||
|
|
8005166: f000 f965 bl 8005434 <vPortEnterCritical>
|
||
|
|
{
|
||
|
|
if( xTimerQueue == NULL )
|
||
|
|
800516a: 4b15 ldr r3, [pc, #84] ; (80051c0 <prvCheckForValidListAndQueue+0x60>)
|
||
|
|
800516c: 681b ldr r3, [r3, #0]
|
||
|
|
800516e: 2b00 cmp r3, #0
|
||
|
|
8005170: d120 bne.n 80051b4 <prvCheckForValidListAndQueue+0x54>
|
||
|
|
{
|
||
|
|
vListInitialise( &xActiveTimerList1 );
|
||
|
|
8005172: 4814 ldr r0, [pc, #80] ; (80051c4 <prvCheckForValidListAndQueue+0x64>)
|
||
|
|
8005174: f7fe f814 bl 80031a0 <vListInitialise>
|
||
|
|
vListInitialise( &xActiveTimerList2 );
|
||
|
|
8005178: 4813 ldr r0, [pc, #76] ; (80051c8 <prvCheckForValidListAndQueue+0x68>)
|
||
|
|
800517a: f7fe f811 bl 80031a0 <vListInitialise>
|
||
|
|
pxCurrentTimerList = &xActiveTimerList1;
|
||
|
|
800517e: 4b13 ldr r3, [pc, #76] ; (80051cc <prvCheckForValidListAndQueue+0x6c>)
|
||
|
|
8005180: 4a10 ldr r2, [pc, #64] ; (80051c4 <prvCheckForValidListAndQueue+0x64>)
|
||
|
|
8005182: 601a str r2, [r3, #0]
|
||
|
|
pxOverflowTimerList = &xActiveTimerList2;
|
||
|
|
8005184: 4b12 ldr r3, [pc, #72] ; (80051d0 <prvCheckForValidListAndQueue+0x70>)
|
||
|
|
8005186: 4a10 ldr r2, [pc, #64] ; (80051c8 <prvCheckForValidListAndQueue+0x68>)
|
||
|
|
8005188: 601a str r2, [r3, #0]
|
||
|
|
/* The timer queue is allocated statically in case
|
||
|
|
configSUPPORT_DYNAMIC_ALLOCATION is 0. */
|
||
|
|
static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
|
||
|
|
static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
|
||
|
|
|
||
|
|
xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
|
||
|
|
800518a: 2300 movs r3, #0
|
||
|
|
800518c: 9300 str r3, [sp, #0]
|
||
|
|
800518e: 4b11 ldr r3, [pc, #68] ; (80051d4 <prvCheckForValidListAndQueue+0x74>)
|
||
|
|
8005190: 4a11 ldr r2, [pc, #68] ; (80051d8 <prvCheckForValidListAndQueue+0x78>)
|
||
|
|
8005192: 2110 movs r1, #16
|
||
|
|
8005194: 200a movs r0, #10
|
||
|
|
8005196: f7fe f91f bl 80033d8 <xQueueGenericCreateStatic>
|
||
|
|
800519a: 4603 mov r3, r0
|
||
|
|
800519c: 4a08 ldr r2, [pc, #32] ; (80051c0 <prvCheckForValidListAndQueue+0x60>)
|
||
|
|
800519e: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if ( configQUEUE_REGISTRY_SIZE > 0 )
|
||
|
|
{
|
||
|
|
if( xTimerQueue != NULL )
|
||
|
|
80051a0: 4b07 ldr r3, [pc, #28] ; (80051c0 <prvCheckForValidListAndQueue+0x60>)
|
||
|
|
80051a2: 681b ldr r3, [r3, #0]
|
||
|
|
80051a4: 2b00 cmp r3, #0
|
||
|
|
80051a6: d005 beq.n 80051b4 <prvCheckForValidListAndQueue+0x54>
|
||
|
|
{
|
||
|
|
vQueueAddToRegistry( xTimerQueue, "TmrQ" );
|
||
|
|
80051a8: 4b05 ldr r3, [pc, #20] ; (80051c0 <prvCheckForValidListAndQueue+0x60>)
|
||
|
|
80051aa: 681b ldr r3, [r3, #0]
|
||
|
|
80051ac: 490b ldr r1, [pc, #44] ; (80051dc <prvCheckForValidListAndQueue+0x7c>)
|
||
|
|
80051ae: 4618 mov r0, r3
|
||
|
|
80051b0: f7fe fd38 bl 8003c24 <vQueueAddToRegistry>
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
taskEXIT_CRITICAL();
|
||
|
|
80051b4: f000 f96e bl 8005494 <vPortExitCritical>
|
||
|
|
}
|
||
|
|
80051b8: bf00 nop
|
||
|
|
80051ba: 46bd mov sp, r7
|
||
|
|
80051bc: bd80 pop {r7, pc}
|
||
|
|
80051be: bf00 nop
|
||
|
|
80051c0: 20003cf8 .word 0x20003cf8
|
||
|
|
80051c4: 20003cc8 .word 0x20003cc8
|
||
|
|
80051c8: 20003cdc .word 0x20003cdc
|
||
|
|
80051cc: 20003cf0 .word 0x20003cf0
|
||
|
|
80051d0: 20003cf4 .word 0x20003cf4
|
||
|
|
80051d4: 20003da4 .word 0x20003da4
|
||
|
|
80051d8: 20003d04 .word 0x20003d04
|
||
|
|
80051dc: 08005cfc .word 0x08005cfc
|
||
|
|
|
||
|
|
080051e0 <pxPortInitialiseStack>:
|
||
|
|
|
||
|
|
/*
|
||
|
|
* See header file for description.
|
||
|
|
*/
|
||
|
|
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||
|
|
{
|
||
|
|
80051e0: b480 push {r7}
|
||
|
|
80051e2: b085 sub sp, #20
|
||
|
|
80051e4: af00 add r7, sp, #0
|
||
|
|
80051e6: 60f8 str r0, [r7, #12]
|
||
|
|
80051e8: 60b9 str r1, [r7, #8]
|
||
|
|
80051ea: 607a str r2, [r7, #4]
|
||
|
|
/* Simulate the stack frame as it would be created by a context switch
|
||
|
|
interrupt. */
|
||
|
|
|
||
|
|
/* Offset added to account for the way the MCU uses the stack on entry/exit
|
||
|
|
of interrupts, and to ensure alignment. */
|
||
|
|
pxTopOfStack--;
|
||
|
|
80051ec: 68fb ldr r3, [r7, #12]
|
||
|
|
80051ee: 3b04 subs r3, #4
|
||
|
|
80051f0: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
|
||
|
|
80051f2: 68fb ldr r3, [r7, #12]
|
||
|
|
80051f4: f04f 7280 mov.w r2, #16777216 ; 0x1000000
|
||
|
|
80051f8: 601a str r2, [r3, #0]
|
||
|
|
pxTopOfStack--;
|
||
|
|
80051fa: 68fb ldr r3, [r7, #12]
|
||
|
|
80051fc: 3b04 subs r3, #4
|
||
|
|
80051fe: 60fb str r3, [r7, #12]
|
||
|
|
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
|
||
|
|
8005200: 68bb ldr r3, [r7, #8]
|
||
|
|
8005202: f023 0201 bic.w r2, r3, #1
|
||
|
|
8005206: 68fb ldr r3, [r7, #12]
|
||
|
|
8005208: 601a str r2, [r3, #0]
|
||
|
|
pxTopOfStack--;
|
||
|
|
800520a: 68fb ldr r3, [r7, #12]
|
||
|
|
800520c: 3b04 subs r3, #4
|
||
|
|
800520e: 60fb str r3, [r7, #12]
|
||
|
|
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
|
||
|
|
8005210: 4a0c ldr r2, [pc, #48] ; (8005244 <pxPortInitialiseStack+0x64>)
|
||
|
|
8005212: 68fb ldr r3, [r7, #12]
|
||
|
|
8005214: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Save code space by skipping register initialisation. */
|
||
|
|
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
|
||
|
|
8005216: 68fb ldr r3, [r7, #12]
|
||
|
|
8005218: 3b14 subs r3, #20
|
||
|
|
800521a: 60fb str r3, [r7, #12]
|
||
|
|
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
|
||
|
|
800521c: 687a ldr r2, [r7, #4]
|
||
|
|
800521e: 68fb ldr r3, [r7, #12]
|
||
|
|
8005220: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* A save method is being used that requires each task to maintain its
|
||
|
|
own exec return value. */
|
||
|
|
pxTopOfStack--;
|
||
|
|
8005222: 68fb ldr r3, [r7, #12]
|
||
|
|
8005224: 3b04 subs r3, #4
|
||
|
|
8005226: 60fb str r3, [r7, #12]
|
||
|
|
*pxTopOfStack = portINITIAL_EXC_RETURN;
|
||
|
|
8005228: 68fb ldr r3, [r7, #12]
|
||
|
|
800522a: f06f 0202 mvn.w r2, #2
|
||
|
|
800522e: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
|
||
|
|
8005230: 68fb ldr r3, [r7, #12]
|
||
|
|
8005232: 3b20 subs r3, #32
|
||
|
|
8005234: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
return pxTopOfStack;
|
||
|
|
8005236: 68fb ldr r3, [r7, #12]
|
||
|
|
}
|
||
|
|
8005238: 4618 mov r0, r3
|
||
|
|
800523a: 3714 adds r7, #20
|
||
|
|
800523c: 46bd mov sp, r7
|
||
|
|
800523e: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8005242: 4770 bx lr
|
||
|
|
8005244: 08005249 .word 0x08005249
|
||
|
|
|
||
|
|
08005248 <prvTaskExitError>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvTaskExitError( void )
|
||
|
|
{
|
||
|
|
8005248: b480 push {r7}
|
||
|
|
800524a: b085 sub sp, #20
|
||
|
|
800524c: af00 add r7, sp, #0
|
||
|
|
volatile uint32_t ulDummy = 0;
|
||
|
|
800524e: 2300 movs r3, #0
|
||
|
|
8005250: 607b str r3, [r7, #4]
|
||
|
|
its caller as there is nothing to return to. If a task wants to exit it
|
||
|
|
should instead call vTaskDelete( NULL ).
|
||
|
|
|
||
|
|
Artificially force an assert() to be triggered if configASSERT() is
|
||
|
|
defined, then stop here so application writers can catch the error. */
|
||
|
|
configASSERT( uxCriticalNesting == ~0UL );
|
||
|
|
8005252: 4b12 ldr r3, [pc, #72] ; (800529c <prvTaskExitError+0x54>)
|
||
|
|
8005254: 681b ldr r3, [r3, #0]
|
||
|
|
8005256: f1b3 3fff cmp.w r3, #4294967295
|
||
|
|
800525a: d00a beq.n 8005272 <prvTaskExitError+0x2a>
|
||
|
|
__asm volatile
|
||
|
|
800525c: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005260: f383 8811 msr BASEPRI, r3
|
||
|
|
8005264: f3bf 8f6f isb sy
|
||
|
|
8005268: f3bf 8f4f dsb sy
|
||
|
|
800526c: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
800526e: bf00 nop
|
||
|
|
8005270: e7fe b.n 8005270 <prvTaskExitError+0x28>
|
||
|
|
__asm volatile
|
||
|
|
8005272: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005276: f383 8811 msr BASEPRI, r3
|
||
|
|
800527a: f3bf 8f6f isb sy
|
||
|
|
800527e: f3bf 8f4f dsb sy
|
||
|
|
8005282: 60bb str r3, [r7, #8]
|
||
|
|
}
|
||
|
|
8005284: bf00 nop
|
||
|
|
portDISABLE_INTERRUPTS();
|
||
|
|
while( ulDummy == 0 )
|
||
|
|
8005286: bf00 nop
|
||
|
|
8005288: 687b ldr r3, [r7, #4]
|
||
|
|
800528a: 2b00 cmp r3, #0
|
||
|
|
800528c: d0fc beq.n 8005288 <prvTaskExitError+0x40>
|
||
|
|
about code appearing after this function is called - making ulDummy
|
||
|
|
volatile makes the compiler think the function could return and
|
||
|
|
therefore not output an 'unreachable code' warning for code that appears
|
||
|
|
after it. */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
800528e: bf00 nop
|
||
|
|
8005290: bf00 nop
|
||
|
|
8005292: 3714 adds r7, #20
|
||
|
|
8005294: 46bd mov sp, r7
|
||
|
|
8005296: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
800529a: 4770 bx lr
|
||
|
|
800529c: 2000001c .word 0x2000001c
|
||
|
|
|
||
|
|
080052a0 <SVC_Handler>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vPortSVCHandler( void )
|
||
|
|
{
|
||
|
|
__asm volatile (
|
||
|
|
80052a0: 4b07 ldr r3, [pc, #28] ; (80052c0 <pxCurrentTCBConst2>)
|
||
|
|
80052a2: 6819 ldr r1, [r3, #0]
|
||
|
|
80052a4: 6808 ldr r0, [r1, #0]
|
||
|
|
80052a6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
||
|
|
80052aa: f380 8809 msr PSP, r0
|
||
|
|
80052ae: f3bf 8f6f isb sy
|
||
|
|
80052b2: f04f 0000 mov.w r0, #0
|
||
|
|
80052b6: f380 8811 msr BASEPRI, r0
|
||
|
|
80052ba: 4770 bx lr
|
||
|
|
80052bc: f3af 8000 nop.w
|
||
|
|
|
||
|
|
080052c0 <pxCurrentTCBConst2>:
|
||
|
|
80052c0: 200037c8 .word 0x200037c8
|
||
|
|
" bx r14 \n"
|
||
|
|
" \n"
|
||
|
|
" .align 4 \n"
|
||
|
|
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
|
||
|
|
);
|
||
|
|
}
|
||
|
|
80052c4: bf00 nop
|
||
|
|
80052c6: bf00 nop
|
||
|
|
|
||
|
|
080052c8 <prvPortStartFirstTask>:
|
||
|
|
{
|
||
|
|
/* Start the first task. This also clears the bit that indicates the FPU is
|
||
|
|
in use in case the FPU was used before the scheduler was started - which
|
||
|
|
would otherwise result in the unnecessary leaving of space in the SVC stack
|
||
|
|
for lazy saving of FPU registers. */
|
||
|
|
__asm volatile(
|
||
|
|
80052c8: 4808 ldr r0, [pc, #32] ; (80052ec <prvPortStartFirstTask+0x24>)
|
||
|
|
80052ca: 6800 ldr r0, [r0, #0]
|
||
|
|
80052cc: 6800 ldr r0, [r0, #0]
|
||
|
|
80052ce: f380 8808 msr MSP, r0
|
||
|
|
80052d2: f04f 0000 mov.w r0, #0
|
||
|
|
80052d6: f380 8814 msr CONTROL, r0
|
||
|
|
80052da: b662 cpsie i
|
||
|
|
80052dc: b661 cpsie f
|
||
|
|
80052de: f3bf 8f4f dsb sy
|
||
|
|
80052e2: f3bf 8f6f isb sy
|
||
|
|
80052e6: df00 svc 0
|
||
|
|
80052e8: bf00 nop
|
||
|
|
" dsb \n"
|
||
|
|
" isb \n"
|
||
|
|
" svc 0 \n" /* System call to start first task. */
|
||
|
|
" nop \n"
|
||
|
|
);
|
||
|
|
}
|
||
|
|
80052ea: bf00 nop
|
||
|
|
80052ec: e000ed08 .word 0xe000ed08
|
||
|
|
|
||
|
|
080052f0 <xPortStartScheduler>:
|
||
|
|
|
||
|
|
/*
|
||
|
|
* See header file for description.
|
||
|
|
*/
|
||
|
|
BaseType_t xPortStartScheduler( void )
|
||
|
|
{
|
||
|
|
80052f0: b580 push {r7, lr}
|
||
|
|
80052f2: b086 sub sp, #24
|
||
|
|
80052f4: af00 add r7, sp, #0
|
||
|
|
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
|
||
|
|
|
||
|
|
/* This port can be used on all revisions of the Cortex-M7 core other than
|
||
|
|
the r0p1 parts. r0p1 parts should use the port from the
|
||
|
|
/source/portable/GCC/ARM_CM7/r0p1 directory. */
|
||
|
|
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
|
||
|
|
80052f6: 4b46 ldr r3, [pc, #280] ; (8005410 <xPortStartScheduler+0x120>)
|
||
|
|
80052f8: 681b ldr r3, [r3, #0]
|
||
|
|
80052fa: 4a46 ldr r2, [pc, #280] ; (8005414 <xPortStartScheduler+0x124>)
|
||
|
|
80052fc: 4293 cmp r3, r2
|
||
|
|
80052fe: d10a bne.n 8005316 <xPortStartScheduler+0x26>
|
||
|
|
__asm volatile
|
||
|
|
8005300: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005304: f383 8811 msr BASEPRI, r3
|
||
|
|
8005308: f3bf 8f6f isb sy
|
||
|
|
800530c: f3bf 8f4f dsb sy
|
||
|
|
8005310: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
8005312: bf00 nop
|
||
|
|
8005314: e7fe b.n 8005314 <xPortStartScheduler+0x24>
|
||
|
|
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
|
||
|
|
8005316: 4b3e ldr r3, [pc, #248] ; (8005410 <xPortStartScheduler+0x120>)
|
||
|
|
8005318: 681b ldr r3, [r3, #0]
|
||
|
|
800531a: 4a3f ldr r2, [pc, #252] ; (8005418 <xPortStartScheduler+0x128>)
|
||
|
|
800531c: 4293 cmp r3, r2
|
||
|
|
800531e: d10a bne.n 8005336 <xPortStartScheduler+0x46>
|
||
|
|
__asm volatile
|
||
|
|
8005320: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005324: f383 8811 msr BASEPRI, r3
|
||
|
|
8005328: f3bf 8f6f isb sy
|
||
|
|
800532c: f3bf 8f4f dsb sy
|
||
|
|
8005330: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
8005332: bf00 nop
|
||
|
|
8005334: e7fe b.n 8005334 <xPortStartScheduler+0x44>
|
||
|
|
|
||
|
|
#if( configASSERT_DEFINED == 1 )
|
||
|
|
{
|
||
|
|
volatile uint32_t ulOriginalPriority;
|
||
|
|
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
|
||
|
|
8005336: 4b39 ldr r3, [pc, #228] ; (800541c <xPortStartScheduler+0x12c>)
|
||
|
|
8005338: 617b str r3, [r7, #20]
|
||
|
|
functions can be called. ISR safe functions are those that end in
|
||
|
|
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
|
||
|
|
ensure interrupt entry is as fast and simple as possible.
|
||
|
|
|
||
|
|
Save the interrupt priority value that is about to be clobbered. */
|
||
|
|
ulOriginalPriority = *pucFirstUserPriorityRegister;
|
||
|
|
800533a: 697b ldr r3, [r7, #20]
|
||
|
|
800533c: 781b ldrb r3, [r3, #0]
|
||
|
|
800533e: b2db uxtb r3, r3
|
||
|
|
8005340: 607b str r3, [r7, #4]
|
||
|
|
|
||
|
|
/* Determine the number of priority bits available. First write to all
|
||
|
|
possible bits. */
|
||
|
|
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
|
||
|
|
8005342: 697b ldr r3, [r7, #20]
|
||
|
|
8005344: 22ff movs r2, #255 ; 0xff
|
||
|
|
8005346: 701a strb r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Read the value back to see how many bits stuck. */
|
||
|
|
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
|
||
|
|
8005348: 697b ldr r3, [r7, #20]
|
||
|
|
800534a: 781b ldrb r3, [r3, #0]
|
||
|
|
800534c: b2db uxtb r3, r3
|
||
|
|
800534e: 70fb strb r3, [r7, #3]
|
||
|
|
|
||
|
|
/* Use the same mask on the maximum system call priority. */
|
||
|
|
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
||
|
|
8005350: 78fb ldrb r3, [r7, #3]
|
||
|
|
8005352: b2db uxtb r3, r3
|
||
|
|
8005354: f003 0350 and.w r3, r3, #80 ; 0x50
|
||
|
|
8005358: b2da uxtb r2, r3
|
||
|
|
800535a: 4b31 ldr r3, [pc, #196] ; (8005420 <xPortStartScheduler+0x130>)
|
||
|
|
800535c: 701a strb r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Calculate the maximum acceptable priority group value for the number
|
||
|
|
of bits read back. */
|
||
|
|
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
||
|
|
800535e: 4b31 ldr r3, [pc, #196] ; (8005424 <xPortStartScheduler+0x134>)
|
||
|
|
8005360: 2207 movs r2, #7
|
||
|
|
8005362: 601a str r2, [r3, #0]
|
||
|
|
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
||
|
|
8005364: e009 b.n 800537a <xPortStartScheduler+0x8a>
|
||
|
|
{
|
||
|
|
ulMaxPRIGROUPValue--;
|
||
|
|
8005366: 4b2f ldr r3, [pc, #188] ; (8005424 <xPortStartScheduler+0x134>)
|
||
|
|
8005368: 681b ldr r3, [r3, #0]
|
||
|
|
800536a: 3b01 subs r3, #1
|
||
|
|
800536c: 4a2d ldr r2, [pc, #180] ; (8005424 <xPortStartScheduler+0x134>)
|
||
|
|
800536e: 6013 str r3, [r2, #0]
|
||
|
|
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
|
||
|
|
8005370: 78fb ldrb r3, [r7, #3]
|
||
|
|
8005372: b2db uxtb r3, r3
|
||
|
|
8005374: 005b lsls r3, r3, #1
|
||
|
|
8005376: b2db uxtb r3, r3
|
||
|
|
8005378: 70fb strb r3, [r7, #3]
|
||
|
|
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
||
|
|
800537a: 78fb ldrb r3, [r7, #3]
|
||
|
|
800537c: b2db uxtb r3, r3
|
||
|
|
800537e: f003 0380 and.w r3, r3, #128 ; 0x80
|
||
|
|
8005382: 2b80 cmp r3, #128 ; 0x80
|
||
|
|
8005384: d0ef beq.n 8005366 <xPortStartScheduler+0x76>
|
||
|
|
#ifdef configPRIO_BITS
|
||
|
|
{
|
||
|
|
/* Check the FreeRTOS configuration that defines the number of
|
||
|
|
priority bits matches the number of priority bits actually queried
|
||
|
|
from the hardware. */
|
||
|
|
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
|
||
|
|
8005386: 4b27 ldr r3, [pc, #156] ; (8005424 <xPortStartScheduler+0x134>)
|
||
|
|
8005388: 681b ldr r3, [r3, #0]
|
||
|
|
800538a: f1c3 0307 rsb r3, r3, #7
|
||
|
|
800538e: 2b04 cmp r3, #4
|
||
|
|
8005390: d00a beq.n 80053a8 <xPortStartScheduler+0xb8>
|
||
|
|
__asm volatile
|
||
|
|
8005392: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005396: f383 8811 msr BASEPRI, r3
|
||
|
|
800539a: f3bf 8f6f isb sy
|
||
|
|
800539e: f3bf 8f4f dsb sy
|
||
|
|
80053a2: 60bb str r3, [r7, #8]
|
||
|
|
}
|
||
|
|
80053a4: bf00 nop
|
||
|
|
80053a6: e7fe b.n 80053a6 <xPortStartScheduler+0xb6>
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Shift the priority group value back to its position within the AIRCR
|
||
|
|
register. */
|
||
|
|
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
|
||
|
|
80053a8: 4b1e ldr r3, [pc, #120] ; (8005424 <xPortStartScheduler+0x134>)
|
||
|
|
80053aa: 681b ldr r3, [r3, #0]
|
||
|
|
80053ac: 021b lsls r3, r3, #8
|
||
|
|
80053ae: 4a1d ldr r2, [pc, #116] ; (8005424 <xPortStartScheduler+0x134>)
|
||
|
|
80053b0: 6013 str r3, [r2, #0]
|
||
|
|
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
|
||
|
|
80053b2: 4b1c ldr r3, [pc, #112] ; (8005424 <xPortStartScheduler+0x134>)
|
||
|
|
80053b4: 681b ldr r3, [r3, #0]
|
||
|
|
80053b6: f403 63e0 and.w r3, r3, #1792 ; 0x700
|
||
|
|
80053ba: 4a1a ldr r2, [pc, #104] ; (8005424 <xPortStartScheduler+0x134>)
|
||
|
|
80053bc: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Restore the clobbered interrupt priority register to its original
|
||
|
|
value. */
|
||
|
|
*pucFirstUserPriorityRegister = ulOriginalPriority;
|
||
|
|
80053be: 687b ldr r3, [r7, #4]
|
||
|
|
80053c0: b2da uxtb r2, r3
|
||
|
|
80053c2: 697b ldr r3, [r7, #20]
|
||
|
|
80053c4: 701a strb r2, [r3, #0]
|
||
|
|
}
|
||
|
|
#endif /* conifgASSERT_DEFINED */
|
||
|
|
|
||
|
|
/* Make PendSV and SysTick the lowest priority interrupts. */
|
||
|
|
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
|
||
|
|
80053c6: 4b18 ldr r3, [pc, #96] ; (8005428 <xPortStartScheduler+0x138>)
|
||
|
|
80053c8: 681b ldr r3, [r3, #0]
|
||
|
|
80053ca: 4a17 ldr r2, [pc, #92] ; (8005428 <xPortStartScheduler+0x138>)
|
||
|
|
80053cc: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
|
||
|
|
80053d0: 6013 str r3, [r2, #0]
|
||
|
|
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
|
||
|
|
80053d2: 4b15 ldr r3, [pc, #84] ; (8005428 <xPortStartScheduler+0x138>)
|
||
|
|
80053d4: 681b ldr r3, [r3, #0]
|
||
|
|
80053d6: 4a14 ldr r2, [pc, #80] ; (8005428 <xPortStartScheduler+0x138>)
|
||
|
|
80053d8: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000
|
||
|
|
80053dc: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Start the timer that generates the tick ISR. Interrupts are disabled
|
||
|
|
here already. */
|
||
|
|
vPortSetupTimerInterrupt();
|
||
|
|
80053de: f000 f8dd bl 800559c <vPortSetupTimerInterrupt>
|
||
|
|
|
||
|
|
/* Initialise the critical nesting count ready for the first task. */
|
||
|
|
uxCriticalNesting = 0;
|
||
|
|
80053e2: 4b12 ldr r3, [pc, #72] ; (800542c <xPortStartScheduler+0x13c>)
|
||
|
|
80053e4: 2200 movs r2, #0
|
||
|
|
80053e6: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Ensure the VFP is enabled - it should be anyway. */
|
||
|
|
vPortEnableVFP();
|
||
|
|
80053e8: f000 f8fc bl 80055e4 <vPortEnableVFP>
|
||
|
|
|
||
|
|
/* Lazy save always. */
|
||
|
|
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
|
||
|
|
80053ec: 4b10 ldr r3, [pc, #64] ; (8005430 <xPortStartScheduler+0x140>)
|
||
|
|
80053ee: 681b ldr r3, [r3, #0]
|
||
|
|
80053f0: 4a0f ldr r2, [pc, #60] ; (8005430 <xPortStartScheduler+0x140>)
|
||
|
|
80053f2: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000
|
||
|
|
80053f6: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Start the first task. */
|
||
|
|
prvPortStartFirstTask();
|
||
|
|
80053f8: f7ff ff66 bl 80052c8 <prvPortStartFirstTask>
|
||
|
|
exit error function to prevent compiler warnings about a static function
|
||
|
|
not being called in the case that the application writer overrides this
|
||
|
|
functionality by defining configTASK_RETURN_ADDRESS. Call
|
||
|
|
vTaskSwitchContext() so link time optimisation does not remove the
|
||
|
|
symbol. */
|
||
|
|
vTaskSwitchContext();
|
||
|
|
80053fc: f7ff f84a bl 8004494 <vTaskSwitchContext>
|
||
|
|
prvTaskExitError();
|
||
|
|
8005400: f7ff ff22 bl 8005248 <prvTaskExitError>
|
||
|
|
|
||
|
|
/* Should not get here! */
|
||
|
|
return 0;
|
||
|
|
8005404: 2300 movs r3, #0
|
||
|
|
}
|
||
|
|
8005406: 4618 mov r0, r3
|
||
|
|
8005408: 3718 adds r7, #24
|
||
|
|
800540a: 46bd mov sp, r7
|
||
|
|
800540c: bd80 pop {r7, pc}
|
||
|
|
800540e: bf00 nop
|
||
|
|
8005410: e000ed00 .word 0xe000ed00
|
||
|
|
8005414: 410fc271 .word 0x410fc271
|
||
|
|
8005418: 410fc270 .word 0x410fc270
|
||
|
|
800541c: e000e400 .word 0xe000e400
|
||
|
|
8005420: 20003df4 .word 0x20003df4
|
||
|
|
8005424: 20003df8 .word 0x20003df8
|
||
|
|
8005428: e000ed20 .word 0xe000ed20
|
||
|
|
800542c: 2000001c .word 0x2000001c
|
||
|
|
8005430: e000ef34 .word 0xe000ef34
|
||
|
|
|
||
|
|
08005434 <vPortEnterCritical>:
|
||
|
|
configASSERT( uxCriticalNesting == 1000UL );
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vPortEnterCritical( void )
|
||
|
|
{
|
||
|
|
8005434: b480 push {r7}
|
||
|
|
8005436: b083 sub sp, #12
|
||
|
|
8005438: af00 add r7, sp, #0
|
||
|
|
__asm volatile
|
||
|
|
800543a: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
800543e: f383 8811 msr BASEPRI, r3
|
||
|
|
8005442: f3bf 8f6f isb sy
|
||
|
|
8005446: f3bf 8f4f dsb sy
|
||
|
|
800544a: 607b str r3, [r7, #4]
|
||
|
|
}
|
||
|
|
800544c: bf00 nop
|
||
|
|
portDISABLE_INTERRUPTS();
|
||
|
|
uxCriticalNesting++;
|
||
|
|
800544e: 4b0f ldr r3, [pc, #60] ; (800548c <vPortEnterCritical+0x58>)
|
||
|
|
8005450: 681b ldr r3, [r3, #0]
|
||
|
|
8005452: 3301 adds r3, #1
|
||
|
|
8005454: 4a0d ldr r2, [pc, #52] ; (800548c <vPortEnterCritical+0x58>)
|
||
|
|
8005456: 6013 str r3, [r2, #0]
|
||
|
|
/* This is not the interrupt safe version of the enter critical function so
|
||
|
|
assert() if it is being called from an interrupt context. Only API
|
||
|
|
functions that end in "FromISR" can be used in an interrupt. Only assert if
|
||
|
|
the critical nesting count is 1 to protect against recursive calls if the
|
||
|
|
assert function also uses a critical section. */
|
||
|
|
if( uxCriticalNesting == 1 )
|
||
|
|
8005458: 4b0c ldr r3, [pc, #48] ; (800548c <vPortEnterCritical+0x58>)
|
||
|
|
800545a: 681b ldr r3, [r3, #0]
|
||
|
|
800545c: 2b01 cmp r3, #1
|
||
|
|
800545e: d10f bne.n 8005480 <vPortEnterCritical+0x4c>
|
||
|
|
{
|
||
|
|
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
|
||
|
|
8005460: 4b0b ldr r3, [pc, #44] ; (8005490 <vPortEnterCritical+0x5c>)
|
||
|
|
8005462: 681b ldr r3, [r3, #0]
|
||
|
|
8005464: b2db uxtb r3, r3
|
||
|
|
8005466: 2b00 cmp r3, #0
|
||
|
|
8005468: d00a beq.n 8005480 <vPortEnterCritical+0x4c>
|
||
|
|
__asm volatile
|
||
|
|
800546a: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
800546e: f383 8811 msr BASEPRI, r3
|
||
|
|
8005472: f3bf 8f6f isb sy
|
||
|
|
8005476: f3bf 8f4f dsb sy
|
||
|
|
800547a: 603b str r3, [r7, #0]
|
||
|
|
}
|
||
|
|
800547c: bf00 nop
|
||
|
|
800547e: e7fe b.n 800547e <vPortEnterCritical+0x4a>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8005480: bf00 nop
|
||
|
|
8005482: 370c adds r7, #12
|
||
|
|
8005484: 46bd mov sp, r7
|
||
|
|
8005486: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
800548a: 4770 bx lr
|
||
|
|
800548c: 2000001c .word 0x2000001c
|
||
|
|
8005490: e000ed04 .word 0xe000ed04
|
||
|
|
|
||
|
|
08005494 <vPortExitCritical>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vPortExitCritical( void )
|
||
|
|
{
|
||
|
|
8005494: b480 push {r7}
|
||
|
|
8005496: b083 sub sp, #12
|
||
|
|
8005498: af00 add r7, sp, #0
|
||
|
|
configASSERT( uxCriticalNesting );
|
||
|
|
800549a: 4b12 ldr r3, [pc, #72] ; (80054e4 <vPortExitCritical+0x50>)
|
||
|
|
800549c: 681b ldr r3, [r3, #0]
|
||
|
|
800549e: 2b00 cmp r3, #0
|
||
|
|
80054a0: d10a bne.n 80054b8 <vPortExitCritical+0x24>
|
||
|
|
__asm volatile
|
||
|
|
80054a2: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80054a6: f383 8811 msr BASEPRI, r3
|
||
|
|
80054aa: f3bf 8f6f isb sy
|
||
|
|
80054ae: f3bf 8f4f dsb sy
|
||
|
|
80054b2: 607b str r3, [r7, #4]
|
||
|
|
}
|
||
|
|
80054b4: bf00 nop
|
||
|
|
80054b6: e7fe b.n 80054b6 <vPortExitCritical+0x22>
|
||
|
|
uxCriticalNesting--;
|
||
|
|
80054b8: 4b0a ldr r3, [pc, #40] ; (80054e4 <vPortExitCritical+0x50>)
|
||
|
|
80054ba: 681b ldr r3, [r3, #0]
|
||
|
|
80054bc: 3b01 subs r3, #1
|
||
|
|
80054be: 4a09 ldr r2, [pc, #36] ; (80054e4 <vPortExitCritical+0x50>)
|
||
|
|
80054c0: 6013 str r3, [r2, #0]
|
||
|
|
if( uxCriticalNesting == 0 )
|
||
|
|
80054c2: 4b08 ldr r3, [pc, #32] ; (80054e4 <vPortExitCritical+0x50>)
|
||
|
|
80054c4: 681b ldr r3, [r3, #0]
|
||
|
|
80054c6: 2b00 cmp r3, #0
|
||
|
|
80054c8: d105 bne.n 80054d6 <vPortExitCritical+0x42>
|
||
|
|
80054ca: 2300 movs r3, #0
|
||
|
|
80054cc: 603b str r3, [r7, #0]
|
||
|
|
__asm volatile
|
||
|
|
80054ce: 683b ldr r3, [r7, #0]
|
||
|
|
80054d0: f383 8811 msr BASEPRI, r3
|
||
|
|
}
|
||
|
|
80054d4: bf00 nop
|
||
|
|
{
|
||
|
|
portENABLE_INTERRUPTS();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
80054d6: bf00 nop
|
||
|
|
80054d8: 370c adds r7, #12
|
||
|
|
80054da: 46bd mov sp, r7
|
||
|
|
80054dc: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80054e0: 4770 bx lr
|
||
|
|
80054e2: bf00 nop
|
||
|
|
80054e4: 2000001c .word 0x2000001c
|
||
|
|
...
|
||
|
|
|
||
|
|
080054f0 <PendSV_Handler>:
|
||
|
|
|
||
|
|
void xPortPendSVHandler( void )
|
||
|
|
{
|
||
|
|
/* This is a naked function. */
|
||
|
|
|
||
|
|
__asm volatile
|
||
|
|
80054f0: f3ef 8009 mrs r0, PSP
|
||
|
|
80054f4: f3bf 8f6f isb sy
|
||
|
|
80054f8: 4b15 ldr r3, [pc, #84] ; (8005550 <pxCurrentTCBConst>)
|
||
|
|
80054fa: 681a ldr r2, [r3, #0]
|
||
|
|
80054fc: f01e 0f10 tst.w lr, #16
|
||
|
|
8005500: bf08 it eq
|
||
|
|
8005502: ed20 8a10 vstmdbeq r0!, {s16-s31}
|
||
|
|
8005506: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
||
|
|
800550a: 6010 str r0, [r2, #0]
|
||
|
|
800550c: e92d 0009 stmdb sp!, {r0, r3}
|
||
|
|
8005510: f04f 0050 mov.w r0, #80 ; 0x50
|
||
|
|
8005514: f380 8811 msr BASEPRI, r0
|
||
|
|
8005518: f3bf 8f4f dsb sy
|
||
|
|
800551c: f3bf 8f6f isb sy
|
||
|
|
8005520: f7fe ffb8 bl 8004494 <vTaskSwitchContext>
|
||
|
|
8005524: f04f 0000 mov.w r0, #0
|
||
|
|
8005528: f380 8811 msr BASEPRI, r0
|
||
|
|
800552c: bc09 pop {r0, r3}
|
||
|
|
800552e: 6819 ldr r1, [r3, #0]
|
||
|
|
8005530: 6808 ldr r0, [r1, #0]
|
||
|
|
8005532: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
||
|
|
8005536: f01e 0f10 tst.w lr, #16
|
||
|
|
800553a: bf08 it eq
|
||
|
|
800553c: ecb0 8a10 vldmiaeq r0!, {s16-s31}
|
||
|
|
8005540: f380 8809 msr PSP, r0
|
||
|
|
8005544: f3bf 8f6f isb sy
|
||
|
|
8005548: 4770 bx lr
|
||
|
|
800554a: bf00 nop
|
||
|
|
800554c: f3af 8000 nop.w
|
||
|
|
|
||
|
|
08005550 <pxCurrentTCBConst>:
|
||
|
|
8005550: 200037c8 .word 0x200037c8
|
||
|
|
" \n"
|
||
|
|
" .align 4 \n"
|
||
|
|
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
||
|
|
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
|
||
|
|
);
|
||
|
|
}
|
||
|
|
8005554: bf00 nop
|
||
|
|
8005556: bf00 nop
|
||
|
|
|
||
|
|
08005558 <xPortSysTickHandler>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void xPortSysTickHandler( void )
|
||
|
|
{
|
||
|
|
8005558: b580 push {r7, lr}
|
||
|
|
800555a: b082 sub sp, #8
|
||
|
|
800555c: af00 add r7, sp, #0
|
||
|
|
__asm volatile
|
||
|
|
800555e: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005562: f383 8811 msr BASEPRI, r3
|
||
|
|
8005566: f3bf 8f6f isb sy
|
||
|
|
800556a: f3bf 8f4f dsb sy
|
||
|
|
800556e: 607b str r3, [r7, #4]
|
||
|
|
}
|
||
|
|
8005570: bf00 nop
|
||
|
|
save and then restore the interrupt mask value as its value is already
|
||
|
|
known. */
|
||
|
|
portDISABLE_INTERRUPTS();
|
||
|
|
{
|
||
|
|
/* Increment the RTOS tick. */
|
||
|
|
if( xTaskIncrementTick() != pdFALSE )
|
||
|
|
8005572: f7fe fecd bl 8004310 <xTaskIncrementTick>
|
||
|
|
8005576: 4603 mov r3, r0
|
||
|
|
8005578: 2b00 cmp r3, #0
|
||
|
|
800557a: d003 beq.n 8005584 <xPortSysTickHandler+0x2c>
|
||
|
|
{
|
||
|
|
/* A context switch is required. Context switching is performed in
|
||
|
|
the PendSV interrupt. Pend the PendSV interrupt. */
|
||
|
|
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
||
|
|
800557c: 4b06 ldr r3, [pc, #24] ; (8005598 <xPortSysTickHandler+0x40>)
|
||
|
|
800557e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
||
|
|
8005582: 601a str r2, [r3, #0]
|
||
|
|
8005584: 2300 movs r3, #0
|
||
|
|
8005586: 603b str r3, [r7, #0]
|
||
|
|
__asm volatile
|
||
|
|
8005588: 683b ldr r3, [r7, #0]
|
||
|
|
800558a: f383 8811 msr BASEPRI, r3
|
||
|
|
}
|
||
|
|
800558e: bf00 nop
|
||
|
|
}
|
||
|
|
}
|
||
|
|
portENABLE_INTERRUPTS();
|
||
|
|
}
|
||
|
|
8005590: bf00 nop
|
||
|
|
8005592: 3708 adds r7, #8
|
||
|
|
8005594: 46bd mov sp, r7
|
||
|
|
8005596: bd80 pop {r7, pc}
|
||
|
|
8005598: e000ed04 .word 0xe000ed04
|
||
|
|
|
||
|
|
0800559c <vPortSetupTimerInterrupt>:
|
||
|
|
/*
|
||
|
|
* Setup the systick timer to generate the tick interrupts at the required
|
||
|
|
* frequency.
|
||
|
|
*/
|
||
|
|
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
|
||
|
|
{
|
||
|
|
800559c: b480 push {r7}
|
||
|
|
800559e: af00 add r7, sp, #0
|
||
|
|
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
|
||
|
|
}
|
||
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
||
|
|
|
||
|
|
/* Stop and clear the SysTick. */
|
||
|
|
portNVIC_SYSTICK_CTRL_REG = 0UL;
|
||
|
|
80055a0: 4b0b ldr r3, [pc, #44] ; (80055d0 <vPortSetupTimerInterrupt+0x34>)
|
||
|
|
80055a2: 2200 movs r2, #0
|
||
|
|
80055a4: 601a str r2, [r3, #0]
|
||
|
|
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
||
|
|
80055a6: 4b0b ldr r3, [pc, #44] ; (80055d4 <vPortSetupTimerInterrupt+0x38>)
|
||
|
|
80055a8: 2200 movs r2, #0
|
||
|
|
80055aa: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* Configure SysTick to interrupt at the requested rate. */
|
||
|
|
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
||
|
|
80055ac: 4b0a ldr r3, [pc, #40] ; (80055d8 <vPortSetupTimerInterrupt+0x3c>)
|
||
|
|
80055ae: 681b ldr r3, [r3, #0]
|
||
|
|
80055b0: 4a0a ldr r2, [pc, #40] ; (80055dc <vPortSetupTimerInterrupt+0x40>)
|
||
|
|
80055b2: fba2 2303 umull r2, r3, r2, r3
|
||
|
|
80055b6: 099b lsrs r3, r3, #6
|
||
|
|
80055b8: 4a09 ldr r2, [pc, #36] ; (80055e0 <vPortSetupTimerInterrupt+0x44>)
|
||
|
|
80055ba: 3b01 subs r3, #1
|
||
|
|
80055bc: 6013 str r3, [r2, #0]
|
||
|
|
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
|
||
|
|
80055be: 4b04 ldr r3, [pc, #16] ; (80055d0 <vPortSetupTimerInterrupt+0x34>)
|
||
|
|
80055c0: 2207 movs r2, #7
|
||
|
|
80055c2: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
80055c4: bf00 nop
|
||
|
|
80055c6: 46bd mov sp, r7
|
||
|
|
80055c8: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
80055cc: 4770 bx lr
|
||
|
|
80055ce: bf00 nop
|
||
|
|
80055d0: e000e010 .word 0xe000e010
|
||
|
|
80055d4: e000e018 .word 0xe000e018
|
||
|
|
80055d8: 20000000 .word 0x20000000
|
||
|
|
80055dc: 10624dd3 .word 0x10624dd3
|
||
|
|
80055e0: e000e014 .word 0xe000e014
|
||
|
|
|
||
|
|
080055e4 <vPortEnableVFP>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
/* This is a naked function. */
|
||
|
|
static void vPortEnableVFP( void )
|
||
|
|
{
|
||
|
|
__asm volatile
|
||
|
|
80055e4: f8df 000c ldr.w r0, [pc, #12] ; 80055f4 <vPortEnableVFP+0x10>
|
||
|
|
80055e8: 6801 ldr r1, [r0, #0]
|
||
|
|
80055ea: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
|
||
|
|
80055ee: 6001 str r1, [r0, #0]
|
||
|
|
80055f0: 4770 bx lr
|
||
|
|
" \n"
|
||
|
|
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
|
||
|
|
" str r1, [r0] \n"
|
||
|
|
" bx r14 "
|
||
|
|
);
|
||
|
|
}
|
||
|
|
80055f2: bf00 nop
|
||
|
|
80055f4: e000ed88 .word 0xe000ed88
|
||
|
|
|
||
|
|
080055f8 <vPortValidateInterruptPriority>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
#if( configASSERT_DEFINED == 1 )
|
||
|
|
|
||
|
|
void vPortValidateInterruptPriority( void )
|
||
|
|
{
|
||
|
|
80055f8: b480 push {r7}
|
||
|
|
80055fa: b085 sub sp, #20
|
||
|
|
80055fc: af00 add r7, sp, #0
|
||
|
|
uint32_t ulCurrentInterrupt;
|
||
|
|
uint8_t ucCurrentPriority;
|
||
|
|
|
||
|
|
/* Obtain the number of the currently executing interrupt. */
|
||
|
|
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
|
||
|
|
80055fe: f3ef 8305 mrs r3, IPSR
|
||
|
|
8005602: 60fb str r3, [r7, #12]
|
||
|
|
|
||
|
|
/* Is the interrupt number a user defined interrupt? */
|
||
|
|
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
|
||
|
|
8005604: 68fb ldr r3, [r7, #12]
|
||
|
|
8005606: 2b0f cmp r3, #15
|
||
|
|
8005608: d914 bls.n 8005634 <vPortValidateInterruptPriority+0x3c>
|
||
|
|
{
|
||
|
|
/* Look up the interrupt's priority. */
|
||
|
|
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
|
||
|
|
800560a: 4a17 ldr r2, [pc, #92] ; (8005668 <vPortValidateInterruptPriority+0x70>)
|
||
|
|
800560c: 68fb ldr r3, [r7, #12]
|
||
|
|
800560e: 4413 add r3, r2
|
||
|
|
8005610: 781b ldrb r3, [r3, #0]
|
||
|
|
8005612: 72fb strb r3, [r7, #11]
|
||
|
|
interrupt entry is as fast and simple as possible.
|
||
|
|
|
||
|
|
The following links provide detailed information:
|
||
|
|
http://www.freertos.org/RTOS-Cortex-M3-M4.html
|
||
|
|
http://www.freertos.org/FAQHelp.html */
|
||
|
|
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
|
||
|
|
8005614: 4b15 ldr r3, [pc, #84] ; (800566c <vPortValidateInterruptPriority+0x74>)
|
||
|
|
8005616: 781b ldrb r3, [r3, #0]
|
||
|
|
8005618: 7afa ldrb r2, [r7, #11]
|
||
|
|
800561a: 429a cmp r2, r3
|
||
|
|
800561c: d20a bcs.n 8005634 <vPortValidateInterruptPriority+0x3c>
|
||
|
|
__asm volatile
|
||
|
|
800561e: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005622: f383 8811 msr BASEPRI, r3
|
||
|
|
8005626: f3bf 8f6f isb sy
|
||
|
|
800562a: f3bf 8f4f dsb sy
|
||
|
|
800562e: 607b str r3, [r7, #4]
|
||
|
|
}
|
||
|
|
8005630: bf00 nop
|
||
|
|
8005632: e7fe b.n 8005632 <vPortValidateInterruptPriority+0x3a>
|
||
|
|
configuration then the correct setting can be achieved on all Cortex-M
|
||
|
|
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
||
|
|
scheduler. Note however that some vendor specific peripheral libraries
|
||
|
|
assume a non-zero priority group setting, in which cases using a value
|
||
|
|
of zero will result in unpredictable behaviour. */
|
||
|
|
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
|
||
|
|
8005634: 4b0e ldr r3, [pc, #56] ; (8005670 <vPortValidateInterruptPriority+0x78>)
|
||
|
|
8005636: 681b ldr r3, [r3, #0]
|
||
|
|
8005638: f403 62e0 and.w r2, r3, #1792 ; 0x700
|
||
|
|
800563c: 4b0d ldr r3, [pc, #52] ; (8005674 <vPortValidateInterruptPriority+0x7c>)
|
||
|
|
800563e: 681b ldr r3, [r3, #0]
|
||
|
|
8005640: 429a cmp r2, r3
|
||
|
|
8005642: d90a bls.n 800565a <vPortValidateInterruptPriority+0x62>
|
||
|
|
__asm volatile
|
||
|
|
8005644: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005648: f383 8811 msr BASEPRI, r3
|
||
|
|
800564c: f3bf 8f6f isb sy
|
||
|
|
8005650: f3bf 8f4f dsb sy
|
||
|
|
8005654: 603b str r3, [r7, #0]
|
||
|
|
}
|
||
|
|
8005656: bf00 nop
|
||
|
|
8005658: e7fe b.n 8005658 <vPortValidateInterruptPriority+0x60>
|
||
|
|
}
|
||
|
|
800565a: bf00 nop
|
||
|
|
800565c: 3714 adds r7, #20
|
||
|
|
800565e: 46bd mov sp, r7
|
||
|
|
8005660: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8005664: 4770 bx lr
|
||
|
|
8005666: bf00 nop
|
||
|
|
8005668: e000e3f0 .word 0xe000e3f0
|
||
|
|
800566c: 20003df4 .word 0x20003df4
|
||
|
|
8005670: e000ed0c .word 0xe000ed0c
|
||
|
|
8005674: 20003df8 .word 0x20003df8
|
||
|
|
|
||
|
|
08005678 <pvPortMalloc>:
|
||
|
|
static size_t xBlockAllocatedBit = 0;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void *pvPortMalloc( size_t xWantedSize )
|
||
|
|
{
|
||
|
|
8005678: b580 push {r7, lr}
|
||
|
|
800567a: b088 sub sp, #32
|
||
|
|
800567c: af00 add r7, sp, #0
|
||
|
|
800567e: 6078 str r0, [r7, #4]
|
||
|
|
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
|
||
|
|
void *pvReturn = NULL;
|
||
|
|
8005680: 2300 movs r3, #0
|
||
|
|
8005682: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* The heap must be initialised before the first call to
|
||
|
|
prvPortMalloc(). */
|
||
|
|
configASSERT( pxEnd );
|
||
|
|
8005684: 4b48 ldr r3, [pc, #288] ; (80057a8 <pvPortMalloc+0x130>)
|
||
|
|
8005686: 681b ldr r3, [r3, #0]
|
||
|
|
8005688: 2b00 cmp r3, #0
|
||
|
|
800568a: d10a bne.n 80056a2 <pvPortMalloc+0x2a>
|
||
|
|
__asm volatile
|
||
|
|
800568c: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005690: f383 8811 msr BASEPRI, r3
|
||
|
|
8005694: f3bf 8f6f isb sy
|
||
|
|
8005698: f3bf 8f4f dsb sy
|
||
|
|
800569c: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
800569e: bf00 nop
|
||
|
|
80056a0: e7fe b.n 80056a0 <pvPortMalloc+0x28>
|
||
|
|
|
||
|
|
vTaskSuspendAll();
|
||
|
|
80056a2: f7fe fd79 bl 8004198 <vTaskSuspendAll>
|
||
|
|
{
|
||
|
|
/* Check the requested block size is not so large that the top bit is
|
||
|
|
set. The top bit of the block size member of the BlockLink_t structure
|
||
|
|
is used to determine who owns the block - the application or the
|
||
|
|
kernel, so it must be free. */
|
||
|
|
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
|
||
|
|
80056a6: 4b41 ldr r3, [pc, #260] ; (80057ac <pvPortMalloc+0x134>)
|
||
|
|
80056a8: 681a ldr r2, [r3, #0]
|
||
|
|
80056aa: 687b ldr r3, [r7, #4]
|
||
|
|
80056ac: 4013 ands r3, r2
|
||
|
|
80056ae: 2b00 cmp r3, #0
|
||
|
|
80056b0: d172 bne.n 8005798 <pvPortMalloc+0x120>
|
||
|
|
{
|
||
|
|
/* The wanted size is increased so it can contain a BlockLink_t
|
||
|
|
structure in addition to the requested amount of bytes. */
|
||
|
|
if( xWantedSize > 0 )
|
||
|
|
80056b2: 687b ldr r3, [r7, #4]
|
||
|
|
80056b4: 2b00 cmp r3, #0
|
||
|
|
80056b6: d00d beq.n 80056d4 <pvPortMalloc+0x5c>
|
||
|
|
{
|
||
|
|
xWantedSize += xHeapStructSize;
|
||
|
|
80056b8: 2208 movs r2, #8
|
||
|
|
80056ba: 687b ldr r3, [r7, #4]
|
||
|
|
80056bc: 4413 add r3, r2
|
||
|
|
80056be: 607b str r3, [r7, #4]
|
||
|
|
|
||
|
|
/* Ensure that blocks are always aligned to the required number
|
||
|
|
of bytes. */
|
||
|
|
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
|
||
|
|
80056c0: 687b ldr r3, [r7, #4]
|
||
|
|
80056c2: f003 0307 and.w r3, r3, #7
|
||
|
|
80056c6: 2b00 cmp r3, #0
|
||
|
|
80056c8: d004 beq.n 80056d4 <pvPortMalloc+0x5c>
|
||
|
|
{
|
||
|
|
/* Byte alignment required. */
|
||
|
|
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
|
||
|
|
80056ca: 687b ldr r3, [r7, #4]
|
||
|
|
80056cc: f023 0307 bic.w r3, r3, #7
|
||
|
|
80056d0: 3308 adds r3, #8
|
||
|
|
80056d2: 607b str r3, [r7, #4]
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
|
||
|
|
80056d4: 687b ldr r3, [r7, #4]
|
||
|
|
80056d6: 2b00 cmp r3, #0
|
||
|
|
80056d8: d05e beq.n 8005798 <pvPortMalloc+0x120>
|
||
|
|
80056da: 4b35 ldr r3, [pc, #212] ; (80057b0 <pvPortMalloc+0x138>)
|
||
|
|
80056dc: 681b ldr r3, [r3, #0]
|
||
|
|
80056de: 687a ldr r2, [r7, #4]
|
||
|
|
80056e0: 429a cmp r2, r3
|
||
|
|
80056e2: d859 bhi.n 8005798 <pvPortMalloc+0x120>
|
||
|
|
{
|
||
|
|
/* Traverse the list from the start (lowest address) block until
|
||
|
|
one of adequate size is found. */
|
||
|
|
pxPreviousBlock = &xStart;
|
||
|
|
80056e4: 4b33 ldr r3, [pc, #204] ; (80057b4 <pvPortMalloc+0x13c>)
|
||
|
|
80056e6: 61bb str r3, [r7, #24]
|
||
|
|
pxBlock = xStart.pxNextFreeBlock;
|
||
|
|
80056e8: 4b32 ldr r3, [pc, #200] ; (80057b4 <pvPortMalloc+0x13c>)
|
||
|
|
80056ea: 681b ldr r3, [r3, #0]
|
||
|
|
80056ec: 61fb str r3, [r7, #28]
|
||
|
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
||
|
|
80056ee: e004 b.n 80056fa <pvPortMalloc+0x82>
|
||
|
|
{
|
||
|
|
pxPreviousBlock = pxBlock;
|
||
|
|
80056f0: 69fb ldr r3, [r7, #28]
|
||
|
|
80056f2: 61bb str r3, [r7, #24]
|
||
|
|
pxBlock = pxBlock->pxNextFreeBlock;
|
||
|
|
80056f4: 69fb ldr r3, [r7, #28]
|
||
|
|
80056f6: 681b ldr r3, [r3, #0]
|
||
|
|
80056f8: 61fb str r3, [r7, #28]
|
||
|
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
||
|
|
80056fa: 69fb ldr r3, [r7, #28]
|
||
|
|
80056fc: 685b ldr r3, [r3, #4]
|
||
|
|
80056fe: 687a ldr r2, [r7, #4]
|
||
|
|
8005700: 429a cmp r2, r3
|
||
|
|
8005702: d903 bls.n 800570c <pvPortMalloc+0x94>
|
||
|
|
8005704: 69fb ldr r3, [r7, #28]
|
||
|
|
8005706: 681b ldr r3, [r3, #0]
|
||
|
|
8005708: 2b00 cmp r3, #0
|
||
|
|
800570a: d1f1 bne.n 80056f0 <pvPortMalloc+0x78>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If the end marker was reached then a block of adequate size
|
||
|
|
was not found. */
|
||
|
|
if( pxBlock != pxEnd )
|
||
|
|
800570c: 4b26 ldr r3, [pc, #152] ; (80057a8 <pvPortMalloc+0x130>)
|
||
|
|
800570e: 681b ldr r3, [r3, #0]
|
||
|
|
8005710: 69fa ldr r2, [r7, #28]
|
||
|
|
8005712: 429a cmp r2, r3
|
||
|
|
8005714: d040 beq.n 8005798 <pvPortMalloc+0x120>
|
||
|
|
{
|
||
|
|
/* Return the memory space pointed to - jumping over the
|
||
|
|
BlockLink_t structure at its start. */
|
||
|
|
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
|
||
|
|
8005716: 69bb ldr r3, [r7, #24]
|
||
|
|
8005718: 681b ldr r3, [r3, #0]
|
||
|
|
800571a: 2208 movs r2, #8
|
||
|
|
800571c: 4413 add r3, r2
|
||
|
|
800571e: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* This block is being returned for use so must be taken out
|
||
|
|
of the list of free blocks. */
|
||
|
|
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
|
||
|
|
8005720: 69fb ldr r3, [r7, #28]
|
||
|
|
8005722: 681a ldr r2, [r3, #0]
|
||
|
|
8005724: 69bb ldr r3, [r7, #24]
|
||
|
|
8005726: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* If the block is larger than required it can be split into
|
||
|
|
two. */
|
||
|
|
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
|
||
|
|
8005728: 69fb ldr r3, [r7, #28]
|
||
|
|
800572a: 685a ldr r2, [r3, #4]
|
||
|
|
800572c: 687b ldr r3, [r7, #4]
|
||
|
|
800572e: 1ad2 subs r2, r2, r3
|
||
|
|
8005730: 2308 movs r3, #8
|
||
|
|
8005732: 005b lsls r3, r3, #1
|
||
|
|
8005734: 429a cmp r2, r3
|
||
|
|
8005736: d90f bls.n 8005758 <pvPortMalloc+0xe0>
|
||
|
|
{
|
||
|
|
/* This block is to be split into two. Create a new
|
||
|
|
block following the number of bytes requested. The void
|
||
|
|
cast is used to prevent byte alignment warnings from the
|
||
|
|
compiler. */
|
||
|
|
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
|
||
|
|
8005738: 69fa ldr r2, [r7, #28]
|
||
|
|
800573a: 687b ldr r3, [r7, #4]
|
||
|
|
800573c: 4413 add r3, r2
|
||
|
|
800573e: 613b str r3, [r7, #16]
|
||
|
|
|
||
|
|
/* Calculate the sizes of two blocks split from the
|
||
|
|
single block. */
|
||
|
|
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
|
||
|
|
8005740: 69fb ldr r3, [r7, #28]
|
||
|
|
8005742: 685a ldr r2, [r3, #4]
|
||
|
|
8005744: 687b ldr r3, [r7, #4]
|
||
|
|
8005746: 1ad2 subs r2, r2, r3
|
||
|
|
8005748: 693b ldr r3, [r7, #16]
|
||
|
|
800574a: 605a str r2, [r3, #4]
|
||
|
|
pxBlock->xBlockSize = xWantedSize;
|
||
|
|
800574c: 69fb ldr r3, [r7, #28]
|
||
|
|
800574e: 687a ldr r2, [r7, #4]
|
||
|
|
8005750: 605a str r2, [r3, #4]
|
||
|
|
|
||
|
|
/* Insert the new block into the list of free blocks. */
|
||
|
|
prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
|
||
|
|
8005752: 6938 ldr r0, [r7, #16]
|
||
|
|
8005754: f000 f896 bl 8005884 <prvInsertBlockIntoFreeList>
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
xFreeBytesRemaining -= pxBlock->xBlockSize;
|
||
|
|
8005758: 4b15 ldr r3, [pc, #84] ; (80057b0 <pvPortMalloc+0x138>)
|
||
|
|
800575a: 681a ldr r2, [r3, #0]
|
||
|
|
800575c: 69fb ldr r3, [r7, #28]
|
||
|
|
800575e: 685b ldr r3, [r3, #4]
|
||
|
|
8005760: 1ad3 subs r3, r2, r3
|
||
|
|
8005762: 4a13 ldr r2, [pc, #76] ; (80057b0 <pvPortMalloc+0x138>)
|
||
|
|
8005764: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
|
||
|
|
8005766: 4b12 ldr r3, [pc, #72] ; (80057b0 <pvPortMalloc+0x138>)
|
||
|
|
8005768: 681a ldr r2, [r3, #0]
|
||
|
|
800576a: 4b13 ldr r3, [pc, #76] ; (80057b8 <pvPortMalloc+0x140>)
|
||
|
|
800576c: 681b ldr r3, [r3, #0]
|
||
|
|
800576e: 429a cmp r2, r3
|
||
|
|
8005770: d203 bcs.n 800577a <pvPortMalloc+0x102>
|
||
|
|
{
|
||
|
|
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
|
||
|
|
8005772: 4b0f ldr r3, [pc, #60] ; (80057b0 <pvPortMalloc+0x138>)
|
||
|
|
8005774: 681b ldr r3, [r3, #0]
|
||
|
|
8005776: 4a10 ldr r2, [pc, #64] ; (80057b8 <pvPortMalloc+0x140>)
|
||
|
|
8005778: 6013 str r3, [r2, #0]
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* The block is being returned - it is allocated and owned
|
||
|
|
by the application and has no "next" block. */
|
||
|
|
pxBlock->xBlockSize |= xBlockAllocatedBit;
|
||
|
|
800577a: 69fb ldr r3, [r7, #28]
|
||
|
|
800577c: 685a ldr r2, [r3, #4]
|
||
|
|
800577e: 4b0b ldr r3, [pc, #44] ; (80057ac <pvPortMalloc+0x134>)
|
||
|
|
8005780: 681b ldr r3, [r3, #0]
|
||
|
|
8005782: 431a orrs r2, r3
|
||
|
|
8005784: 69fb ldr r3, [r7, #28]
|
||
|
|
8005786: 605a str r2, [r3, #4]
|
||
|
|
pxBlock->pxNextFreeBlock = NULL;
|
||
|
|
8005788: 69fb ldr r3, [r7, #28]
|
||
|
|
800578a: 2200 movs r2, #0
|
||
|
|
800578c: 601a str r2, [r3, #0]
|
||
|
|
xNumberOfSuccessfulAllocations++;
|
||
|
|
800578e: 4b0b ldr r3, [pc, #44] ; (80057bc <pvPortMalloc+0x144>)
|
||
|
|
8005790: 681b ldr r3, [r3, #0]
|
||
|
|
8005792: 3301 adds r3, #1
|
||
|
|
8005794: 4a09 ldr r2, [pc, #36] ; (80057bc <pvPortMalloc+0x144>)
|
||
|
|
8005796: 6013 str r3, [r2, #0]
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
traceMALLOC( pvReturn, xWantedSize );
|
||
|
|
}
|
||
|
|
( void ) xTaskResumeAll();
|
||
|
|
8005798: f7fe fd0c bl 80041b4 <xTaskResumeAll>
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return pvReturn;
|
||
|
|
800579c: 697b ldr r3, [r7, #20]
|
||
|
|
}
|
||
|
|
800579e: 4618 mov r0, r3
|
||
|
|
80057a0: 3720 adds r7, #32
|
||
|
|
80057a2: 46bd mov sp, r7
|
||
|
|
80057a4: bd80 pop {r7, pc}
|
||
|
|
80057a6: bf00 nop
|
||
|
|
80057a8: 20003e04 .word 0x20003e04
|
||
|
|
80057ac: 20003e18 .word 0x20003e18
|
||
|
|
80057b0: 20003e08 .word 0x20003e08
|
||
|
|
80057b4: 20003dfc .word 0x20003dfc
|
||
|
|
80057b8: 20003e0c .word 0x20003e0c
|
||
|
|
80057bc: 20003e10 .word 0x20003e10
|
||
|
|
|
||
|
|
080057c0 <vPortFree>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vPortFree( void *pv )
|
||
|
|
{
|
||
|
|
80057c0: b580 push {r7, lr}
|
||
|
|
80057c2: b086 sub sp, #24
|
||
|
|
80057c4: af00 add r7, sp, #0
|
||
|
|
80057c6: 6078 str r0, [r7, #4]
|
||
|
|
uint8_t *puc = ( uint8_t * ) pv;
|
||
|
|
80057c8: 687b ldr r3, [r7, #4]
|
||
|
|
80057ca: 617b str r3, [r7, #20]
|
||
|
|
BlockLink_t *pxLink;
|
||
|
|
|
||
|
|
if( pv != NULL )
|
||
|
|
80057cc: 687b ldr r3, [r7, #4]
|
||
|
|
80057ce: 2b00 cmp r3, #0
|
||
|
|
80057d0: d04d beq.n 800586e <vPortFree+0xae>
|
||
|
|
{
|
||
|
|
/* The memory being freed will have an BlockLink_t structure immediately
|
||
|
|
before it. */
|
||
|
|
puc -= xHeapStructSize;
|
||
|
|
80057d2: 2308 movs r3, #8
|
||
|
|
80057d4: 425b negs r3, r3
|
||
|
|
80057d6: 697a ldr r2, [r7, #20]
|
||
|
|
80057d8: 4413 add r3, r2
|
||
|
|
80057da: 617b str r3, [r7, #20]
|
||
|
|
|
||
|
|
/* This casting is to keep the compiler from issuing warnings. */
|
||
|
|
pxLink = ( void * ) puc;
|
||
|
|
80057dc: 697b ldr r3, [r7, #20]
|
||
|
|
80057de: 613b str r3, [r7, #16]
|
||
|
|
|
||
|
|
/* Check the block is actually allocated. */
|
||
|
|
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
|
||
|
|
80057e0: 693b ldr r3, [r7, #16]
|
||
|
|
80057e2: 685a ldr r2, [r3, #4]
|
||
|
|
80057e4: 4b24 ldr r3, [pc, #144] ; (8005878 <vPortFree+0xb8>)
|
||
|
|
80057e6: 681b ldr r3, [r3, #0]
|
||
|
|
80057e8: 4013 ands r3, r2
|
||
|
|
80057ea: 2b00 cmp r3, #0
|
||
|
|
80057ec: d10a bne.n 8005804 <vPortFree+0x44>
|
||
|
|
__asm volatile
|
||
|
|
80057ee: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80057f2: f383 8811 msr BASEPRI, r3
|
||
|
|
80057f6: f3bf 8f6f isb sy
|
||
|
|
80057fa: f3bf 8f4f dsb sy
|
||
|
|
80057fe: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
8005800: bf00 nop
|
||
|
|
8005802: e7fe b.n 8005802 <vPortFree+0x42>
|
||
|
|
configASSERT( pxLink->pxNextFreeBlock == NULL );
|
||
|
|
8005804: 693b ldr r3, [r7, #16]
|
||
|
|
8005806: 681b ldr r3, [r3, #0]
|
||
|
|
8005808: 2b00 cmp r3, #0
|
||
|
|
800580a: d00a beq.n 8005822 <vPortFree+0x62>
|
||
|
|
__asm volatile
|
||
|
|
800580c: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005810: f383 8811 msr BASEPRI, r3
|
||
|
|
8005814: f3bf 8f6f isb sy
|
||
|
|
8005818: f3bf 8f4f dsb sy
|
||
|
|
800581c: 60bb str r3, [r7, #8]
|
||
|
|
}
|
||
|
|
800581e: bf00 nop
|
||
|
|
8005820: e7fe b.n 8005820 <vPortFree+0x60>
|
||
|
|
|
||
|
|
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
|
||
|
|
8005822: 693b ldr r3, [r7, #16]
|
||
|
|
8005824: 685a ldr r2, [r3, #4]
|
||
|
|
8005826: 4b14 ldr r3, [pc, #80] ; (8005878 <vPortFree+0xb8>)
|
||
|
|
8005828: 681b ldr r3, [r3, #0]
|
||
|
|
800582a: 4013 ands r3, r2
|
||
|
|
800582c: 2b00 cmp r3, #0
|
||
|
|
800582e: d01e beq.n 800586e <vPortFree+0xae>
|
||
|
|
{
|
||
|
|
if( pxLink->pxNextFreeBlock == NULL )
|
||
|
|
8005830: 693b ldr r3, [r7, #16]
|
||
|
|
8005832: 681b ldr r3, [r3, #0]
|
||
|
|
8005834: 2b00 cmp r3, #0
|
||
|
|
8005836: d11a bne.n 800586e <vPortFree+0xae>
|
||
|
|
{
|
||
|
|
/* The block is being returned to the heap - it is no longer
|
||
|
|
allocated. */
|
||
|
|
pxLink->xBlockSize &= ~xBlockAllocatedBit;
|
||
|
|
8005838: 693b ldr r3, [r7, #16]
|
||
|
|
800583a: 685a ldr r2, [r3, #4]
|
||
|
|
800583c: 4b0e ldr r3, [pc, #56] ; (8005878 <vPortFree+0xb8>)
|
||
|
|
800583e: 681b ldr r3, [r3, #0]
|
||
|
|
8005840: 43db mvns r3, r3
|
||
|
|
8005842: 401a ands r2, r3
|
||
|
|
8005844: 693b ldr r3, [r7, #16]
|
||
|
|
8005846: 605a str r2, [r3, #4]
|
||
|
|
|
||
|
|
vTaskSuspendAll();
|
||
|
|
8005848: f7fe fca6 bl 8004198 <vTaskSuspendAll>
|
||
|
|
{
|
||
|
|
/* Add this block to the list of free blocks. */
|
||
|
|
xFreeBytesRemaining += pxLink->xBlockSize;
|
||
|
|
800584c: 693b ldr r3, [r7, #16]
|
||
|
|
800584e: 685a ldr r2, [r3, #4]
|
||
|
|
8005850: 4b0a ldr r3, [pc, #40] ; (800587c <vPortFree+0xbc>)
|
||
|
|
8005852: 681b ldr r3, [r3, #0]
|
||
|
|
8005854: 4413 add r3, r2
|
||
|
|
8005856: 4a09 ldr r2, [pc, #36] ; (800587c <vPortFree+0xbc>)
|
||
|
|
8005858: 6013 str r3, [r2, #0]
|
||
|
|
traceFREE( pv, pxLink->xBlockSize );
|
||
|
|
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
|
||
|
|
800585a: 6938 ldr r0, [r7, #16]
|
||
|
|
800585c: f000 f812 bl 8005884 <prvInsertBlockIntoFreeList>
|
||
|
|
xNumberOfSuccessfulFrees++;
|
||
|
|
8005860: 4b07 ldr r3, [pc, #28] ; (8005880 <vPortFree+0xc0>)
|
||
|
|
8005862: 681b ldr r3, [r3, #0]
|
||
|
|
8005864: 3301 adds r3, #1
|
||
|
|
8005866: 4a06 ldr r2, [pc, #24] ; (8005880 <vPortFree+0xc0>)
|
||
|
|
8005868: 6013 str r3, [r2, #0]
|
||
|
|
}
|
||
|
|
( void ) xTaskResumeAll();
|
||
|
|
800586a: f7fe fca3 bl 80041b4 <xTaskResumeAll>
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
800586e: bf00 nop
|
||
|
|
8005870: 3718 adds r7, #24
|
||
|
|
8005872: 46bd mov sp, r7
|
||
|
|
8005874: bd80 pop {r7, pc}
|
||
|
|
8005876: bf00 nop
|
||
|
|
8005878: 20003e18 .word 0x20003e18
|
||
|
|
800587c: 20003e08 .word 0x20003e08
|
||
|
|
8005880: 20003e14 .word 0x20003e14
|
||
|
|
|
||
|
|
08005884 <prvInsertBlockIntoFreeList>:
|
||
|
|
return xMinimumEverFreeBytesRemaining;
|
||
|
|
}
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
|
||
|
|
{
|
||
|
|
8005884: b480 push {r7}
|
||
|
|
8005886: b085 sub sp, #20
|
||
|
|
8005888: af00 add r7, sp, #0
|
||
|
|
800588a: 6078 str r0, [r7, #4]
|
||
|
|
BlockLink_t *pxIterator;
|
||
|
|
uint8_t *puc;
|
||
|
|
|
||
|
|
/* Iterate through the list until a block is found that has a higher address
|
||
|
|
than the block being inserted. */
|
||
|
|
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
|
||
|
|
800588c: 4b28 ldr r3, [pc, #160] ; (8005930 <prvInsertBlockIntoFreeList+0xac>)
|
||
|
|
800588e: 60fb str r3, [r7, #12]
|
||
|
|
8005890: e002 b.n 8005898 <prvInsertBlockIntoFreeList+0x14>
|
||
|
|
8005892: 68fb ldr r3, [r7, #12]
|
||
|
|
8005894: 681b ldr r3, [r3, #0]
|
||
|
|
8005896: 60fb str r3, [r7, #12]
|
||
|
|
8005898: 68fb ldr r3, [r7, #12]
|
||
|
|
800589a: 681b ldr r3, [r3, #0]
|
||
|
|
800589c: 687a ldr r2, [r7, #4]
|
||
|
|
800589e: 429a cmp r2, r3
|
||
|
|
80058a0: d8f7 bhi.n 8005892 <prvInsertBlockIntoFreeList+0xe>
|
||
|
|
/* Nothing to do here, just iterate to the right position. */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Do the block being inserted, and the block it is being inserted after
|
||
|
|
make a contiguous block of memory? */
|
||
|
|
puc = ( uint8_t * ) pxIterator;
|
||
|
|
80058a2: 68fb ldr r3, [r7, #12]
|
||
|
|
80058a4: 60bb str r3, [r7, #8]
|
||
|
|
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
|
||
|
|
80058a6: 68fb ldr r3, [r7, #12]
|
||
|
|
80058a8: 685b ldr r3, [r3, #4]
|
||
|
|
80058aa: 68ba ldr r2, [r7, #8]
|
||
|
|
80058ac: 4413 add r3, r2
|
||
|
|
80058ae: 687a ldr r2, [r7, #4]
|
||
|
|
80058b0: 429a cmp r2, r3
|
||
|
|
80058b2: d108 bne.n 80058c6 <prvInsertBlockIntoFreeList+0x42>
|
||
|
|
{
|
||
|
|
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
|
||
|
|
80058b4: 68fb ldr r3, [r7, #12]
|
||
|
|
80058b6: 685a ldr r2, [r3, #4]
|
||
|
|
80058b8: 687b ldr r3, [r7, #4]
|
||
|
|
80058ba: 685b ldr r3, [r3, #4]
|
||
|
|
80058bc: 441a add r2, r3
|
||
|
|
80058be: 68fb ldr r3, [r7, #12]
|
||
|
|
80058c0: 605a str r2, [r3, #4]
|
||
|
|
pxBlockToInsert = pxIterator;
|
||
|
|
80058c2: 68fb ldr r3, [r7, #12]
|
||
|
|
80058c4: 607b str r3, [r7, #4]
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Do the block being inserted, and the block it is being inserted before
|
||
|
|
make a contiguous block of memory? */
|
||
|
|
puc = ( uint8_t * ) pxBlockToInsert;
|
||
|
|
80058c6: 687b ldr r3, [r7, #4]
|
||
|
|
80058c8: 60bb str r3, [r7, #8]
|
||
|
|
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
|
||
|
|
80058ca: 687b ldr r3, [r7, #4]
|
||
|
|
80058cc: 685b ldr r3, [r3, #4]
|
||
|
|
80058ce: 68ba ldr r2, [r7, #8]
|
||
|
|
80058d0: 441a add r2, r3
|
||
|
|
80058d2: 68fb ldr r3, [r7, #12]
|
||
|
|
80058d4: 681b ldr r3, [r3, #0]
|
||
|
|
80058d6: 429a cmp r2, r3
|
||
|
|
80058d8: d118 bne.n 800590c <prvInsertBlockIntoFreeList+0x88>
|
||
|
|
{
|
||
|
|
if( pxIterator->pxNextFreeBlock != pxEnd )
|
||
|
|
80058da: 68fb ldr r3, [r7, #12]
|
||
|
|
80058dc: 681a ldr r2, [r3, #0]
|
||
|
|
80058de: 4b15 ldr r3, [pc, #84] ; (8005934 <prvInsertBlockIntoFreeList+0xb0>)
|
||
|
|
80058e0: 681b ldr r3, [r3, #0]
|
||
|
|
80058e2: 429a cmp r2, r3
|
||
|
|
80058e4: d00d beq.n 8005902 <prvInsertBlockIntoFreeList+0x7e>
|
||
|
|
{
|
||
|
|
/* Form one big block from the two blocks. */
|
||
|
|
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
|
||
|
|
80058e6: 687b ldr r3, [r7, #4]
|
||
|
|
80058e8: 685a ldr r2, [r3, #4]
|
||
|
|
80058ea: 68fb ldr r3, [r7, #12]
|
||
|
|
80058ec: 681b ldr r3, [r3, #0]
|
||
|
|
80058ee: 685b ldr r3, [r3, #4]
|
||
|
|
80058f0: 441a add r2, r3
|
||
|
|
80058f2: 687b ldr r3, [r7, #4]
|
||
|
|
80058f4: 605a str r2, [r3, #4]
|
||
|
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
|
||
|
|
80058f6: 68fb ldr r3, [r7, #12]
|
||
|
|
80058f8: 681b ldr r3, [r3, #0]
|
||
|
|
80058fa: 681a ldr r2, [r3, #0]
|
||
|
|
80058fc: 687b ldr r3, [r7, #4]
|
||
|
|
80058fe: 601a str r2, [r3, #0]
|
||
|
|
8005900: e008 b.n 8005914 <prvInsertBlockIntoFreeList+0x90>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
pxBlockToInsert->pxNextFreeBlock = pxEnd;
|
||
|
|
8005902: 4b0c ldr r3, [pc, #48] ; (8005934 <prvInsertBlockIntoFreeList+0xb0>)
|
||
|
|
8005904: 681a ldr r2, [r3, #0]
|
||
|
|
8005906: 687b ldr r3, [r7, #4]
|
||
|
|
8005908: 601a str r2, [r3, #0]
|
||
|
|
800590a: e003 b.n 8005914 <prvInsertBlockIntoFreeList+0x90>
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
|
||
|
|
800590c: 68fb ldr r3, [r7, #12]
|
||
|
|
800590e: 681a ldr r2, [r3, #0]
|
||
|
|
8005910: 687b ldr r3, [r7, #4]
|
||
|
|
8005912: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* If the block being inserted plugged a gab, so was merged with the block
|
||
|
|
before and the block after, then it's pxNextFreeBlock pointer will have
|
||
|
|
already been set, and should not be set here as that would make it point
|
||
|
|
to itself. */
|
||
|
|
if( pxIterator != pxBlockToInsert )
|
||
|
|
8005914: 68fa ldr r2, [r7, #12]
|
||
|
|
8005916: 687b ldr r3, [r7, #4]
|
||
|
|
8005918: 429a cmp r2, r3
|
||
|
|
800591a: d002 beq.n 8005922 <prvInsertBlockIntoFreeList+0x9e>
|
||
|
|
{
|
||
|
|
pxIterator->pxNextFreeBlock = pxBlockToInsert;
|
||
|
|
800591c: 68fb ldr r3, [r7, #12]
|
||
|
|
800591e: 687a ldr r2, [r7, #4]
|
||
|
|
8005920: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mtCOVERAGE_TEST_MARKER();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
8005922: bf00 nop
|
||
|
|
8005924: 3714 adds r7, #20
|
||
|
|
8005926: 46bd mov sp, r7
|
||
|
|
8005928: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
800592c: 4770 bx lr
|
||
|
|
800592e: bf00 nop
|
||
|
|
8005930: 20003dfc .word 0x20003dfc
|
||
|
|
8005934: 20003e04 .word 0x20003e04
|
||
|
|
|
||
|
|
08005938 <vPortDefineHeapRegions>:
|
||
|
|
/*-----------------------------------------------------------*/
|
||
|
|
|
||
|
|
void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
|
||
|
|
{
|
||
|
|
8005938: b480 push {r7}
|
||
|
|
800593a: b08f sub sp, #60 ; 0x3c
|
||
|
|
800593c: af00 add r7, sp, #0
|
||
|
|
800593e: 6078 str r0, [r7, #4]
|
||
|
|
BlockLink_t *pxFirstFreeBlockInRegion = NULL, *pxPreviousFreeBlock;
|
||
|
|
8005940: 2300 movs r3, #0
|
||
|
|
8005942: 623b str r3, [r7, #32]
|
||
|
|
size_t xAlignedHeap;
|
||
|
|
size_t xTotalRegionSize, xTotalHeapSize = 0;
|
||
|
|
8005944: 2300 movs r3, #0
|
||
|
|
8005946: 633b str r3, [r7, #48] ; 0x30
|
||
|
|
BaseType_t xDefinedRegions = 0;
|
||
|
|
8005948: 2300 movs r3, #0
|
||
|
|
800594a: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
size_t xAddress;
|
||
|
|
const HeapRegion_t *pxHeapRegion;
|
||
|
|
|
||
|
|
/* Can only call once! */
|
||
|
|
configASSERT( pxEnd == NULL );
|
||
|
|
800594c: 4b5a ldr r3, [pc, #360] ; (8005ab8 <vPortDefineHeapRegions+0x180>)
|
||
|
|
800594e: 681b ldr r3, [r3, #0]
|
||
|
|
8005950: 2b00 cmp r3, #0
|
||
|
|
8005952: d00a beq.n 800596a <vPortDefineHeapRegions+0x32>
|
||
|
|
__asm volatile
|
||
|
|
8005954: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005958: f383 8811 msr BASEPRI, r3
|
||
|
|
800595c: f3bf 8f6f isb sy
|
||
|
|
8005960: f3bf 8f4f dsb sy
|
||
|
|
8005964: 617b str r3, [r7, #20]
|
||
|
|
}
|
||
|
|
8005966: bf00 nop
|
||
|
|
8005968: e7fe b.n 8005968 <vPortDefineHeapRegions+0x30>
|
||
|
|
|
||
|
|
pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
|
||
|
|
800596a: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
800596c: 00db lsls r3, r3, #3
|
||
|
|
800596e: 687a ldr r2, [r7, #4]
|
||
|
|
8005970: 4413 add r3, r2
|
||
|
|
8005972: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
|
||
|
|
while( pxHeapRegion->xSizeInBytes > 0 )
|
||
|
|
8005974: e07d b.n 8005a72 <vPortDefineHeapRegions+0x13a>
|
||
|
|
{
|
||
|
|
xTotalRegionSize = pxHeapRegion->xSizeInBytes;
|
||
|
|
8005976: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8005978: 685b ldr r3, [r3, #4]
|
||
|
|
800597a: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
|
||
|
|
/* Ensure the heap region starts on a correctly aligned boundary. */
|
||
|
|
xAddress = ( size_t ) pxHeapRegion->pucStartAddress;
|
||
|
|
800597c: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
800597e: 681b ldr r3, [r3, #0]
|
||
|
|
8005980: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
|
||
|
|
8005982: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8005984: f003 0307 and.w r3, r3, #7
|
||
|
|
8005988: 2b00 cmp r3, #0
|
||
|
|
800598a: d00e beq.n 80059aa <vPortDefineHeapRegions+0x72>
|
||
|
|
{
|
||
|
|
xAddress += ( portBYTE_ALIGNMENT - 1 );
|
||
|
|
800598c: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
800598e: 3307 adds r3, #7
|
||
|
|
8005990: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
xAddress &= ~portBYTE_ALIGNMENT_MASK;
|
||
|
|
8005992: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8005994: f023 0307 bic.w r3, r3, #7
|
||
|
|
8005998: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
|
||
|
|
/* Adjust the size for the bytes lost to alignment. */
|
||
|
|
xTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress;
|
||
|
|
800599a: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
800599c: 681b ldr r3, [r3, #0]
|
||
|
|
800599e: 461a mov r2, r3
|
||
|
|
80059a0: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80059a2: 1ad3 subs r3, r2, r3
|
||
|
|
80059a4: 6b7a ldr r2, [r7, #52] ; 0x34
|
||
|
|
80059a6: 4413 add r3, r2
|
||
|
|
80059a8: 637b str r3, [r7, #52] ; 0x34
|
||
|
|
}
|
||
|
|
|
||
|
|
xAlignedHeap = xAddress;
|
||
|
|
80059aa: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80059ac: 61fb str r3, [r7, #28]
|
||
|
|
|
||
|
|
/* Set xStart if it has not already been set. */
|
||
|
|
if( xDefinedRegions == 0 )
|
||
|
|
80059ae: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
80059b0: 2b00 cmp r3, #0
|
||
|
|
80059b2: d106 bne.n 80059c2 <vPortDefineHeapRegions+0x8a>
|
||
|
|
{
|
||
|
|
/* xStart is used to hold a pointer to the first item in the list of
|
||
|
|
free blocks. The void cast is used to prevent compiler warnings. */
|
||
|
|
xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;
|
||
|
|
80059b4: 69fb ldr r3, [r7, #28]
|
||
|
|
80059b6: 4a41 ldr r2, [pc, #260] ; (8005abc <vPortDefineHeapRegions+0x184>)
|
||
|
|
80059b8: 6013 str r3, [r2, #0]
|
||
|
|
xStart.xBlockSize = ( size_t ) 0;
|
||
|
|
80059ba: 4b40 ldr r3, [pc, #256] ; (8005abc <vPortDefineHeapRegions+0x184>)
|
||
|
|
80059bc: 2200 movs r2, #0
|
||
|
|
80059be: 605a str r2, [r3, #4]
|
||
|
|
80059c0: e01f b.n 8005a02 <vPortDefineHeapRegions+0xca>
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Should only get here if one region has already been added to the
|
||
|
|
heap. */
|
||
|
|
configASSERT( pxEnd != NULL );
|
||
|
|
80059c2: 4b3d ldr r3, [pc, #244] ; (8005ab8 <vPortDefineHeapRegions+0x180>)
|
||
|
|
80059c4: 681b ldr r3, [r3, #0]
|
||
|
|
80059c6: 2b00 cmp r3, #0
|
||
|
|
80059c8: d10a bne.n 80059e0 <vPortDefineHeapRegions+0xa8>
|
||
|
|
__asm volatile
|
||
|
|
80059ca: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80059ce: f383 8811 msr BASEPRI, r3
|
||
|
|
80059d2: f3bf 8f6f isb sy
|
||
|
|
80059d6: f3bf 8f4f dsb sy
|
||
|
|
80059da: 613b str r3, [r7, #16]
|
||
|
|
}
|
||
|
|
80059dc: bf00 nop
|
||
|
|
80059de: e7fe b.n 80059de <vPortDefineHeapRegions+0xa6>
|
||
|
|
|
||
|
|
/* Check blocks are passed in with increasing start addresses. */
|
||
|
|
configASSERT( xAddress > ( size_t ) pxEnd );
|
||
|
|
80059e0: 4b35 ldr r3, [pc, #212] ; (8005ab8 <vPortDefineHeapRegions+0x180>)
|
||
|
|
80059e2: 681b ldr r3, [r3, #0]
|
||
|
|
80059e4: 461a mov r2, r3
|
||
|
|
80059e6: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
80059e8: 4293 cmp r3, r2
|
||
|
|
80059ea: d80a bhi.n 8005a02 <vPortDefineHeapRegions+0xca>
|
||
|
|
__asm volatile
|
||
|
|
80059ec: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
80059f0: f383 8811 msr BASEPRI, r3
|
||
|
|
80059f4: f3bf 8f6f isb sy
|
||
|
|
80059f8: f3bf 8f4f dsb sy
|
||
|
|
80059fc: 60fb str r3, [r7, #12]
|
||
|
|
}
|
||
|
|
80059fe: bf00 nop
|
||
|
|
8005a00: e7fe b.n 8005a00 <vPortDefineHeapRegions+0xc8>
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Remember the location of the end marker in the previous region, if
|
||
|
|
any. */
|
||
|
|
pxPreviousFreeBlock = pxEnd;
|
||
|
|
8005a02: 4b2d ldr r3, [pc, #180] ; (8005ab8 <vPortDefineHeapRegions+0x180>)
|
||
|
|
8005a04: 681b ldr r3, [r3, #0]
|
||
|
|
8005a06: 61bb str r3, [r7, #24]
|
||
|
|
|
||
|
|
/* pxEnd is used to mark the end of the list of free blocks and is
|
||
|
|
inserted at the end of the region space. */
|
||
|
|
xAddress = xAlignedHeap + xTotalRegionSize;
|
||
|
|
8005a08: 69fa ldr r2, [r7, #28]
|
||
|
|
8005a0a: 6b7b ldr r3, [r7, #52] ; 0x34
|
||
|
|
8005a0c: 4413 add r3, r2
|
||
|
|
8005a0e: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
xAddress -= xHeapStructSize;
|
||
|
|
8005a10: 2208 movs r2, #8
|
||
|
|
8005a12: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8005a14: 1a9b subs r3, r3, r2
|
||
|
|
8005a16: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
xAddress &= ~portBYTE_ALIGNMENT_MASK;
|
||
|
|
8005a18: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8005a1a: f023 0307 bic.w r3, r3, #7
|
||
|
|
8005a1e: 62bb str r3, [r7, #40] ; 0x28
|
||
|
|
pxEnd = ( BlockLink_t * ) xAddress;
|
||
|
|
8005a20: 6abb ldr r3, [r7, #40] ; 0x28
|
||
|
|
8005a22: 4a25 ldr r2, [pc, #148] ; (8005ab8 <vPortDefineHeapRegions+0x180>)
|
||
|
|
8005a24: 6013 str r3, [r2, #0]
|
||
|
|
pxEnd->xBlockSize = 0;
|
||
|
|
8005a26: 4b24 ldr r3, [pc, #144] ; (8005ab8 <vPortDefineHeapRegions+0x180>)
|
||
|
|
8005a28: 681b ldr r3, [r3, #0]
|
||
|
|
8005a2a: 2200 movs r2, #0
|
||
|
|
8005a2c: 605a str r2, [r3, #4]
|
||
|
|
pxEnd->pxNextFreeBlock = NULL;
|
||
|
|
8005a2e: 4b22 ldr r3, [pc, #136] ; (8005ab8 <vPortDefineHeapRegions+0x180>)
|
||
|
|
8005a30: 681b ldr r3, [r3, #0]
|
||
|
|
8005a32: 2200 movs r2, #0
|
||
|
|
8005a34: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* To start with there is a single free block in this region that is
|
||
|
|
sized to take up the entire heap region minus the space taken by the
|
||
|
|
free block structure. */
|
||
|
|
pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;
|
||
|
|
8005a36: 69fb ldr r3, [r7, #28]
|
||
|
|
8005a38: 623b str r3, [r7, #32]
|
||
|
|
pxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion;
|
||
|
|
8005a3a: 6a3b ldr r3, [r7, #32]
|
||
|
|
8005a3c: 6aba ldr r2, [r7, #40] ; 0x28
|
||
|
|
8005a3e: 1ad2 subs r2, r2, r3
|
||
|
|
8005a40: 6a3b ldr r3, [r7, #32]
|
||
|
|
8005a42: 605a str r2, [r3, #4]
|
||
|
|
pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
|
||
|
|
8005a44: 4b1c ldr r3, [pc, #112] ; (8005ab8 <vPortDefineHeapRegions+0x180>)
|
||
|
|
8005a46: 681a ldr r2, [r3, #0]
|
||
|
|
8005a48: 6a3b ldr r3, [r7, #32]
|
||
|
|
8005a4a: 601a str r2, [r3, #0]
|
||
|
|
|
||
|
|
/* If this is not the first region that makes up the entire heap space
|
||
|
|
then link the previous region to this region. */
|
||
|
|
if( pxPreviousFreeBlock != NULL )
|
||
|
|
8005a4c: 69bb ldr r3, [r7, #24]
|
||
|
|
8005a4e: 2b00 cmp r3, #0
|
||
|
|
8005a50: d002 beq.n 8005a58 <vPortDefineHeapRegions+0x120>
|
||
|
|
{
|
||
|
|
pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;
|
||
|
|
8005a52: 69bb ldr r3, [r7, #24]
|
||
|
|
8005a54: 6a3a ldr r2, [r7, #32]
|
||
|
|
8005a56: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
|
||
|
|
xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;
|
||
|
|
8005a58: 6a3b ldr r3, [r7, #32]
|
||
|
|
8005a5a: 685b ldr r3, [r3, #4]
|
||
|
|
8005a5c: 6b3a ldr r2, [r7, #48] ; 0x30
|
||
|
|
8005a5e: 4413 add r3, r2
|
||
|
|
8005a60: 633b str r3, [r7, #48] ; 0x30
|
||
|
|
|
||
|
|
/* Move onto the next HeapRegion_t structure. */
|
||
|
|
xDefinedRegions++;
|
||
|
|
8005a62: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8005a64: 3301 adds r3, #1
|
||
|
|
8005a66: 62fb str r3, [r7, #44] ; 0x2c
|
||
|
|
pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
|
||
|
|
8005a68: 6afb ldr r3, [r7, #44] ; 0x2c
|
||
|
|
8005a6a: 00db lsls r3, r3, #3
|
||
|
|
8005a6c: 687a ldr r2, [r7, #4]
|
||
|
|
8005a6e: 4413 add r3, r2
|
||
|
|
8005a70: 627b str r3, [r7, #36] ; 0x24
|
||
|
|
while( pxHeapRegion->xSizeInBytes > 0 )
|
||
|
|
8005a72: 6a7b ldr r3, [r7, #36] ; 0x24
|
||
|
|
8005a74: 685b ldr r3, [r3, #4]
|
||
|
|
8005a76: 2b00 cmp r3, #0
|
||
|
|
8005a78: f47f af7d bne.w 8005976 <vPortDefineHeapRegions+0x3e>
|
||
|
|
}
|
||
|
|
|
||
|
|
xMinimumEverFreeBytesRemaining = xTotalHeapSize;
|
||
|
|
8005a7c: 4a10 ldr r2, [pc, #64] ; (8005ac0 <vPortDefineHeapRegions+0x188>)
|
||
|
|
8005a7e: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8005a80: 6013 str r3, [r2, #0]
|
||
|
|
xFreeBytesRemaining = xTotalHeapSize;
|
||
|
|
8005a82: 4a10 ldr r2, [pc, #64] ; (8005ac4 <vPortDefineHeapRegions+0x18c>)
|
||
|
|
8005a84: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8005a86: 6013 str r3, [r2, #0]
|
||
|
|
|
||
|
|
/* Check something was actually defined before it is accessed. */
|
||
|
|
configASSERT( xTotalHeapSize );
|
||
|
|
8005a88: 6b3b ldr r3, [r7, #48] ; 0x30
|
||
|
|
8005a8a: 2b00 cmp r3, #0
|
||
|
|
8005a8c: d10a bne.n 8005aa4 <vPortDefineHeapRegions+0x16c>
|
||
|
|
__asm volatile
|
||
|
|
8005a8e: f04f 0350 mov.w r3, #80 ; 0x50
|
||
|
|
8005a92: f383 8811 msr BASEPRI, r3
|
||
|
|
8005a96: f3bf 8f6f isb sy
|
||
|
|
8005a9a: f3bf 8f4f dsb sy
|
||
|
|
8005a9e: 60bb str r3, [r7, #8]
|
||
|
|
}
|
||
|
|
8005aa0: bf00 nop
|
||
|
|
8005aa2: e7fe b.n 8005aa2 <vPortDefineHeapRegions+0x16a>
|
||
|
|
|
||
|
|
/* Work out the position of the top bit in a size_t variable. */
|
||
|
|
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
|
||
|
|
8005aa4: 4b08 ldr r3, [pc, #32] ; (8005ac8 <vPortDefineHeapRegions+0x190>)
|
||
|
|
8005aa6: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
|
||
|
|
8005aaa: 601a str r2, [r3, #0]
|
||
|
|
}
|
||
|
|
8005aac: bf00 nop
|
||
|
|
8005aae: 373c adds r7, #60 ; 0x3c
|
||
|
|
8005ab0: 46bd mov sp, r7
|
||
|
|
8005ab2: f85d 7b04 ldr.w r7, [sp], #4
|
||
|
|
8005ab6: 4770 bx lr
|
||
|
|
8005ab8: 20003e04 .word 0x20003e04
|
||
|
|
8005abc: 20003dfc .word 0x20003dfc
|
||
|
|
8005ac0: 20003e0c .word 0x20003e0c
|
||
|
|
8005ac4: 20003e08 .word 0x20003e08
|
||
|
|
8005ac8: 20003e18 .word 0x20003e18
|
||
|
|
|
||
|
|
08005acc <__libc_init_array>:
|
||
|
|
8005acc: b570 push {r4, r5, r6, lr}
|
||
|
|
8005ace: 4d0d ldr r5, [pc, #52] ; (8005b04 <__libc_init_array+0x38>)
|
||
|
|
8005ad0: 4c0d ldr r4, [pc, #52] ; (8005b08 <__libc_init_array+0x3c>)
|
||
|
|
8005ad2: 1b64 subs r4, r4, r5
|
||
|
|
8005ad4: 10a4 asrs r4, r4, #2
|
||
|
|
8005ad6: 2600 movs r6, #0
|
||
|
|
8005ad8: 42a6 cmp r6, r4
|
||
|
|
8005ada: d109 bne.n 8005af0 <__libc_init_array+0x24>
|
||
|
|
8005adc: 4d0b ldr r5, [pc, #44] ; (8005b0c <__libc_init_array+0x40>)
|
||
|
|
8005ade: 4c0c ldr r4, [pc, #48] ; (8005b10 <__libc_init_array+0x44>)
|
||
|
|
8005ae0: f000 f8f2 bl 8005cc8 <_init>
|
||
|
|
8005ae4: 1b64 subs r4, r4, r5
|
||
|
|
8005ae6: 10a4 asrs r4, r4, #2
|
||
|
|
8005ae8: 2600 movs r6, #0
|
||
|
|
8005aea: 42a6 cmp r6, r4
|
||
|
|
8005aec: d105 bne.n 8005afa <__libc_init_array+0x2e>
|
||
|
|
8005aee: bd70 pop {r4, r5, r6, pc}
|
||
|
|
8005af0: f855 3b04 ldr.w r3, [r5], #4
|
||
|
|
8005af4: 4798 blx r3
|
||
|
|
8005af6: 3601 adds r6, #1
|
||
|
|
8005af8: e7ee b.n 8005ad8 <__libc_init_array+0xc>
|
||
|
|
8005afa: f855 3b04 ldr.w r3, [r5], #4
|
||
|
|
8005afe: 4798 blx r3
|
||
|
|
8005b00: 3601 adds r6, #1
|
||
|
|
8005b02: e7f2 b.n 8005aea <__libc_init_array+0x1e>
|
||
|
|
8005b04: 08005dd8 .word 0x08005dd8
|
||
|
|
8005b08: 08005dd8 .word 0x08005dd8
|
||
|
|
8005b0c: 08005dd8 .word 0x08005dd8
|
||
|
|
8005b10: 08005ddc .word 0x08005ddc
|
||
|
|
|
||
|
|
08005b14 <__retarget_lock_acquire_recursive>:
|
||
|
|
8005b14: 4770 bx lr
|
||
|
|
|
||
|
|
08005b16 <__retarget_lock_release_recursive>:
|
||
|
|
8005b16: 4770 bx lr
|
||
|
|
|
||
|
|
08005b18 <memcpy>:
|
||
|
|
8005b18: 440a add r2, r1
|
||
|
|
8005b1a: 4291 cmp r1, r2
|
||
|
|
8005b1c: f100 33ff add.w r3, r0, #4294967295
|
||
|
|
8005b20: d100 bne.n 8005b24 <memcpy+0xc>
|
||
|
|
8005b22: 4770 bx lr
|
||
|
|
8005b24: b510 push {r4, lr}
|
||
|
|
8005b26: f811 4b01 ldrb.w r4, [r1], #1
|
||
|
|
8005b2a: f803 4f01 strb.w r4, [r3, #1]!
|
||
|
|
8005b2e: 4291 cmp r1, r2
|
||
|
|
8005b30: d1f9 bne.n 8005b26 <memcpy+0xe>
|
||
|
|
8005b32: bd10 pop {r4, pc}
|
||
|
|
|
||
|
|
08005b34 <memset>:
|
||
|
|
8005b34: 4402 add r2, r0
|
||
|
|
8005b36: 4603 mov r3, r0
|
||
|
|
8005b38: 4293 cmp r3, r2
|
||
|
|
8005b3a: d100 bne.n 8005b3e <memset+0xa>
|
||
|
|
8005b3c: 4770 bx lr
|
||
|
|
8005b3e: f803 1b01 strb.w r1, [r3], #1
|
||
|
|
8005b42: e7f9 b.n 8005b38 <memset+0x4>
|
||
|
|
|
||
|
|
08005b44 <cleanup_glue>:
|
||
|
|
8005b44: b538 push {r3, r4, r5, lr}
|
||
|
|
8005b46: 460c mov r4, r1
|
||
|
|
8005b48: 6809 ldr r1, [r1, #0]
|
||
|
|
8005b4a: 4605 mov r5, r0
|
||
|
|
8005b4c: b109 cbz r1, 8005b52 <cleanup_glue+0xe>
|
||
|
|
8005b4e: f7ff fff9 bl 8005b44 <cleanup_glue>
|
||
|
|
8005b52: 4621 mov r1, r4
|
||
|
|
8005b54: 4628 mov r0, r5
|
||
|
|
8005b56: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
||
|
|
8005b5a: f000 b869 b.w 8005c30 <_free_r>
|
||
|
|
...
|
||
|
|
|
||
|
|
08005b60 <_reclaim_reent>:
|
||
|
|
8005b60: 4b2c ldr r3, [pc, #176] ; (8005c14 <_reclaim_reent+0xb4>)
|
||
|
|
8005b62: 681b ldr r3, [r3, #0]
|
||
|
|
8005b64: 4283 cmp r3, r0
|
||
|
|
8005b66: b570 push {r4, r5, r6, lr}
|
||
|
|
8005b68: 4604 mov r4, r0
|
||
|
|
8005b6a: d051 beq.n 8005c10 <_reclaim_reent+0xb0>
|
||
|
|
8005b6c: 6a43 ldr r3, [r0, #36] ; 0x24
|
||
|
|
8005b6e: b143 cbz r3, 8005b82 <_reclaim_reent+0x22>
|
||
|
|
8005b70: 68db ldr r3, [r3, #12]
|
||
|
|
8005b72: 2b00 cmp r3, #0
|
||
|
|
8005b74: d14a bne.n 8005c0c <_reclaim_reent+0xac>
|
||
|
|
8005b76: 6a63 ldr r3, [r4, #36] ; 0x24
|
||
|
|
8005b78: 6819 ldr r1, [r3, #0]
|
||
|
|
8005b7a: b111 cbz r1, 8005b82 <_reclaim_reent+0x22>
|
||
|
|
8005b7c: 4620 mov r0, r4
|
||
|
|
8005b7e: f000 f857 bl 8005c30 <_free_r>
|
||
|
|
8005b82: 6961 ldr r1, [r4, #20]
|
||
|
|
8005b84: b111 cbz r1, 8005b8c <_reclaim_reent+0x2c>
|
||
|
|
8005b86: 4620 mov r0, r4
|
||
|
|
8005b88: f000 f852 bl 8005c30 <_free_r>
|
||
|
|
8005b8c: 6a61 ldr r1, [r4, #36] ; 0x24
|
||
|
|
8005b8e: b111 cbz r1, 8005b96 <_reclaim_reent+0x36>
|
||
|
|
8005b90: 4620 mov r0, r4
|
||
|
|
8005b92: f000 f84d bl 8005c30 <_free_r>
|
||
|
|
8005b96: 6ba1 ldr r1, [r4, #56] ; 0x38
|
||
|
|
8005b98: b111 cbz r1, 8005ba0 <_reclaim_reent+0x40>
|
||
|
|
8005b9a: 4620 mov r0, r4
|
||
|
|
8005b9c: f000 f848 bl 8005c30 <_free_r>
|
||
|
|
8005ba0: 6be1 ldr r1, [r4, #60] ; 0x3c
|
||
|
|
8005ba2: b111 cbz r1, 8005baa <_reclaim_reent+0x4a>
|
||
|
|
8005ba4: 4620 mov r0, r4
|
||
|
|
8005ba6: f000 f843 bl 8005c30 <_free_r>
|
||
|
|
8005baa: 6c21 ldr r1, [r4, #64] ; 0x40
|
||
|
|
8005bac: b111 cbz r1, 8005bb4 <_reclaim_reent+0x54>
|
||
|
|
8005bae: 4620 mov r0, r4
|
||
|
|
8005bb0: f000 f83e bl 8005c30 <_free_r>
|
||
|
|
8005bb4: 6de1 ldr r1, [r4, #92] ; 0x5c
|
||
|
|
8005bb6: b111 cbz r1, 8005bbe <_reclaim_reent+0x5e>
|
||
|
|
8005bb8: 4620 mov r0, r4
|
||
|
|
8005bba: f000 f839 bl 8005c30 <_free_r>
|
||
|
|
8005bbe: 6da1 ldr r1, [r4, #88] ; 0x58
|
||
|
|
8005bc0: b111 cbz r1, 8005bc8 <_reclaim_reent+0x68>
|
||
|
|
8005bc2: 4620 mov r0, r4
|
||
|
|
8005bc4: f000 f834 bl 8005c30 <_free_r>
|
||
|
|
8005bc8: 6b61 ldr r1, [r4, #52] ; 0x34
|
||
|
|
8005bca: b111 cbz r1, 8005bd2 <_reclaim_reent+0x72>
|
||
|
|
8005bcc: 4620 mov r0, r4
|
||
|
|
8005bce: f000 f82f bl 8005c30 <_free_r>
|
||
|
|
8005bd2: 69a3 ldr r3, [r4, #24]
|
||
|
|
8005bd4: b1e3 cbz r3, 8005c10 <_reclaim_reent+0xb0>
|
||
|
|
8005bd6: 6aa3 ldr r3, [r4, #40] ; 0x28
|
||
|
|
8005bd8: 4620 mov r0, r4
|
||
|
|
8005bda: 4798 blx r3
|
||
|
|
8005bdc: 6ca1 ldr r1, [r4, #72] ; 0x48
|
||
|
|
8005bde: b1b9 cbz r1, 8005c10 <_reclaim_reent+0xb0>
|
||
|
|
8005be0: 4620 mov r0, r4
|
||
|
|
8005be2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
|
||
|
|
8005be6: f7ff bfad b.w 8005b44 <cleanup_glue>
|
||
|
|
8005bea: 5949 ldr r1, [r1, r5]
|
||
|
|
8005bec: b941 cbnz r1, 8005c00 <_reclaim_reent+0xa0>
|
||
|
|
8005bee: 3504 adds r5, #4
|
||
|
|
8005bf0: 6a63 ldr r3, [r4, #36] ; 0x24
|
||
|
|
8005bf2: 2d80 cmp r5, #128 ; 0x80
|
||
|
|
8005bf4: 68d9 ldr r1, [r3, #12]
|
||
|
|
8005bf6: d1f8 bne.n 8005bea <_reclaim_reent+0x8a>
|
||
|
|
8005bf8: 4620 mov r0, r4
|
||
|
|
8005bfa: f000 f819 bl 8005c30 <_free_r>
|
||
|
|
8005bfe: e7ba b.n 8005b76 <_reclaim_reent+0x16>
|
||
|
|
8005c00: 680e ldr r6, [r1, #0]
|
||
|
|
8005c02: 4620 mov r0, r4
|
||
|
|
8005c04: f000 f814 bl 8005c30 <_free_r>
|
||
|
|
8005c08: 4631 mov r1, r6
|
||
|
|
8005c0a: e7ef b.n 8005bec <_reclaim_reent+0x8c>
|
||
|
|
8005c0c: 2500 movs r5, #0
|
||
|
|
8005c0e: e7ef b.n 8005bf0 <_reclaim_reent+0x90>
|
||
|
|
8005c10: bd70 pop {r4, r5, r6, pc}
|
||
|
|
8005c12: bf00 nop
|
||
|
|
8005c14: 20000020 .word 0x20000020
|
||
|
|
|
||
|
|
08005c18 <__malloc_lock>:
|
||
|
|
8005c18: 4801 ldr r0, [pc, #4] ; (8005c20 <__malloc_lock+0x8>)
|
||
|
|
8005c1a: f7ff bf7b b.w 8005b14 <__retarget_lock_acquire_recursive>
|
||
|
|
8005c1e: bf00 nop
|
||
|
|
8005c20: 20003e1c .word 0x20003e1c
|
||
|
|
|
||
|
|
08005c24 <__malloc_unlock>:
|
||
|
|
8005c24: 4801 ldr r0, [pc, #4] ; (8005c2c <__malloc_unlock+0x8>)
|
||
|
|
8005c26: f7ff bf76 b.w 8005b16 <__retarget_lock_release_recursive>
|
||
|
|
8005c2a: bf00 nop
|
||
|
|
8005c2c: 20003e1c .word 0x20003e1c
|
||
|
|
|
||
|
|
08005c30 <_free_r>:
|
||
|
|
8005c30: b537 push {r0, r1, r2, r4, r5, lr}
|
||
|
|
8005c32: 2900 cmp r1, #0
|
||
|
|
8005c34: d044 beq.n 8005cc0 <_free_r+0x90>
|
||
|
|
8005c36: f851 3c04 ldr.w r3, [r1, #-4]
|
||
|
|
8005c3a: 9001 str r0, [sp, #4]
|
||
|
|
8005c3c: 2b00 cmp r3, #0
|
||
|
|
8005c3e: f1a1 0404 sub.w r4, r1, #4
|
||
|
|
8005c42: bfb8 it lt
|
||
|
|
8005c44: 18e4 addlt r4, r4, r3
|
||
|
|
8005c46: f7ff ffe7 bl 8005c18 <__malloc_lock>
|
||
|
|
8005c4a: 4a1e ldr r2, [pc, #120] ; (8005cc4 <_free_r+0x94>)
|
||
|
|
8005c4c: 9801 ldr r0, [sp, #4]
|
||
|
|
8005c4e: 6813 ldr r3, [r2, #0]
|
||
|
|
8005c50: b933 cbnz r3, 8005c60 <_free_r+0x30>
|
||
|
|
8005c52: 6063 str r3, [r4, #4]
|
||
|
|
8005c54: 6014 str r4, [r2, #0]
|
||
|
|
8005c56: b003 add sp, #12
|
||
|
|
8005c58: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
|
||
|
|
8005c5c: f7ff bfe2 b.w 8005c24 <__malloc_unlock>
|
||
|
|
8005c60: 42a3 cmp r3, r4
|
||
|
|
8005c62: d908 bls.n 8005c76 <_free_r+0x46>
|
||
|
|
8005c64: 6825 ldr r5, [r4, #0]
|
||
|
|
8005c66: 1961 adds r1, r4, r5
|
||
|
|
8005c68: 428b cmp r3, r1
|
||
|
|
8005c6a: bf01 itttt eq
|
||
|
|
8005c6c: 6819 ldreq r1, [r3, #0]
|
||
|
|
8005c6e: 685b ldreq r3, [r3, #4]
|
||
|
|
8005c70: 1949 addeq r1, r1, r5
|
||
|
|
8005c72: 6021 streq r1, [r4, #0]
|
||
|
|
8005c74: e7ed b.n 8005c52 <_free_r+0x22>
|
||
|
|
8005c76: 461a mov r2, r3
|
||
|
|
8005c78: 685b ldr r3, [r3, #4]
|
||
|
|
8005c7a: b10b cbz r3, 8005c80 <_free_r+0x50>
|
||
|
|
8005c7c: 42a3 cmp r3, r4
|
||
|
|
8005c7e: d9fa bls.n 8005c76 <_free_r+0x46>
|
||
|
|
8005c80: 6811 ldr r1, [r2, #0]
|
||
|
|
8005c82: 1855 adds r5, r2, r1
|
||
|
|
8005c84: 42a5 cmp r5, r4
|
||
|
|
8005c86: d10b bne.n 8005ca0 <_free_r+0x70>
|
||
|
|
8005c88: 6824 ldr r4, [r4, #0]
|
||
|
|
8005c8a: 4421 add r1, r4
|
||
|
|
8005c8c: 1854 adds r4, r2, r1
|
||
|
|
8005c8e: 42a3 cmp r3, r4
|
||
|
|
8005c90: 6011 str r1, [r2, #0]
|
||
|
|
8005c92: d1e0 bne.n 8005c56 <_free_r+0x26>
|
||
|
|
8005c94: 681c ldr r4, [r3, #0]
|
||
|
|
8005c96: 685b ldr r3, [r3, #4]
|
||
|
|
8005c98: 6053 str r3, [r2, #4]
|
||
|
|
8005c9a: 4421 add r1, r4
|
||
|
|
8005c9c: 6011 str r1, [r2, #0]
|
||
|
|
8005c9e: e7da b.n 8005c56 <_free_r+0x26>
|
||
|
|
8005ca0: d902 bls.n 8005ca8 <_free_r+0x78>
|
||
|
|
8005ca2: 230c movs r3, #12
|
||
|
|
8005ca4: 6003 str r3, [r0, #0]
|
||
|
|
8005ca6: e7d6 b.n 8005c56 <_free_r+0x26>
|
||
|
|
8005ca8: 6825 ldr r5, [r4, #0]
|
||
|
|
8005caa: 1961 adds r1, r4, r5
|
||
|
|
8005cac: 428b cmp r3, r1
|
||
|
|
8005cae: bf04 itt eq
|
||
|
|
8005cb0: 6819 ldreq r1, [r3, #0]
|
||
|
|
8005cb2: 685b ldreq r3, [r3, #4]
|
||
|
|
8005cb4: 6063 str r3, [r4, #4]
|
||
|
|
8005cb6: bf04 itt eq
|
||
|
|
8005cb8: 1949 addeq r1, r1, r5
|
||
|
|
8005cba: 6021 streq r1, [r4, #0]
|
||
|
|
8005cbc: 6054 str r4, [r2, #4]
|
||
|
|
8005cbe: e7ca b.n 8005c56 <_free_r+0x26>
|
||
|
|
8005cc0: b003 add sp, #12
|
||
|
|
8005cc2: bd30 pop {r4, r5, pc}
|
||
|
|
8005cc4: 20003e20 .word 0x20003e20
|
||
|
|
|
||
|
|
08005cc8 <_init>:
|
||
|
|
8005cc8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
||
|
|
8005cca: bf00 nop
|
||
|
|
8005ccc: bcf8 pop {r3, r4, r5, r6, r7}
|
||
|
|
8005cce: bc08 pop {r3}
|
||
|
|
8005cd0: 469e mov lr, r3
|
||
|
|
8005cd2: 4770 bx lr
|
||
|
|
|
||
|
|
08005cd4 <_fini>:
|
||
|
|
8005cd4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
||
|
|
8005cd6: bf00 nop
|
||
|
|
8005cd8: bcf8 pop {r3, r4, r5, r6, r7}
|
||
|
|
8005cda: bc08 pop {r3}
|
||
|
|
8005cdc: 469e mov lr, r3
|
||
|
|
8005cde: 4770 bx lr
|