Katedra Mikroelektroniki i Technik Informatycznych Politechniki Lódzkiej; Komputerowe projektowanie ukladów

*

*Features:

*Low input bias current =

30pA

*Low input offset current =

3pA

*High input impedance =

1Tohm

*Low input offset voltage =

1mV

*

****************INPUT STAGE**************

*

IOS 2 1 3P

*^Input offset current

R1 1 3 1E12

R2 3 2 1E12

I1 99 4 100U

J1 5 2 4 JX

J2 6 7 4 JX

R3 5 50 20K

R4 6 50 20K

*Fp2=12 MHz

C4 5 6 3.31573E-13

*

***********COMMON MODE EFFECT***********

*

I2 99 50 4.65MA

*^Quiescent supply current

EOS 7 1 POLY(1) 16 49 3E-3 1

*Input offset voltage.^

R8 99 49 50K

R9 49 50 50K

*

*********OUTPUT VOLTAGE LIMITING********

V2 99 8 2.63

D1 9 8 DX

D2 10 9 DX

V3 10 50 2.63

*

**************SECOND STAGE**************

*

EH 99 98 99 49 1

F1 9 98 POLY(1) VA3 0 0 0 8.1291E7

G1 98 9 5 6 2E-3

R5 98 9 100MEG

VA3 9 11 0

*Fp1=224 HZ

C3 98 11 7.10513P

*

***************POLE STAGE***************

*

*Fp3=42 MHz

G3 98 15 9 49 1E-6

R12 98 15 1MEG

C5 98 15 8.3766E-15

*

*********COMMON-MODE ZERO STAGE*********

*

G4 98 16 3 49 1E-8

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